FAN7930CMX - Fairchild Semiconductor Corporation

July 2011

FAN7930C • Rev. 1.0.1

FAN7930C — Critical Conduction Mode PFC Controller

FAN7930C

Critical Conduction Mode PFC Controller

Features

 PFC-Ready Signal

 Input Voltage Absent Detection

 Maximum Switching Frequency Limitation

 Internal Soft-Start and Startup without Overshoot

 Internal Total Harmonic Distortion (THD) Optimizer

 Precise Adjustable Output Over-Voltage Protection

 Open-Feedback Protection and Disable Function

 Zero-Current Detector (ZCD)

 150μs Internal Startup Timer

 MOSFET Over-Current Protection (OCP)

 Under-Voltage Lockout with 3.5V Hysteresis

 Low Startup and Operating Current

 Totem-Pole Output with High State Clamp

 +500/-800mA Peak Gate Drive Current

 8-Pin SOP

Applications

 Adapter

 Ballast

 LCD TV, CRT TV

 SMPS

Description

The FAN7930C is an active power factor correction

(PFC) controller for boost PFC applications that operate

in critical conduction mode (CRM). It uses a voltage-

mode PWM that compares an internal ramp signal with

the error amplifier output to generate a MOSFET turn-off

signal. Because the voltage-mode CRM PFC controller

does not need rectified AC line voltage information, it

saves the power loss of an input voltage sensing network

necessary for a current-mode CRM PFC controller.

FAN7930C provides over-voltage protection (OVP),

open-feedback protection, over-current protection

(OCP), input-voltage-absent detection, and under-

voltage lockout protection (UVLO). The PFC-ready pin

can be used to trigger other power stages when PFC

output voltage reaches the proper level with hysteresis.

The FAN7930C can be disabled if the INV pin voltage is

lower than 0.45V and the operating current decreases to

a very low level. Using a new variable on-time control

method, THD is lower than the conventional CRM boost

PFC ICs.

Related Resources

AN-8035 — Design Consideration for Boundary

Conduction Mode PFC Using F AN7930

Ordering Information

Part Number Operating

Temperature Range Top Mark Package Packing

Method

FAN7930CM -40 to +125°C FAN7930C 8-Lead Small Outline Package (SOP) Rail

FAN7930CMX Tape & Reel

FAN7930C • Rev. 1.0.1 2

FAN7930C — Critical Conduction Mode PFC Controller

Application Diagram

Figure 1. Typical Boost PFC Application

Internal Block Diagram

Figure 2. Functional Block Diagram

FAN7930C • Rev. 1.0.1 3

FAN7930C — Critical Conduction Mode PFC Controller

Pin Configuration

Figure 3. Pin Configuration (Top View)

Pin Definitions

Pin # Name Description

1 INV

This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter

should be resistively divided to 2.5V.

2 RDY

This pin is used to detect PFC output voltage reaching a pre-determined value. When output

voltage reaches 89% of rated output voltage, this pin is pulled HIGH, which is an (open-drain)

output type.

3 COMP

This pin is the output of the transconductance error amplifier. Components for the output voltage

compensation should be connected between this pin and GND.

4 CS

This pin is the input of the over-current protection comparator. The MOSFET current is sensed

using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is

included to filter switching noise.

5 ZCD

This pin is the input of the zero-current detection block. If the voltage of this pin goes higher than

1.5V, then goes lower than 1.4V, the MOSFET is turned on.

6 GND

This pin is used for the ground potential of all the pins. For proper operation, the signal ground

and the power ground should be separated.

7 OUT

This pin is the gate drive output. The peak sourcing and sinking current levels are +500mA and

-800mA, respectively. For proper operation, the stray inductance in the gate driving path must be

minimized.

8 VCC This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.

FAN7930C • Rev. 1.0.1 4

FAN7930C — Critical Conduction Mode PFC Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage VZ V

IOH, IOL Peak Drive Output Current -800 +500 mA

ICLAMP Driver Output Clamping Diodes VO>VCC or VO<-0.3V -10 +10 mA

IDET Detector Clamping Diodes -10 +10 mA

VIN

RDY Pin(1) VZ

Error Amplifier Input, Output and ZCD(1) -0.3 8.0

CS Input Voltage(2) -10.0 6.0

TJ Operating Junction Temperature +150 °C

TA Operating Temperature Range -40 +125 °C

TSTG Storage Temperature Range -65 +150 °C

ESD Electrostatic Discharge

Capability

Human Body Model, JESD22-A114 2.5 kV

Charged Device Model, JESD22-C101 2.0

Notes:

1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50mA.

2. In case of DC input, acceptable input range is -0.3V~6V: within 100ns -10V~6V is acceptable, but electrical

specifications are not guaranteed during such a short time.

Thermal Impedance

Symbol Parameter Min. Max. Unit

JA Thermal Resistance, Junction-to-Ambient(3) 150 °C/W

Note:

3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.

FAN7930C • Rev. 1.0.1 5

FAN7930C — Critical Conduction Mode PFC Controller

Electrical Characteristics

VCC = 14V, TA = -40°C~+125°C, unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

VCC Section

VSTART Start Threshold Voltage VCC Increasing 11 12 13 V

VSTOP Stop Threshold Voltage VCC Decreasing 7.5 8.5 9.5 V

HYUVLO UVLO Hysteresis 3.0 3.5 4.0 V

VZ Zener Voltage ICC=20mA 20 22 24 V

VOP Recommended Operating Range 13 20 V

Supply Current Section

ISTART Startup Supply Current VCC=VSTART-0.2V 120 190 µA

IOP Operating Supply Current Output Not Switching 1.5 3.0 mA

IDOP Dynamic Operating Supply Current 50kHZ, CI=1nF 2.5 4.0 mA

IOPDIS Operating Current at Disable VINV=0V 90 160 230 µA

Error Amplifier Section

VREF1 Voltage Feedback Input Threshold1 TA=25°C 2.465 2.500 2.535 V

VREF1 Line Regulation VCC=14V~20V 0.1 10.0 mV

VREF2 Temperature Stability of VREF1(4) 20 mV

IEA,BS Input Bias Current VINV=1V~4V -0.5 0.5 µA

IEAS,SR Output Source Current VINV=VREF -0.1V -12 µA

IEAS,SK Output Sink Current VINV=VREF +0.1V 12 µA

VEAH Output Upper Clamp Voltage VINV=1V, VCS=0V 6.0 6.5 7.0 V

VEAZ Zero-Duty Cycle Output Voltage 0.9 1.0 1.1 V

gm Transconductance(4) 90 115 140 µmho

Maximum On-Time Section

tON,MAX1 Maximum On-Time Programming 1 TA=25°C, VZCD=1V 35.5 41.5 47.5 µs

tON,MAX2 Maximum On-Time Programming 2 TA=25°C,

IZCD=0.469mA 11.2 13.0 14.8 µs

Current-Sense Section

VCS Current-Sense Input Threshold

Voltage Limit 0.7 0.8 0.9 V

ICS,BS Input Bias Current VCS=0V~1V -1.0 -0.1 1.0 µA

tCS,D Current-Sense Delay to Output(4) dV/dt=1V/100ns,

from 0V to 5V 350 500 ns

Continued on the following page…

FAN7930C • Rev. 1.0.1 6

FAN7930C — Critical Conduction Mode PFC Controller

Electrical Characteristics

VCC = 14V, TA = -40°C~+125°C, unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

Zero-Current Detect Section

VZCD Input Voltage Threshold(4) 1.35 1.50 1.65 V

HYZCD Detect Hysteresis(4) 0.05 0.10 0.15 V

VCLAMPH Input High Clamp Voltage IDET=3mA 5.5 6.2 7.5 V

VCLAMPL Input Low Clamp Voltage IDET= -3mA 0 0.65 1.00 V

IZCD,BS Input Bias Current VZCD=1V~5V -1.0 -0.1 1.0 µA

IZCD,SR Source Current Capability(4) T

A=25°C -4 mA

IZCD,SK Sink Current Capability(4) T

A=25°C 10 mA

tZCD,D Maximum Delay From ZCD to Output

Turn-On(4)

dV/dt=-1V/100ns,

from 5V to 0V 100 200 ns

Output Section

VOH Output Voltage High IO=-100mA, TA=25°C 9.2 11.0 12.8 V

VOL Output Voltage Low IO=200mA, TA=25°C 1.0 2.5 V

tRISE Rising Time(4) C

IN=1nF 50 100 ns

tFALL Falling Time(4) C

IN=1nF 50 100 ns

VO,MAX Maximum Output Voltage VCC=20V, IO=100µA 11.5 13.0 14.5 V

VO,UVLO Output Voltage with UVLO Activated VCC=5V, IO=100µA 1 V

Restart / Maximum Switching Frequency Limit Section

tRST Restart Timer Delay 50 150 300 µs

fMAX Maximum Switching Frequency(4) 250 300 350 kHz

RDY Pin

IRDY,SK Output Sink Current 1 2 4 mA

VRDY,SAT Output Saturation Voltage IRDY,SK=2mA 320 500 mV

IRDY,LK Output Leakage Current Output High Impedance 1 µA

Soft-Start Timer Section

tSS Internal Soft-Soft(4) 3 5 7 ms

UVLO Section

VRDY Output Ready Voltage 2.166 2.240 2.314 V

HYRDY Output Ready Hysteresis 0.189 V

Protections

VOVP OVP Threshold Voltage TA=25°C 2.620 2.675 2.730 V

HYOVP OVP Hysteresis TA=25°C 0.120 0.175 0.230 V

VEN Enable Threshold Voltage 0.40 0.45 0.50 V

HYEN Enable Hysteresis 0.050 0.100 0.150 V

TSD Thermal Shutdown Temperature(4) 125 140 155 °C

THYS Hysteresis Temperature of TSD(4) 60 °C

Note:

4. These parameters, although guaranteed by design, are not production tested.

FAN7930C • Rev. 1.0.1 7

FAN7930C — Critical Conduction Mode PFC Controller

Comparison of FAN7530 and FAN7930C

Function FAN7530 FAN7930C FAN7930C Advantages

PFC Ready Pin None Integrated

No External Circuit for PFC Output UVLO

 Reduce Power Loss and BOM Cost Caused by

PFC Out UVLO Circuit

 Versatile Open-Drain Pin

Frequency Limit None Integrated

Abnormal CCM Operation Prohibited

 Abnormal Inductor Current Accumulation can be

Prohibited

VIN-Absent Detection None Integrated

Increase System Reliability by testing for input

supply voltage

 Guarantee Stable Operation at Short Electric

Power Failure

Soft-Start and

Overshoot

Prevention

None Integrated

Reduce Voltage and Current Stress at Startup

 Eliminate Audible Noise due to Unwanted OVP

Triggering

THD Optimizer External Internal No External Resistor is Needed

TSD None

140°C with 60°C

Hysteresis

Stable and Reliable TSD Operation

 Converter Temperature Range Limited Range

Comparison between FAN7930 and FAN7930C

Function FAN7930 FAN7930C FAN7930C Remark

RDY Threshold 2.240V 2.240V

If PFC rated output voltage is assumed 390V:

FAN7930: VRDY_HIGH trigger voltage = 349V

VRDY_LOW trigger voltage = 256V

FAN7930C: VRDY_HIGH trigger voltage = 349V

VRDY_LOW trigger voltage = 320V

RDY Hysteresis 0.600V 0.189V

Control Range

Compensation None Integrated

FAN7930C • Rev. 1.0.1 8

FAN7930C — Critical Conduction Mode PFC Controller

Typical Performance Characteristics

Figure 4.

oltage Feedback Input Threshold 1 (VREF1)

vs. TA

Figure 5. Sta

t Threshold Voltage (

START) vs. TA

Figure 6. Stop Threshold Voltage (

STOP) vs. TAFigure 7. Startup Supply Current (ISTART) vs. TA

Figure 8. Operating Supply Current (IOP) vs. TAFigure 9. Output Upper Clamp Voltage (VEAH) vs. TA

FAN7930C • Rev. 1.0.1 9

FAN7930C — Critical Conduction Mode PFC Controller

Typical Performance Characteristics

Figure 10. Zero Duty Cycle Output Voltage (VEAZ)

vs. TA

Figure 11. Maximum On-Time Program 1 (tON,MAX1)

vs. TA

Figure 12. Maximum On-Time Program 2 (tON,MAX2)

vs. TA

Figure 13. Current-Sense Input Threshold Voltage

Limit (VCS) vs. TA

Figure 14. Input High Clamp Voltage (

CLAMPH) vs. TAFigure 15. Input Low Clamp Voltage (

CLAMPL) vs. TA

FAN7930C • Rev. 1.0.1 10

FAN7930C — Critical Conduction Mode PFC Controller

Typical Performance Characteristics

Figure 16. Output Voltage High (VOH) vs. TAFigure 17. Output Voltage Low (

OL) vs. TA

Figure 18. Restart Timer Delay (tRST) vs. TAFigure 19. Output Ready Voltage (VRDY) vs. TA

Figure 20. Output Saturation Voltage (VRDY,SAT)

vs. TA

Figure 21. OVP Threshold Voltage (

OVP) vs. TA

FAN7930C • Rev. 1.0.1 11

FAN7930C — Critical Conduction Mode PFC Controller

Applications Information

1. Startup: Normally, supply voltage (VCC) of a PFC

block is fed from the additional power supply, which can

be called standby power. Without this standby power,

auxiliary winding for zero current detection can be used

as a supply source. Once the supply voltage of the PFC

block exceeds 12V, internal operation is enabled until

the voltage drops to 8.5V. If VCC exceeds VZ, 20mA

current is sinking from VCC.

Figure 22. Startup Circuit

2. INV Block: Scaled-down voltage from the output is

the input for the INV pin. Many functions are embedded

based on the INV pin: transconductance amplifier,

output OVP comparator, disable comparator, and output

UVLO comparator.

For the output voltage control, a transconductance

amplifier is used instead of the conventional voltage

amplifier. The transconductance amplifier (voltage-

controlled current source) aids the implementation of the

OVP and disable functions. The output current of the

amplifier changes according to the voltage difference of

the inverting and non-inverting input of the amplifier. To

cancel down the line input voltage effect on power factor

correction, the effective control response of the PFC

block should be slower than the line frequency and this

conflicts with the transient response of controller. Two-

pole one-zero type compensation may be used to meet

both requirements.

The OVP comparator shuts down the output drive block

when the voltage of the INV pin is higher than 2.675V

and there is 0.175V hysteresis. The disable comparator

disables operation when the voltage of the inverting

input is lower than 0.35V and there is 100mV hysteresis.

An external small-signal MOSFET can be used to

disable the IC, as shown in Figure 23. The IC operating

current decreases to reduce power consumption if the

IC is disabled. Figure 24 is the timing chart of the

internal circuit near the INV pin when rated PFC output

voltage is 390VDC and VCC supply voltage is 15V.

Figure 23. Circuit Around INV Pin

Figure 24. Timing Chart for INV Block

3. RDY Output: When the INV voltage is higher than

2.24V, RDY output is triggered HIGH and lasts until the

INV voltage is lower than 2.051V. When input AC

voltage is quite high, for example 240VAC, PFC output

voltage is always higher than RDY threshold, regardless

of boost converter operation. In this case, the INV

voltage is already higher than 2.24V before PFC VCC

touches VSTART; however, RDY output is not triggered to

HIGH until VCC touches VSTART. After boost converter

operation stops, RDY is not pulled LOW because the

INV voltage is higher than the RDY threshold. When VCC

of the PFC drops below 5V, RDY is pulled LOW even

though PFC output voltage is higher than threshold. The

RDY pin output is open drain, so needs an external pull-

up resistor to supply the proper power source. The RDY

pin output remains floating until VCC is higher than 2V.

FAN7930C • Rev. 1.0.1 12

FAN7930C — Critical Conduction Mode PFC Controller

Figure 25. Two Cases of RDY Triggered HIGH

Figure 26. Two Cases of RDY Triggered LOW

4. Zero-Current Detection: Zero-current detection

(ZCD) generates the turn-on signal of the MOSFET

when the boost inductor current reaches zero using an

auxiliary winding coupled with the inductor. When the

power switch turns on, negative voltage is induced at the

auxiliary winding due to the opposite winding direction

(see Equation 1). Positive voltage is induced (see

Equation 2) when the power switch turns off.

IND

AUX

AUX V

V (1)



ACPFCOUT

IND

AUX

AUX VV

V (2)

where:

VAUX is the auxiliary winding voltage;

TIND is boost inductor turns;

TIND auxiliary winding turns;

VAC is input voltage for PFC converter; and

VOUT_PFC is output voltage from the PFC converter.

Figure 27. Circuit Near ZCD

Because auxiliary winding voltage can swing from

negative to positive voltage, the internal block in ZCD

pin has both positive and negative voltage clamping

circuits. When the auxiliary voltage is negative, internal

circuit clamps the negative voltage at the ZCD pin

around 0.65V by sourcing current to the serial resistor

between the ZCD pin and the auxiliary winding. When

the auxiliary voltage is higher than 6.5V, current is

sinked through a resistor from the auxiliary winding to

the ZCD pin.

Figure 28. Auxiliary Voltage Depends on

MOSFET Switching

The auxiliary winding voltage is used to check the boost

inductor current zero instance. When boost inductor

current becomes zero, there is a resonance between

boost inductor and all capacitors at the MOSFET drain

pin: including COSS of the MOSFET; an external

capacitor at the D-S pin to reduce the voltage rising and

falling slope of the MOSFET; a parasitic capacitor at

inductor; and so on to improve performance. Resonated

voltage is reflected to the auxiliary winding and can be

used for detecting zero current of boost inductor and

valley position of MOSFET voltage stress.

FAN7930C • Rev. 1.0.1 13

FAN7930C — Critical Conduction Mode PFC Controller

For valley detection, a minor delay by the resistor and

capacitor is needed. A capacitor increases the noise

immunity at the ZCD pin. If ZCD voltage is higher than

1.5V, an internal ZCD comparator output becomes

HIGH and LOW when the ZCD goes below 1.4V. At the

falling edge of comparator output, internal logic turns on

the MOSFET.

Figure 29. Auxiliary Voltage Threshold

When no ZCD signal is available, the PFC controller

cannot turn on the MOSFET, so the controller checks

every switching off time and forces MOSFET turn on

when the off time is longer than 150μs. This is called the

restart timer, which triggers MOSFET turn-on at startup

and may be used at the input voltage zero-cross period.

s150



Figure 30. Restart Timer at Startup

Because the MOSFET turn-on depends on the ZCD

input, switching frequency may increase to higher than

several megahertz due to the miss-triggering or noise

on the nearby ZCD pin. If the switching frequency is

higher than needed for critical conduction mode (CRM),

operation mode shifts to continuous conduction mode

(CCM). In CCM, unlike CRM where the boost inductor

current is reset to zero at the next switch on; inductor

current builds up at every switching cycle and can be

raised to very high current that exceeds the current

rating of the power switch or diode. This can seriously

damage the power switch and result in burn down. To

avoid this, maximum switching frequency limitation is

embedded. If ZCD signal is applied again within 3.3μs

after the previous rising edge of gate signal, this signal

is ignored internally and FAN7930C waits for another

ZCD signal. This slightly degrades the power factor

performance at light load and high input voltage.

Figure 31. Maximum Switching Frequency

Limit Operation

5. Control: The scaled output is compared with the

internal reference voltage and sinking or sourcing

current is generated from the COMP pin by the

transconductance amplifier. The error amplifier output is

compared with the internal sawtooth waveform to give

proper turn-on time based on the controller.

Figure 32. Control Circuit

Unlike a conventional voltage-mode PWM controller,

FAN7930C turns on the MOSFET at the falling edge of

ZCD signal. On-instance is determined by the external

signal and the turn-on time lasts until the error amplifier

output (VCOMP) and sawtooth waveform meet. When

load is heavy, output voltage decreases, scaled output

decreases, COMP voltage increases to compensate low

output, turn-on time lengthens to give more inductor

turn-on time, and increased inductor current raises the

output voltage. This is how PFC negative feedback

controller regulates output.

The maximum of VCOMP is limited to 6.5V, which dictates

the maximum turn-on time, and switching stops when

VCOMP is lower than 1.0V.

FAN7930C • Rev. 1.0.1 14

FAN7930C — Critical Conduction Mode PFC Controller

s/V155.0



Figure 33. Turn-On Time Determination

The roles of PFC controller are regulating output voltage

and input current shaping to increase power factor. Duty

control based on the output voltage should be fast

enough to compensate output voltage dip or overshoot.

For the power factor, however, the control loop must not

react to the fluctuating AC input voltage. These two

requirements conflict; therefore, when designing a

feedback loop, the feedback loop should be least 10

times slower than AC line frequency. That slow

response is made by C1 at compensator. R1 makes

gain boost around operation region and C2 attenuates

gain at higher frequency. Boost gain by R1 helps raise

the response time and improves phase margin.

Figure 34. Compensators Gain Curve

For the transconductance error amplifier side, gain

changes based on differential input. When the error is

large, gain is large to make the output dip or peak to

suppress quickly. When the error is small, low gain is

used to improve power factor performance.

mho250



mho115



Figure 35. Gain Characteristic

6. Soft-Start: When VCC reaches VSTART, the internal

reference voltage is increased like a stair step for 5ms.

As a result, VCOMP is also raised gradually and MOSFET

turn-on time increases smoothly. This reduces voltage

and current stress on the power switch during startup.

Figure 36. Soft-Start Sequence

7. Startup without Overshoot: Feedback control speed

of PFC is quite slow. Due to the slow response, there is

a gap between output voltage and feedback control.

That is why over-voltage protection (OVP) is critical at

the PFC controller and voltage dip caused by fast load

changes from light to heavy is diminished by a bulk

capacitor. OVP is easily triggered at startup phase.

Operation on and off by OVP at startup may cause

audible noise and can increase voltage stress at startup,

which is normally higher than in normal operation. This

operation is better when soft-start time is very long.

However, too much startup time enlarges the output

voltage building time at light load. FAN7930C has

overshoot avoidance at startup. During startup, the

feedback loop is controlled by an internal proportional

gain controller and, when the output voltage reaches the

rated value, it switches to an external compensator after

a transition time of 30ms. This internal proportional gain

controller eliminates overshoot at startup and an

external conventional compensator takes over

successfully afterward.

FAN7930C • Rev. 1.0.1 15

FAN7930C — Critical Conduction Mode PFC Controller

Figure 37. Startup Control without Overshoot

8. THD Optimization: Total Harmonic Distortion (THD)

is the factor that dictates how closely input current

shape matches sinusoidal form. The turn-on time of the

PFC controller is almost constant over one AC line

period due to the extremely low feedback control

response. The turn-off time is determined by the current

decrease slope of the boost inductor made by the input

voltage and output voltage. Once inductor current

becomes zero, resonance between COSS and the boost

inductor makes oscillating waveforms at the drain pin

and auxiliary winding. By checking the auxiliary winding

voltage through the ZCD pin, the controller can check

the zero current of boost inductor. At the same time, a

minor delay is inserted to determine the valley position

of drain voltage. The input and output voltage difference

is at its maximum at the zero cross point of AC input

voltage. The current decrease slope is steep near the

zero cross region and more negative inductor current

flows during a drain voltage valley detection time. Such

a negative inductor current cancels down the positive

current flows and input current becomes zero, called

“zero-cross distortion” in PFC.

Figure 38. Input and Output Current Near Input

Voltage Peak

Figure 39. Input and Output Current Near Input

Voltage Peak Zero Cross

To improve this, lengthened turn-on time near the zero

cross region is a well-known technique, though the

method may vary and may be proprietary. FAN7930C

optimizes this by sourcing current through the ZCD pin.

Auxiliary winding voltage becomes negative when the

MOSFET turns on and is proportional to input voltage.

The negative clamping circuit of ZCD outputs the

current to maintain the ZCD voltage at a fixed value.

The sourcing current from the ZCD is directly

proportional to the input voltage. Some portion of this

current is applied to the internal sawtooth generator,

together with a fixed-current source. Theoretically, the

fixed-current source and the capacitor at sawtooth

generator determine the maximum turn-on time when no

current is sourcing at ZCD clamp circuit and available

turn-on time gets shorter proportional to the ZCD

sourcing current.

Figure 40. Circuit of THD Optimizer

FAN7930C • Rev. 1.0.1 16

FAN7930C — Critical Conduction Mode PFC Controller

Figure 41. Effect of THD Optimizer

By THD optimizer, turn-on time over one AC line period

is proportionally changed, depending on input voltage.

Near zero cross, lengthened turn-on time improves THD

performance.

9. VIN Absent Detection: To save power loss caused by

input voltage sensing resistors and to optimize THD, the

FAN7930C omits AC input voltage detection. Therefore,

no information about AC input is available from the

internal controller. In many cases, the VCC of PFC

controller is supplied by a independent power source,

like standby power. In this scheme, some mismatch

may exist. For example, when the electric power is

suddenly interrupted during two or three AC line

periods; VCC is still live during that time, but output

voltage drops because there is no input power source.

Consequently, the control loop tries to compensate for

the output voltage drop and VCOMP reaches its

maximum. This lasts until AC input voltage is live again.

When AC input voltage is live again, high VCOMP allows

high switching current and more stress is put on the

MOSFET and diode. To protect against this, FAN7930C

checks if the input AC voltage exists. If input does not

exist, soft-start is reset and waits until AC input is live

again. Soft-start manages the turn-on time for smooth

operation when it detects AC input is applied again and

applies less voltage and current stress on startup.

10. Current Sense: The MOSFET current is sensed

using an external sensing resistor for over-current

protection. If the CS pin voltage is higher than 0.8V, the

over-current protection comparator generates a

protection signal. An internal RC filter of 40kΩ and 8pF

is included to filter switching noise.

11. Gate Driver Output: FAN7930C contains a single

totem-pole output stage designed for a direct drive of

the power MOSFET. The drive output is capable of up

to +500/-800mA peak current with a typical rise and fall

time of 50ns with 1nF load. The output voltage is

clamped to 13V to protect the MOSFET gate even if the

VCC voltage is higher than 13V.

VIN

VOUT

VAUX

MOSFET gate

IDS

fMIN

DMAX

VIN Absence Detected

NewVCOMP

Though VIN is

eliminated, operation of

controller is normal due

to the large bypass

capacitor.

FAN7930 Rev.00

fMIN DMIN

Smooth

Soft-Start

Figure 42. Operation without VIN Absent Circuit

Figure 43. Operation with VIN Absent Circuit

FAN7930C • Rev. 1.0.1 17

FAN7930C — Critical Conduction Mode PFC Controller

PCB Layout Guide

PFC block normally handles high switching current and

the voltage low energy signal path can be affected by

the high energy path. Cautious PCB layout is mandatory

for stable operation.

1. The gate drive path should be as short as possible.

The closed-loop that runs from the gate driver,

MOSFET gate, and MOSFET source to ground of

PFC controller should be as close as possible. This

is also crossing point between power ground and

signal ground. Power ground path from the bridge

diode to the output bulk capacitor should be short

and wide. The sharing position between power

ground and signal ground should be only at one

position to avoid ground loop noise. Signal path of

PFC controller should be short and wide for

external components to contact.

2. PFC output voltage sensing resistor is normally

high to reduce current consumption. This path can

be affected by external noise. To reduce noise

potential at the INV pin, a shorter path for output

sensing is recommended. If a shorter path is not

possible, place some dividing resistors between

PFC output and the INV pin — closer to the INV pin

is better. Relative high voltage close to the INV pin

can be helpful.

3. ZCD path is recommended close to auxiliary

winding from boost inductor and to the ZCD pin. If

that is difficult, place a small capacitor (below 50pF)

to reduce noise.

4. The switching current sense path should not share

with another path to avoid interference. Some

additional components may be needed to reduce

the noise level applied to the CS pin.

5. A stabilizing capacitor for VCC is recommended as

close as possible to the VCC and ground pins. If it is

difficult, place the SMD capacitor as close to the

corresponding pins as possible.

Figure 44. Recommended PCB Layout

FAN7930C • Rev. 1.0.1 18

FAN7930C — Critical Conduction Mode PFC Controller

Typical Application Circuit

Application Device

Input Voltage

Range

Rated Output

Power

Output Voltage

(Maximum

Current)

LCD TV Power Supply FAN7930C 90-265VAC 195W 390V (0.5A)

Features

 Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 95% at universal input.

 Power factor at rated load is higher than 0.98 at universal input.

 Total Harmonic Distortion (THD) at rated load is lower than 15% at universal input.

Key Design Notes

 When auxiliary VCC supply is not available, VCC power can be supplied through Zero Current Detect (ZCD)

winding. The power consumption of R103 is quite high, so its power rating needs checking.

 Because the input bias current of INV pin is almost zero, output voltage sensing resistors (R112~R115) should

be as high as possible. However, too-high resistance makes the node susceptible to noise. Resistor values need

to strike a balance between power consumption and noise immunity.

 Quick-charge diode D106 can be eliminated. Without D106, system operation is normal due to the controller’s

highly reliable protection features.

1. Schematic

ZNR101

,10D471

230mH,

49:6

D105

600V 8A

VAUX

DC OUTPUT

Q101

FCPF

20N60

D106

600V 3A

FS101,

250V,5

R101,1M-

C101,

220nF

C114

,2.2n

LF101

,23mH

C102,

680nF

TH101

,5D15

BD101,

600V,15A

C1030,68m

F,630Vdc

C107

,33m

C105, 100nF

R107

,10k

C108,

220nF

C109

,47n

R110,10k

R109

R108

4.7

D103,1N414

D104,1N414

C112,470p

R111

0.08, 5W

C110,1n

R115

75k

R112

3.9M

C111

220mF, 450V

LP101,EER3124N

R113

3.9M

R114

3.9M

R104,

30k

FAN7930C

Com

pINV

VCC Out

GND

DCS

C115

,2.2n

R103,

10k,1W

D102,

UF4004

C104,

12nF

D101,1N474

R102,

330k

Circuit for VCC. If external VCC is used, this circuit is not needed.

VCC for another power stage

Circuit for VCC for another power stage thus components structure and values may vary.

Optional

Figure 45. Demonstration Circuit

FAN7930C • Rev. 1.0.1 19

FAN7930C — Critical Conduction Mode PFC Controller

2. Transformer

Figure 46. Transformer Schematic Diagram

3. Winding Specification

Position No Pin (S → F) Wire Turns Winding

Method

Barrier Tape

TOP BOT Ts

Bottom

Np 9, 10 → 7, 8 0.1φ×50 49 Solenoid Winding 1

Insulation: Polyester Tape t = 0.025mm, 3 Layers

Top

NAUX 2 → 4 0.3φ 6 Solenoid Winding

Insulation: Polyester Tape t = 0.025mm, 4 Layers

4. Electrical Characteristics

Pin Specification Remark

Inductance 9, 10 → 7, 8 230H ±7% 100kHz, 1V

5. Core & Bobbin

Core: EER3124, Samhwa (PL-7) (Ae=97.9mm2)

Bobbin: EER3124

FAN7930C • Rev. 1.0.1 20

FAN7930C — Critical Conduction Mode PFC Controller

6. Bill of Materials

Part # Value Note Part # Value Note

Resister Switch

R101 1M 1W Q101 FCPF20N60 20A, 600V, SuperFET

R102 330k 1/2W Diode

R103 10k 1W D101 1N4746 1W, 18V, Zener Diode

R104 30k 1/4W D102 UF4004

1A, 400V Glass Passivated

High-Efficiency Rectifier

R107 10k 1/4W D103 1N4148 1A, 100V Small-Signal Diode

R108 4.7k 1/4W D104 1N4148 1A, 100V Small-Signal Diode

R109 47k 1/4W D105

8A, 600V, General-Purpose

Rectifier

R110 10k 1/4W D106

3A, 600V, General-Purpose

Rectifier

R111 0.80k 5W

R112, 113, 114 3.9k 1/4W IC101 FAN7930C CRM PFC Controller

R115 75k 1/4W

Capacitor Fuse

C101 220nF/275VAC Box Capacitor FS101 5A/250V

C102 680nF/275VAC Box Capacitor NTC

C103 0.68µF/630V Box Capacitor TH101 5D-15

C104 12nF/50V Ceramic Capacitor Bridge Diode

C105 100nF/50V SMD (1206) BD101 15A, 600V

C107 33µF/50V Electrolytic Capacitor Line Filter

C108 220nF/50V Ceramic Capacitor LF101 23mH

C109 47nF/50V Ceramic Capacitor Transformer

C110 1nF/50V Ceramic Capacitor T1 EER3124 Ae=97.9mm2

C112 47nF/50V Ceramic Capacitor ZNR

C111 220µF/450V Electrolytic Capacitor ZNR101 10D471

C114 2.2nF/450V Box Capacitor

C115 2.2nF/450V Box Capacitor

FAN7930C • Rev. 1.0.1 21

FAN7930C — Critical Conduction Mode PFC Controller

Physical Dimensions

Figure 47. 8-Lead Small Outline Package (SOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

8°

0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

LAND PATTERN RECOMMENDATION

SEATING PLANE

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR

5.60

0.65

1.75

1.27

6.20

5.80

3.81

4.00

3.80

5.00

4.80

(0.33)

1.27

0.51

0.33

0.25

0.10

1.75 MAX

0.25

0.19

0.36

0.50

0.25

R0.10

0.90

0.40

(1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

0.25 CBA

0.10 C

FAN7930C • Rev. 1.0.1 22

FAN7930C — Critical Conduction Mode PFC Controller