ISL28617SM10EV1Z - Intersil

FN6562 Rev 3.00 Page 1 of 20

May 27, 2015

FN6562

Rev 3.00

May 27, 2015

ISL28617

40V Precision Instrumentation Amplifier with Differential ADC Driver

DATASHEET

The ISL28617 is a high performance, differential input,

differential output instrumentation amplifier designed for

precision analog-to-digital applications. It can operate over a

supply range of 8V (±4V) to 40V (±20V) and features a

differential input voltage range up to ±34V. The output stage

has rail-to-rail output drive capability optimized for differential

ADC driver applications. Its versatility and small package

makes it suitable for a variety of general purpose applications.

Additional features not found in other instrumentation

amplifiers enable high levels of DC precision and excellent AC

performance.

The gain of the ISL28617 can be programmed from 0.1 to

10,000 via two external resistors, RIN and RFB. The gain

accuracy is determined by the matching of RIN and RFB. The

gain resistors have Kelvin sensing, which removes gain error

due to PC trace resistance. The input and output stages have

individual power supply pins, which enable input signals riding

on a high common mode voltage to be level shifted to a low

voltage device, such as an A/D converter. The rail-to-rail output

stage can be powered from the same supplies as the ADC,

which preserves the ADC maximum input dynamic range and

eliminates ADC input overdrive.

Related Literature

•AN1753, “ISL28617VYXXEV1Z User’s Guide” Evaluation

board with bulk metal foil resistors for high precision.

•AN1748, “ISL28617SMXXEV1Z User’s Guide” Evaluation

board with standard resistors for low cost, medium

precision.

Features

• Rail-to-rail differential output ADC driver

• High voltage interface to low voltage circuits

• Wide operating voltage range . . . . . . . . . . . . . . . ±4V to ±20V

• Low input offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30µV

• Excellent CMRR and PSRR . . . . . . . . . . . . . . . . . . . . . . . 120dB

• Closed loop -3dB BW . . .0.3MHz (AV= 1k) to 5MHz (AV=0.1)

• Operating temperature range. . . . . . . . . . . .-40°C to +125°C

• Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ld TSSOP

Applications

• Precision test and measurement

• High voltage industrial process control

• Signal conditioning amplifier for remote powered sensors

•Weigh scales

• ECG and biomedical sense amplifiers

100

120

140

CMRR (dB)

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

= 100

FIGURE 1. CMRR RF = 121k

= 1000

= 10

= 1

= 0.1

RIN

+RIN

-RIN

IN+

+RIN

-RIN

IN-

+RFB

-RFB

+RFB

-RFB

VCC

VCO

GND

VEE

VEO

RFB

+VOUT

-VOUT

VCMO VREF

+5V

+20V

-5V

-20V

ISL28617

A-D

BRIDGE

VDD

GND

-VFB

+VFB CONVERTER

EXCITATION

FULL BRIDGE STRAIN GAUGE AMPLIFIER AND DIFFERENTIAL ADC DRIVER

+IN

-IN ISL26132

VREF

ISL21090

AV = RFB/RIN RANGE FROM 0.1 TO 10,000

FIGURE 2. BASIC APPLICATION CIRCUIT

SENSE

NOT RECOMMENDED FOR NEW DESIGNS

NO RECOMMENDED REPLACEMENT

contact our Technical Support Center at

1-888-INTERSIL or www.intersil.com/tsc

ISL28617

FN6562 Rev 3.00 Page 2 of 20

May 27, 2015

ISL28617

(24 LD TSSOP)

TOP VIEW

817

DNC

+RFB

IN+

IN-

DNC

+RIN

+RFB SENSE +RIN SENSE

-RFB SENSE

-RFB

-RIN SENSE

-RIN

GND VCMO

12 13

VCC VEE

VCO

+VFB

VEO

-VFB

+VOUT -VOUT

DNC

Pin Descriptions

NAME PIN NUMBER DESCRIPTION

NC 1 No Internal Connection

DNC 2, 3, 22 For internal use; Do Not Connect.

+RFB 4 Feedback Resistor, RFB+ pin

+RFB SENSE 5 +RFB, Positive Sense pin connects to the

resistor RFB+ terminal to form the RFB+

Kelvin connection.

-RFB SENSE 6 -RFB, Negative Sense pin connects to the

resistor RFB- terminal to form the RFB-

Kelvin connection.

-RFB 7 Feedback Resistor, Negative Terminal.

GND 8 Ground Pin is capacitively coupled to the

internal ESD circuit and should be

connected to power supply common or

signal GND.

VCC 9 Positive Supply for Input Stage and

Feedback Amp.

VCO 10 Positive Supply for Output Stage.

+VFB 11 Positive Output Feedback

+VOUT 12 Positive Output

-VOUT 13 Negative Output

-VFB 14 Negative Output Feedback

VEO 15 Negative Supply for Output Stage.

VEE 16 Negative Supply for Input Stage and

Feedback Amp.

VCMO 17 Output Common Mode Reference input.

-RIN 18 Input Resistor, Negative Terminal.

-RIN SENSE 19 -RIN, Negative Sense pin connects to the

resistor RIN- terminal to form the RIN-

Kelvin connection.

+RIN SENSE 20 +RIN, Positive Sense pin connects to the

resistor RIN+ terminal to form the RIN+

Kelvin connection.

+RIN 21 Input Resistor, Positive Terminal.

IN- 23 Negative Input

IN+ 24 Positive Input

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

TEMP RANGE

(°C)

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

ISL28617FVZ 28617 FVZ -40 to +125 24 Ld TSSOP M24.173

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-

free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28617. For more information on MSL please see tech brief TB363.

ISL28617

FN6562 Rev 3.00 Page 3 of 20

May 27, 2015

Simplified Block Diagram

+15V

+RIN

-RIN

GND

IN+

IN-

RIN

-15V

IN+

+OUT

-OUT

VCMO

+RINSENSE

-RINSENSE

VEE VEO

VCC

+VOUT

-VOUT

IN-

ISL28617 VCO

GND

+RFB

-RFB

RFB

+VFB

+RFBSENSE

-RFBSENSE

-VFB

VCC

VEE

FIGURE 3. SIMPLIFIED BLOCK DIAGRAM

ISL28617

FN6562 Rev 3.00 Page 4 of 20

May 27, 2015

Absolute Maximum Ratings Thermal Information

Maximum Supply Voltage (VCC to VEE or GND) . . . . . . . . . . . . . . . . . . . . 42V

Maximum Supply Voltage (VCO to VEO or GND) . . . . . . . . . . . . . . . . . . . . 42V

Maximum Voltage (VCO to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.5V, -40V

Maximum Voltage (VEO to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V, +40V

Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA

Max/Min Input Current for Input Voltage >VCC or <VEE . . . . . . . . . . . . . ±10mA

Maximum Input Current (±RIN, ±RFB, ±RINSENSE, ±RFBSENSE) . . . .±5mA

Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V

Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . ..(VEE - 0.5V) to (VCC + 0.5V)

Output Short-circuit Duration (1 Output at a Time). . . . . . . . . . . . . . Continuous

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V

Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV

Thermal Resistance (Typical) JA (°C/W) JC (°C/W)

24 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . . 74 28

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . .+150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

Recommended Operating Conditions

Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-40°C to +125°C

VCC, VEE Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . ±4V to ±20V

VCO, VEO Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . ±1.5V to ±20V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5. For JC, the “case temp” location is taken at the package top center.

Electrical Specifications VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = 10kΩRFB = RIN = 30.1kΩTA = +25°C, unless otherwise

specified. Boldface limits apply across the operating temperature range, -40°C to +125°C.

PARAMETER DESCRIPTION TEST CONDITIONS

MIN

(Note 6)TYP

MAX

(Note 6)UNIT

INPUT DC SPECIFICATIONS

VCMIRIN IN+, IN- Common Mode Input Voltage Range VEE +3V VCC -3V V

VOSIN Input Offset Voltage -100 ±30 100 µV

-275 275 µV

TCVOSIN Input Offset Voltage Temperature Coefficient -2.75 ±0.3 2.75 µV/°C

IBIN Input Bias Current -1 ±0.2 1 nA

-1.3 1.3 nA

IOSIN Input Offset Current -0.75 ±0.2 0.75 nA

-1 1 nA

IRIN Input Resistor Drive Current (Note 7) 87 102 117 µA

RINCM Common Mode Input Resistance 80 GΩ

CMRR Common Mode Rejection Ratio VEE +3V < VCM < VCC -3V

G = 1

110 120 dB

107 dB

VEE +3V < VCM < VCC -3V

G = 100

130 150 dB

110 dB

FEEDBACK DC SPECIFICATIONS

VCMIRFB +FB, -FB Common Mode Input Voltage Range VEE + 3V VCC - 3V V

VOSFB Feedback Input Offset Voltage -1600 ±400 1600 µV

-3000 3000 µV

IBVFB+,- Input Bias Current at VFB ± Inputs 15 nA

OUTPUT DC SPECIFICATIONS

VOL Output Voltage Low, VOUT to V- V

CC = +15V, VEE = -15V,

VCO = +4V, VEO = -4V

RIN = RF = 121kΩIOUT = 1.5mA

150 200 mV

200 mV

ISL28617

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May 27, 2015

VOH Output Voltage High, V+ to VOUT V

CC = +15V, VEE = -15V,

VCO = +4V, VEO = -4V

RIN = RF = 121kΩIOUT = 1.5mA

150 200 mV

200 mV

ISC Output Short-circuit Current RL = 0Ωto GND ±45 mA

-20 20 mA

IERR Total Internal Offset Error Current (Note 8) -17 ±5 17 nA

-90 90 nA

EGGain Error (Notes 9, 10)V

OUT = -10V to +10V, RF = 121kΩ

±0.003 %

G = 1

G = 100 ±0.004 %

VOUT = -2.5V to +2.5V, RF = 30.1kΩ

±0.0005 %

G = 1

OUTPUT COMMON MODE SPECIFICATIONS

VCMOCMIR Output Common Mode Control Input Voltage

Range

VEE +3V VCC -3V V

VOSCM Output Common Mode Offset Voltage from

VCMO Input

-1.3 ±0.5 1.3 mV

-4.75 4.75 mV

IBVCMO Input Bias Current at VCMO Input -0.6 ±0.2 0.6 µA

-1.75 1.75 µA

POWER SUPPLY SPECIFICATIONS

ICC Supply Current, VCC to VEE RL = OPEN 2.05 2.2 mA

2.85 mA

ICO Supply Current, VCO to VEO RL = OPEN 2.25 2.6 mA

2.85 mA

VCC to VEE Input Supply Voltage Dual Supply ±4 ±20 V

Single Supply 8 40 V

VCO to VEO Output Supply Voltage Dual Supply ±1.5 ±20 V

Single Supply 3 40 V

PSRR VCC to VEE Power Supply Rejection Ratio VCC to VEE = ±4V to ±20V

123 130

G = 100

118 dB

PSRR VCO to VEO Power Supply Rejection Ratio VCO to VEO = ±4V to ±20V 110 120 dB

110 dB

AC SPECIFICATIONS

eNInput Noise Voltage Density f = 1kHz 8.6 nV/√Hz

eNrms Input rms Noise Voltage f = 0.1 to 10Hz 85 nVrms

iNInput Noise Current Density f = 1kHz 150 fA/√Hz

iNIERR Total Internal Noise Current Density f = 1kHz 2.6 pA/√Hz

iNIERR rms 0.1 to 10Hz Total Internal rms Noise Current f = 0.1 to 10Hz 4 pArms

Electrical Specifications VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = 10kΩRFB = RIN = 30.1kΩTA = +25°C, unless otherwise

specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)

PARAMETER DESCRIPTION TEST CONDITIONS

MIN

(Note 6)TYP

MAX

(Note 6)UNIT

ISL28617

FN6562 Rev 3.00 Page 6 of 20

May 27, 2015

-3dB BW -3dB Bandwidth vs Closed Loop Gain,

RFB = 30.1k

RFB = 30.1kΩRIN = 301kΩG = 0.1 5.5 MHz

RFB = 30.1kΩRIN = 30.1kΩG = 1 2.6 MHz

RFB = 30.1kΩRIN = 3.01kΩG = 10 2.2 MHz

RFB = 30.1kΩRIN = 301ΩG = 100 2.0 MHz

RFB = 30.1kΩRIN = 30.1ΩG = 1000 0.3 MHz

-3dB BW -3dB Bandwidth vs Closed Loop Gain,

RFB = 121k

RFB = 121kΩRIN = 1.21MΩG = 0.1 5.0 MHz

RFB = 121kΩRIN = 121kΩG = 1 1.4 MHz

RFB = 121kΩRIN = 12.1kΩG = 10 0.5 MHz

RFB = 121kΩRIN = 1.21kΩG = 100 0.45 MHz

RFB = 121kΩRIN = 121ΩG = 1000 0.4 MHz

SR Slew Rate 4V/µs

tSSettling Time to 0.01% VOUT = +2.4V, RF = 30.1kΩ3µs

VOUT = +9.6V, RF = 121kΩ11 µs

NOTES:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

7. Compliance to datasheet limits is assured by Design simulation.

8. VOS,OUT = AV*VOS,IN + VOS,FB + IERR * RFB.

9. Differential Gain(AV) = RFB/RIN.

10. ±VOUT, clipping ~ IRF*RFB.

Electrical Specifications VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = 10kΩRFB = RIN = 30.1kΩTA = +25°C, unless otherwise

specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)

PARAMETER DESCRIPTION TEST CONDITIONS

MIN

(Note 6)TYP

MAX

(Note 6)UNIT

ISL28617

FN6562 Rev 3.00 Page 7 of 20

May 27, 2015

Typical Performance Curves VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.

FIGURE 4. ICC vs SUPPLY VOLTAGE (VCC - VEE)FIGURE 5. ICO vs SUPPLY VOLTAGE (VCO - VEO)

FIGURE 6. IERR vs INPUT COMMON MODE VOLTAGE FIGURE 7. IERR vs SUPPLY VOLTAGE (VCC - VEE)

FIGURE 8. VOSFB vs INPUT COMMON MODE VOLTAGE FIGURE 9. VOSFB vs SUPPLY VOLTAGE (VCC - VEE)

0 10 20 30 40 50

SUPPLY VOLTAGE (VCC - VEE)

SUPPLY CURRENT (mA)

0 10 20 30 40 50

SUPPLY VOLTAGE (VCO - VEO)

SUPPLY CURRENT (mA)

-20

-15

-10

-5

-15 -10 -5 0 5 10 15

VCM (V)

Ierr (nA)

-20

-10

0 5 10 15 20 25 30 35 40 45 50

VSUP (VCC - VEE)

Ierr (nA)

-1000

-800

-600

-400

-200

200

400

600

800

1000

-15 -10 -5 0 5 10 15

VCM (V)

VOSFB (µV)

-1000

-800

-600

-400

-200

200

400

600

800

1000

0 5 10 15 20 25 30 35 40 45 50

VSUP (VCC - VEE)

VOSFB (µV)

ISL28617

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May 27, 2015

FIGURE 10. IOS vs SUPPLY VOLTAGE (VCC - VEE)FIGURE 11. IOS vs SUPPLY VOLTAGE (VCC - VEE)

FIGURE 12. IB vs INPUT COMMON MODE VOLTAGE FIGURE 13. IB vs SUPPLY VOLTAGE (VCC - VEE)

FIGURE 14. VOS IN vs INPUT COMMON MODE VOLTAGE FIGURE 15. VOS IN vs SUPPLY VOLTAGE (VCC - VEE)

Typical Performance Curves VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.

-1000

-800

-600

-400

-200

200

400

600

800

1000

0 5 10 15 20 25 30 35 40 45 50

VSUP (VCC - VEE)

IOS (pA)

-1000

-800

-600

-400

-200

200

400

600

800

1000

0 5 10 15 20 25 30 35 40 45 50

VSUP (VCC - VEE)

IOS (pA)

-1000

-800

-600

-400

-200

200

400

600

800

1000

-15 -10 -5 0 5 10 15

VCM (V)

-IB

+IB

IB (pA)

-1000

-800

-600

-400

-200

200

400

600

800

1000

0 5 10 15 20 25 30 35 40 45 50

VSUP (VCC- VEE)

IB (pA)

-IB

+IB

-100

-80

-60

-40

-20

100

-15 -10 -5 0 5 10 15

VCM (V)

VOS IN (µV)

-100

-80

-60

-40

-20

100

0 5 10 15 20 25 30 35 40 45 50

VSUP (VCC - VEE)

VOS IN (µV)

ISL28617

FN6562 Rev 3.00 Page 9 of 20

May 27, 2015

FIGURE 16. IBVCMO vs VCMO INPUT VOLTAGE RANGE FIGURE 17. COMMON MODE RANGE vs OUTPUT VOLTAGE

FIGURE 18. COMMON MODE RANGE vs OUTPUT VOLTAGE FIGURE 19. CLOSED LOOP GAIN (RFB = 30.1k) vs FREQUENCY)

FIGURE 20. CLOSED LOOP GAIN (RFB = 121k) vs FREQUENCY FIGURE 21. POSITIVE PSRR VEE AND VCC (RF = 30.1k)

Typical Performance Curves VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.

-5

-4

-3

-2

-1

-15 -10 -5 0 5 10 15

VCMO (V)

IBVCMO (µA)

-15

-10

-5

-6 -4 -2 0 2 4 6

VOUT+ TO VOUT- (V)

INPUT VCM (V)

VCC = +10V; VEE = -10V

RFB = 120k; RIN = 120

VCO = +5V; VEO = 0V

VCMO = 2.5V

-15

-10

-5

-3 -2 -1 0 1 2 3

VOUT+ TO VOUT- (V)

INPUT VCM (V)

-4

VCC = +10V; VEE = -10V

RFB = 30k; RIN = 30.1

VCO = +3V; VEO = 0V

VCMO = 1.5V

-40

-20

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

AV = 100

AV = 10

RIN = 301

RFB = 30.1k

AV = 1 RIN = 30.1k, RFB = 30.1k

GAIN (dB)

AV = 1000 RIN = 30.1, RFB = 30.1k

RIN = 3.01k, RFB = 30.1k

RIN = 301k, RFB = 30.1k

AV = 0.1

-40

-20

FREQUENCY (Hz)

10 100 1k 10k 100k 1M 10M 100M

AV = 100

AV = 1000

AV = 10

RFB = 121k

AV = 1

GAIN (dB)

AV = 0.1

RIN = 12.1k, RFB = 121k

RIN = 121k, RFB = 121k

= 1.21k

RIN = 121, RFB = 121k

RIN = 1.21M, RFB = 121k

100

120

140

160

1 10 100 1k 10k 100k 1M

POSITIVE PSRR (dB)

FREQUENCY (Hz)

AV = 1000 AV = 100

AV = 0.1

AV = 1

AV = 10

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FIGURE 22. NEGATIVE PSRR VEE AND VCC (RF = 30.1k) FIGURE 23. POSITIVE PSRR VEE AND VCC (RF = 121k)

FIGURE 24. NEGATIVE PSRR VEE AND VCC (RF = 121k) FIGURE 25. POSITIVE PSRR VE0 AND VC0 (RF = 30.1k)

FIGURE 26. NEGATIVE PSRR VEO AND VCO (RF = 30.1k) FIGURE 27. POSITIVE PSRR VEO AND VCO (RF = 121k)

Typical Performance Curves VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.

100

120

140

160

NEGATIVE PSRR (dB)

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 100

AV = 10

AV = 1

AV = 1000

100

120

140

160

POSITIVE PSRR (dB)

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 100

AV = 10

AV = 1000

AV = 1

100

120

140

160

NEGATIVE PSRR (dB)

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 1000

AV = 100

AV = 0.1

AV = 10

AV = 1

100

120

140

160

180

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

POSITIVE PSRR (dB)

AV = 1000

AV = 100

AV = 0.1 AV = 1

AV = 10

100

120

140

160

180

NEGATIVE PSRR (dB)

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 1000

AV = 100

AV = 0.1 AV = 1

AV = 10

100

120

140

160

180

200

POSITIVE PSRR (dB)

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 1000

AV = 100

AV = 0.1

AV = 10

AV = 1

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FIGURE 28. NEGATIVE PSRR VE0 AND VCO (RF = 121k) FIGURE 29. CMRR RF = 30.1k

FIGURE 30. CMRR RF = 121k FIGURE 31. INPUT VOLTAGE AND CURRENT NOISE

Typical Performance Curves VCC = VCO = 15V, VEE = VEO = -15V, VCM = 0V, RL = Open, unless otherwise specified.

100

120

140

160

NEGATIVE PSRR (dB)

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 1000

AV = 100

AV = 0.1

AV = 10

AV = 1

100

120

140

CMRR R

= 30.1k (dB)

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 1000

AV = 100

AV = 10

AV = 1

100

120

140

CMRR R

= 121k (dB)

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 1000

AV = 100

AV = 10

AV = 1

AV = 0.1

1000

0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

100

0.1

0.01

INPUT NOISE VOLTAGE (nV/√Hz)

INPUT NOISE CURRENT (pA/√Hz)

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FN6562 Rev 3.00 Page 12 of 20

May 27, 2015

FIGURE 32. ISL28617 FUNCTIONAL BLOCK DIAGRAM

IN+

RIN

IN-

RFB

100µA

-VCMO

VFB-

-VOUT

VCC

VEE VEO

VCO

VFB+

+VOUT

100µA

INPUT FEEDBACK OUTPUT

STAGESTAGESTAGE

+RINSENSE -RINSENSE

A1 A2 A3 A4

-RFBSENSE +RFBSENSE

Q1 Q2 Q3 Q4

I1 I2 I3 I4

0.1µF

GND

GAIN RESISTORS AND

KELVIN CONNECTIONS

500Ω

+RIN -RIN +RFB -RFB

IS1 IS2 IS3 IS4

I1, I3

I2, I4

ISL28617

FN6562 Rev 3.00 Page 13 of 20

May 27, 2015

Applications Information

“General Description” section: contains the ISL28617 functional

and performance objectives and description of operation.

“Designing with the ISL28617” on page 14 section: contains the

application circuit design equations and guidelines for achieving

the desired DC and AC performance levels.

“Estimating Amplifier DC and Noise Performance” on page 17

section: provides equations for predicting DC offset voltage and

noise of the finished design.

General Description

The ISL28617 Instrumentation Amplifier was developed to

accomplish the following:

• Provide a fully differential, rail-to-rail output for optimally

driving ADCs.

• Limit the output swing to prevent output overdrive.

• Allow any gain, including attenuation.

• Maximize gain accuracy by removing on-chip component

tolerances and external PC board parasitic resistance.

• Enable user control of amplifier precision level with choice of

external resistor tolerance.

• Maintain CMRR>100dB and remove CMRR sensitivity to gain

resistor tolerance.

• Provide a level shift interface from bipolar analog input signal

sources to unipolar and bipolar ADC output terminations.

Functional Description

Figure 32 shows the functional block diagram for the ISL28617.

Input GM Amplifier

The input stage consists of high performance, wide band

amplifiers A1, A2, GM drive transistors Q1, Q2 and input gain

resistor RIN. Current drive for Q1 and Q2 emitters are provided by

matched pair of 100µA current sinks. A unity gain buffer from

each input (IN+, IN-) to the terminals of the input resistor, RIN, is

formed by the connection of the Kelvin resistor sense pins and

drive pins to the terminals of the input resistor, as shown in

Figure 32. In this configuration, the voltage across the input

resistor RIN is equal to the input differential voltage across IN+

and IN-.

The input GM stage operates by creating a current difference in

the collector currents Q1 and Q2 in response to the voltage

difference between the IN+ and IN- pins. When the input voltage

applied to the IN+ and IN- pins is zero, the voltage across the

terminals of the gain resistor RIN, is also zero. Since there is no

current flow through the gain resistor, transistors Q1 and Q2

collector currents I1 and I2 are equal.

A change in the input differential voltage causes an equivalent

voltage drop across the input gain resistor RIN and the resulting

current flow through RIN, causes an imbalance in Q1 and Q2

collector currents I1 and I2, given by Equations 1 and 2:

Feedback GM Amplifier

The feedback amplifiers A3 and A4 form a differential

transconductance amplifier identical to the input stage. The

input terminals (VFB+, VFB-) connect to the ISL28617 differential

output terminals (+VOUT, -VOUT), so that the output voltage also

appears across the feedback gain resistor RFB.

Operation is the same as the input GM stage and the differential

currents I3 and I4 are given by Equations 3 and 4:

Error Amplifier A5, Output Amplifier A6

(Figure 32)

Amplifiers A5 and A6 act together to form a high gain,

differential I/O trans impedance amplifier. Differential current

amplifier A5 sums the differential currents (I1 + I3 and I2 + I4)

from the input and feedback GM amplifiers. From that

summation, a differential error voltage is sent to A6, which

generates the rail-to-rail differential output drive to the +VOUT and

-VOUT pins.

The external connection of the output pins to the feedback

amplifier closes a servo loop where a change in the differential

input voltage is converted into differential current imbalances at

I1 and I2 (Equations 1 and 2) at the summing node inputs to A5.

Current I1 sums with current I3 from the feedback stage and I2

sums with I4. A5 senses the difference between current pairs I1,

I3 and I2, I4. A difference voltage is generated, amplified and fed

back to the feedback amplifier, which creates correction currents

at I3 and I4 to match the currents at I1 and I2 (Equations 3 and 4).

Therefore, at equilibrium:

Combining Equations 1 and 3, (and their complements I2 and I4)

and solving for VOUT as a function of VIN, RIN and RFB, yields

Equation 6:

Equation 6 can be rearranged to form the gain, see Equation 7:

Which is general form of the gain equation for the ISL28617.

(EQ. 1)

I1100AV

IN+ VIN-

–RIN

+=

(EQ. 2)

I2100AV

IN+ VIN-

–RIN

–=

(EQ. 3)

I3100A+V

OUT-VOUT–RFB

–=

(EQ. 4)

I4100A+V

OUT-VOUT–RFB

+=

(EQ. 5)

I1I3and I2I4

(EQ. 6)

Where

VOUT VIN RFB

RIN

=

VOUT +VOUT

-VOUT

 and VIN IN+ IN-–=–=

(EQ. 7)

Gain VOUT VIN

RFB RIN

==

ISL28617

FN6562 Rev 3.00 Page 14 of 20

May 27, 2015

Designing with the ISL28617

To complete a working design, the following procedure is

recommended:

1. Define the output voltage swing

2. Set the feedback resistor value, RFB

3. Set the input gain resistor value, RIN

4. Set the VCO, VEO power supply voltages

5. Set the VCC and VEE supply voltages

The gain of the instrumentation amplifier is set by the resistor

ratio RFB/RIN (Equation 7) and the maximum output swing is set

by the absolute value of the feedback resistor RFB (Equation 8).

VCO and VEO supply power to the rail-to-rail output stage and

define the maximum output voltage swing at the ±VOUT

differential output pins. Power supply pins VCC and VEE power the

feedback amplifiers, which require an additional ±3V beyond the

VCO and VEO voltages to maintain linear operation of the

feedback GM stage.

Setting the Feedback Gain Resistor RFB

(Figures 32, 33)

Resistor RFB defines the maximum differential voltage at output

terminals +VOUT to -VOUT. External resistor RFB and the differential

100µA current sources define the maximum dynamic range of

the feedback stage, which defines the maximum differential

output swing of the output stage. Overload circuitry allows

>100µA to flow through RFB to maintain feedback, but linearity is

degraded. Therefore, it is a good practice to keep the maximum

linear dynamic range to within ±80% of the maximum I*R across

the resistor.

In cases where large pulse overshoot is expected, the maximum

current in Equation 8 could be reduced to 50% for additional

margin (see “AC Performance Considerations” on page 16). The

penalty for increasing the feedback resistor value is higher DC

offset voltage and noise.

Output voltages that exceed the maximum dynamic range of the

feedback amplifier can degrade phase margin and cause

instability. The plot in Figure 33 shows the maximum differential

output voltage swing vs resistor value for RFB and RIN using the

80% and 50% current source levels.

Setting the Input Gain Resistor RIN

(Figures 32, 33)

The input gain resistor RIN is scaled to the feedback resistor

according to the gain shown by Equation 9:

The input GM stage uses the same differential current source

arrangement as the feedback stage. Therefore, the amount of

overdrive margin (50%, 80%) included in the calculation for RFB

is also included in the calculation for RIN.

Input Stage Overdrive Considerations

(Figure 34)

There are a few cases where the input stage can be overdriven,

which must be considered in the application. An input signal that

exceeds the maximum dynamic range of the gain resistor RIN,

calculated previously, can cause the ESD diodes to conduct.

When this occurs, a low impedance path from the inputs to the

input gain resistor RIN will result in signal distortion.

High-speed input signals that remain within the maximum

dynamic range of the input stage can cause distortion if the input

slew rate exceeds the input stage slew rate (~4V/µs). When the

input slews at a faster rate than the GM stage can follow, the

voltage difference appears across the input ESD diodes from

each input and resistor RIN. When the voltage difference is large

enough to cause the diodes to conduct, the input terminals are

shunted to RIN through the 500Ωinput protection resistors,

causing distortion during the rise and fall times of the transient

pulse. The distortion will last until the resistor voltage catches up

to the input voltage.

Setting the Power Supply Voltages

The ISL28617 power supplies are partitioned so that the input stage

and feedback stages are powered from a separate pair of supply

pins (VCC, VEE) than the differential output stage (VCO,V

EO). This

partitioning provides the user with the ability to adapt the ISL28617

to a wide variety of input signal power sources that would not be

possible if the supplies were strapped together internally (VCC = VCO

and VEE = VEO). However, powering the input and output supplies

from unequal supplies has restrictions that are described in the next

section.

(EQ. 8)

VOUTDIFF ±80ARFB

=

FIGURE 33. RFB, RIN vs DYNAMIC RANGE

00 50 100 150 200 250 300 350 400

DYNAMIC VOLTAGE RANGE (±V)

RFB, RIN VALUE (kΩ)

VOUT (V) AT 80%

VOUT (V) AT 50%

(EQ. 9)

RIN RFB Gain=

IN+

RIN

IN-

100µA

VEE

500Ω

VCC

500Ω

ESD

PROTECTION

ESD

PROTECTION

FIGURE 34. INPUT STAGE ESD PROTECTION DIODES

A1 A2

Q1 Q2

ISL28617

FN6562 Rev 3.00 Page 15 of 20

May 27, 2015

Powering the Input and Feedback Stages

(VCC, VEE)

The input pins IN+, IN- cannot swing rail-to-rail, but have a

maximum input voltage range given by Equation 10:

This requires the sum of the common mode input voltage and

the differential input voltage to remain within 3V of either the VCC

or VEE rail, otherwise distortion will result.

The feedback pins VFB+ and VFB- have the same input common

mode voltage constraint as the input pins IN+ and IN-. The

maximum input voltage range of the feedback pins is given by

Equation 11:

To maintain stability, it is critical to respect the ±3V requirement

in Equation 11.

Powering the Rail-to-rail Output Stage

(VCO, VEO)

The output stage (A6) is of rail-to-rail design and is powered by the

VCO and VEO pins. The differential output pins +VOUT and -VOUT

connect to the VFB+ and VFB- pins to close the output feedback

loop. The feedback stage is powered from VCC and VEE pins. The

VFB+ and VFB- have a common mode input range 3V below the VCC

rail and 3V above the and VEE rail. If the output voltage exceeds the

feedback common mode input voltage, loop instability will result.

Therefore, the voltages at the ±VOUT pins should always be 3V

away from either rail, as shown in Equation 12:

Rail-to-rail Differential ADC Driver

The differential output stage of ISL28617 is designed to drive the

differential input stage of an ADC. In this configuration, the VCO

and VEO power supply pins connect directly to the ADC power

supply pins. This output swing arrangement is ideal for driving

rail-to-rail ADC drive without the possibility of overdriving the ADC

input.

The output stage is capable of rail-to-rail operation when VCO and

VEO are powered from a single supply or from split supplies. It

has a single supply voltage range (VCO) from 3V to 15V (with VEO

at GND) and a ±1.5V to ±15V split supply voltage range. Under all

power supply conditions, VCC must be greater than VCO by 3V and

VEE must be less than VEO by 3V to maintain the rail-to-rail output

drive capability.

The VCMO pin is an input to a very low bias current terminal and

sets the output common mode reference voltage when driving a

differential input ADC, such that the output would have a ± input

signal span centered around an external DC reference voltage

applied to the VCMO pin.

Power Supply Voltages by Application

The ISL28617 can be adapted to a wide variety of

instrumentation amplifier applications where the signal source is

powered from supply voltages that are different from the supply

voltages powering downstream circuits. The following examples

are included as a guide to the proper connection and voltages

applied to the supply pins VCC, VEE, VCO and VEO.

There are a common set of requirements across all power

applications:

1. A common ground connection from the input supplies, (VCC,

VEE) to the output supplies (VCO, VEO) is required for all

powering options.

2. The signal input pins IN+ and IN- cannot float and must have

a DC return path to ground.

3. The input and output supplies cannot both be operated in

single supply mode due to the 3V feedback amplifier

common mode headroom requirement in Equation 11.

The following are typical power examples:

EXAMPLE 1: BIPOLAR INPUT TO SINGLE SUPPLY

OUTPUT

The ISL28617 is configured as a 5V ADC driver in a high-gain

sensor bridge amplifier powered from a ±10V excitation source.

The sensor signal output is at a much lower voltage level. In this

application, the ISL28617 must extract the low-level bipolar

sensor signal and shift the level to the 0V to +5V differential

rail-to-rail signal needed by the ADC. The following powering

option is recommended:

•V

CC = +10V, VEE = -10V

•V

CO = +5V, VEO = GND

•V

CMO = +2.5V

•V

CC and VEE power supply common connects to GND

EXAMPLE 2: HIGH VOLTAGE BIPOLAR I/O BUFFER

The ISL28617 is configured as a high impedance buffer

instrumentation amplifier in a ±15V industrial sensor application. In

this application, the ISL28617 must extract and amplify the high

impedance sensor signal and send it downstream to a differential

ADC operating from ±15V supplies. The following powering options

are recommended:

1. Input and output supplies are strapped to the same supplies and

rail-to-rail input to the ADC is not required.

-V

CC = VCO = +15V

-V

EE = VEO = -15V

-V

CMO = GND

-V

CC, VEE power supply common connects to GND

and VOUT = ±12V

2. ±15V Rail-to-rail output is required, then:

-V

CC = +18V, VEE = -18V

-V

CO = +15V, VEO = -15V

-V

CMO = GND

-V

CC and VEE power supply common connects to GND

(EQ. 10)

Where VIN = maximum di fferenti al v ol tage IN+ to IN-

VEE 3V VCMIRIN VINVCC 3V–++

(EQ. 11)

VEE 3V VCMIRFB VCC 3V–+

Where VCMIRFB +VOUT -VOUT–VCMO

+=

(EQ. 12)

VEE 3V VOUT VCC 3V–+

Where VOUT +VOUT or -VOUT

ISL28617

FN6562 Rev 3.00 Page 16 of 20

May 27, 2015

The VCO and VEO power supply pins connect to the ADC (±15V) power

supply pins. Rail-to-rail output swing requires that VCC =V

CO +3V and

VEE = VEO -3V, or ±18V.

EXAMPLE 3: GAINS LESS THAN 1

The ISL28617 is configured to a gain of 0.2V/V driving a

rail-to-rail 3V ADC. In this application, the maximum input

dynamic range is ±15V.

-V

CC = +18V, VEE = -18V

-V

CO = +3V, VEO = GND

-V

CMO = +1.5V

-V

CC, VEE power supply common connects to GND

In this attenuator configuration, the input signal range is ±15V,

which requires an additional ±3V of input overhead from the

input supplies. Thus, VCC and VEE = ±18V.

AC Performance Considerations

The ISL28617 closed loop frequency response is formed by the

feedback GM amplifier and gain resistor RFB and has the

characteristics of a current feedback amplifier. Therefore, the

-3dB gain does not significantly decrease at high gains as is the

case with the constant gain-bandwidth response of the classic

voltage feedback amplifier.

There are four behaviors of current feedback amplifiers that

must be considered:

• Frequency response increases with decreasing values of RFB.

A comparison of the G = 100, -3db response (Figures 19, 20)

RFB at 30.1kΩvs 121kΩshows almost a 4x decrease from

2MHz to 0.5MHz.

• Gain peaking tends to increase with decreasing values of RFB.

• Wide band applications at gains less than 1 (Figures 19, 20)

can have high gain peaking resulting in high levels of

overshoot with pulsed input signals.

• Parasitic capacitance at the feedback resistor terminals

(+RFB,-R

FB) and the Kelvin sense terminals (+RFBSENSE,

-RFBSENSE) will result in increasing levels of peaking and

transient response overshoot.

To minimize peaking external PC parasitic capacitance should be

minimized as much as possible. The ISL28617 is designed to be

stable with PC board parasitic capacitance up to 20pF and

feedback resistor values down to 30.1kΩ. At gains less than 1,

the maximum parasitic capacitance may have to be limited

further to avoid additional compensation.

Uncorrected gain peaking and high overshoot in the feedback

stage can cause loss of feedback loop stability if the transient

causes the feedback voltage to exceed the common mode input

range of the feedback amplifier or the maximum linear range of

the feedback resistor RFB. Corrective actions include increasing

the size of the feedback resistor (see Figure 33) and rescaling

the input gain resistor RIN, or adding input frequency

compensation described in the next section.

The penalty of increasing the RFB (and RIN rescaling) is increased

noise, so this is generally not the corrective action of choice.

AC Compensation Techniques

The input compensation with a low pass filter (Figure 35) can be

an effective way to block high frequency signals from the

differential amplifier inputs. It does not change the gain peaking

behavior of the feedback loop, but it does block signals from

creating overdrive instability. This method is useful after other

corrective measures have been implemented and when there is

little control over the input signal frequency content.

Input Common Mode Rejection

Considerations

The ISL28617 is capable of a very high level (120dB) of CMRR

performance from DC to as high as 1kHz. (Figure 1; CMRR vs

Frequency). This high level of performance over frequency is

made possible by the high common mode input impedance

(80GΩ but requires careful attention to the matching of the

IN+ and IN- external impedances to GND.

A mismatch in the series impedance in conjunction with parasitic

capacitance at the IN+ and IN- terminals (Figure 35) will cause a

common mode amplitude imbalance that will show up as a

differential input signal, rapidly degrading CMRR as the common

mode frequency increases.

Maximum CMRR performance is achieved with attention to

balancing external components and attention to PC layout.

Layout Guidelines

The ISL28617 is a high precision device with wide band AC

performance. Maximizing DC precision requires attention to the

layout of the gain resistors. Achieving good AC response requires

attention to parasitic capacitance at the gain resistor terminals

and CMRR performance over frequency is ensured with

symmetrical component placement and layout of the input

differential signals to the IN+ and IN- terminals.

To ensure the highest DC precision, the location of the gain

resistors and PC trace connections to the Kelvin connections are

most important. Proper Kelvin connections remove trace

resistance errors so that the amplifier gain accuracy and gain

temperature coefficients are determined by the gain resistor

matching tolerance. Interconnect constraints preclude mounting

the gain resistors next to each other, so they should be located on

either side of the ISL28617 and as close to the device as

IN+

IN-

500Ω

R/2

GND

COMMON

MODE ERROR

DIFFERENTIAL

INPUT SIGNAL

FIGURE 35. INPUT DIFFERENTIAL LOW PASS FILTER AND

PARASITIC CAPACITANCE

TRACE

CAPACITANCE

ISL28617

FN6562 Rev 3.00 Page 17 of 20

May 27, 2015

possible. The Kelvin connections are formed at the junction of

the sense pins (±RINSENSE, ±RFBSENSE) and the gain resistor

current drive terminals (±RIN, ±RFB) terminals. This junction

should be made at the terminal pads directly under the ends of

each resistor.

Reduced trace lengths that maintain DC accuracy are also

important for minimizing the capacitance that can degrade AC

stability. This is especially true at gains less than 1. Layout

techniques for precision applications using larger size precision

gain resistors at very low gains (G = 0.1V/V) include removing a

section of the underlying PC ground plane directly under the gain

resistor terminals and body.

Layout guidelines for high CMRR include matching trace lengths

and symmetrical component placement on the circuit that

connects the signal source to the IN+ and IN- pins. This ensures

matching of the IN+ and IN- input impedances (Figure 35).

Power Supply Decoupling

Standard power supply decoupling consists of a single 0.1µF

50V ceramic capacitor at the power supply terminals located as

close to the device as possible. In applications where the input

and output supplies are strapped to the same voltage (VEE = VEO,

VCC = VCO) the connection point should be as close to the device

as possible, with a single 0.1µF 50V ceramic capacitor at the

junction. Applications using separate supplies require 0.1µF 50V

ceramic decoupling capacitors at each power supply terminal.

Estimating Amplifier DC and

Noise Performance

The gain resistor ohmic values and ratios are all that is required

to estimate DC offset and noise. The following sections illustrate

methods to calculate DC offset and noise performance. These

estimates are useful for optimizing resistor values for noise and

DC offset.

Calculating DC Offset Voltage

Output offset voltage, like output noise, has several contributors.

Also similar to output noise, the major offset contributor depends

on the gain configuration. In high-gain, VOS(I) dominates, while in

low-gain, offset due to IERR dominates.

The summation of DC offsets to arrive at total DC offset error is

performed in two ways. Equation 13 is a simple addition of the

DC offsets appearing at the output and is useful when defining

the minimum to maximum range of offset that can be expected.

The drawback is that the result defines the corner of the corner

of the error box and not a typical value given that these sources

are uncorrelated.

Equation 14 expresses the total DC error as the rms, or square

root of the sum of the squares to provide an estimate of a typical

value.

Equation 15 converts the output offset error range (Equation 13)

to an input referred error range [VOS(RTI)] and enables a

comparison with the DC component of the input signal.

Similarly, Equation 16 shows the typical DC offset value

(Equation 14) referred to the input.

NOTE: These results are summarized in Table 1.

Calculating Noise Voltage

The calculation of noise spectral density at the output [eN(RTO)]

from all noise sources is given by Equations 17 and 18:

Then converts the output noise to the input referred value when

evaluating the input signal to noise ratio.

Table 2 provides examples of the noise contribution of each

source by circuit gain and output voltage span. In a high-gain

configuration, the input noise is the dominant noise source. In a

low-gain configuration, the noise voltage from the product of the

internal noise current, IN(err) and the feedback resistor, RFB

dominates. The contribution of the internal noise current, IN(err)

increases in proportion to RFB, but the corresponding increase in

output voltage with RFB keeps the ratio of this noise voltage to

output voltage constant.

(EQ. 13)

VOS RTOAVVOS(I) VOS(FB)IERR RFB

++=

(EQ. 14)

VOS RTOTYP √ AVVOS(I)



2VOS(FB)2

+ IERR RFB



2+=

(EQ. 15)

VOS RTIVOS(I)VOS(FB) AV IERR RFB

AV

++=

(EQ. 16)

VOS RTITYP √ VOS(I)2VOS(FB) AV



+ IERR RFB

AV



2+=

(EQ. 17)

eNRTO√A

 eN

I

22A

iN

I 5002++=



24kT RIN

4kT RFB

RFB iNIERR

2eNFB2+++

(EQ. 18)

eNRTIeNRTOAV

=

ISL28617

FN6562 Rev 3.00 Page 18 of 20

May 27, 2015

TABLE 1. COMPUTING TYPICAL OUTPUT OFFSET VOLTAGE RANGES

AVVO(LIN)

RIN

(kΩ)

RFB

(kΩ)

AV x VOS(I)

(µV)

(Note 11)

VOS(FB)

(µV)

(Note 11)

IERR (5nA) x RFB

(µV)

(Note 11)

VOS(RTO)

(µV)

(Equation 13)

VOS(RTI)

(µV)

(Equation 15)

TYPICAL

VOS(RTO)

(µV)

(Equation 14)

TYPICAL

VOS(RTI)

(µV)

(Equation 16)

1 ±2.5 30 30 ±30 ±400 ±150 ±580 428

1 ±10 120 120 ±15 ±400 ±600 ±1015 721

100 ±2.5 0.3 30 ±1500 ±400 ±150 ±2000 ±20 1560 15.6

100 ±10 1.2 120 ±1500 ±400 ±600 ±2500 ±25 1669 16.7

NOTE:

11. Chosen for illustration purposes and does not reflect actual device performance.

TABLE 2. 1kHz INPUT NOISE AND THERMAL NOISE CONTRIBUTIONS

RIN

(kΩ)

RFB

(kΩ)

AV x eN(I)

(nV/√Hz)

2 x AV x iN(I)

x 500

(nV/√Hz)

AV x √(4kT x RIN)

(nV/√Hz)

√(4kT x RFB)

(nV/√Hz)

RFB x iN(IERR)

(nV/√Hz)

eN(FB)

(nV/√Hz)

eN (RTO)

OUTPUT

REFERRED

NOISE

(nV/√Hz)

eN (RTI)

INPUT

REFERRED

NOISE

(nV/√Hz)

1 30 30 8.6 0.15 22.3 22.3 78 8.6 86

1 120 120 8.6 0.15 44.6 44.6 300 8.6 307

100 0.3 30 860 15 223 22.3 78 8.6 892 8.9

100 1.2 120 860 15 446 44.6 300 8.6 1015 10.15

NOTE:

12. eN and iN values are chosen for illustration purposes and may not reflect actual device performance.

FN6562 Rev 3.00 Page 19 of 20

May 27, 2015

ISL28617

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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

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modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

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Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev.

DATE REVISION CHANGE

May 27, 2015 FN6562.3 The units of the Y axis on Figures 8, 9, 14, 15 changed from "mV" to “µA” and Figure 16 changed from "mA" to

"µA.

On page 15, under EXAMPLE 1, added the following after the first sentence: “The sensor signal output is at a

much lower voltage level”.

November 17, 2014 FN6562.2 Corrected Typo under “Recommended Operating Conditions” on page 4 from “VE+ to VEO”.

Removed Important note (All parameters having Min/Max specifications are guaranteed. Typ values are for

information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed

tests, therefore: TJ = TC = TA) on page 4 as Note 6 covers this.

Updated About Intersil verbiage.

October 17, 2013 FN6562.1 Added a description to the “Related Literature” on page 1.

“Thermal Information” on page 4: Added theta jc (top) = 28C/W.

Added two new graphs for common mode range vs output voltage (Figure 17 and 18).

May 25, 2012 FN6562.0 Initial release.

ISL28617

FN6562 Rev 3.00 Page 20 of 20

May 27, 2015

Package Outline Drawing

M24.173

24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 1, 5/10

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

SIDE VIEW

END VIEW

Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

Dimensions are measured at datum plane H.

Dimensioning and tolerancing per ASME Y14.5M-1994.

Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.08mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead

is 0.07mm.

Dimension in ( ) are for reference only.

Conforms to JEDEC MO-153.

NOTES:

SEATING PLANE

1 3

PLANE

GAUGE

0.05 MIN

0.15 MAX

0°-8°

0.60± 0.15

0.90

1.00 REF

0.25

SEE DETAIL "X"

0.15

0.25

(0.65 TYP)

(5.65)

(0.35 TYP)

(1.45)

6.40

4.40 ±0.10

0.65

1.20 MAX

PIN #1

I.D. MARK

7.80 ±0.10

+0.05

-0.06

+0.05

-0.10

+0.15

0.20 C B A

0.10 C

0.05

0.10 C B A

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