
Datasheet 11.000
July 2018
These specificat i ons are subject to change without notice. 07/26/2018
© 2018 Greenliant 2 S71060
GLS29EE512 Small-Sec tor Flash™
512 Kbit (64K x8) Page-Write EEPROM
Read
The Read o perations of GLS29EE512 is controlled b y
CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the
output contr o l a nd is us ed t o gat e data fr om the out put
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read Cycle
Timing diagram for further details (Figure 3).
Write
The Page-Write to GLS29EE512 should always use
the JEDEC Standard Software Data Protection (SDP)
three-byte command sequence. GLS29EE512
contains the optional JEDEC approved Software Data
Protection scheme. Greenliant recommends that SDP
always be enabled, thus, the description of the Write
operations will be given using the SDP enabled
format. The three-byte SDP Enable and SDP Write
commands are identical; therefore, any time a SDP
Write command is issued, Software Data
Protection is automatically assured. The first time
the three-byte SDP command is given, the device
becomes SDP enabled. Subsequent issuance of the
same command bypasses the data protection for the
page being written. At the end of the desired Page-
Write, the entire device remains protected. For
additional descriptions, please see the application
note, Protecting Against Unintentional Writes When
Using Sing le Pow er Supply Flash Memories.
The Write operation consists of three steps. Step 1 is
the three-byte load sequence for Software Data
Protection. Step 2 is the byte-load cycle to a page
buffer of GLS29EE512. Steps 1 and 2 use the same
timing for both operations. Step 3 is an internally
controlled Write cycle for w ritin g th e da ta loa ded in the
page buffer into the memory array for nonvolatile
storage.
During both the SDP three-byte load sequence and
the byte-load cycle, the addresses are latched by the
falling edge of either CE# or WE#, whichever occurs
last. The data is latched by the rising edge of either
CE# or WE#, whichever occurs first. The internal
Write cycle is initiated by the TBLCO timer after the
rising edge of WE# or CE#, whichever occurs first.
The Write cycle, once initiated, will continue to
completi on, typically within 5 m s. See Figures 4 and 5
for WE# and CE# controlled Page-Write cycle timing
diagrams and Figures 15 and 17 for flowcharts.
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page-
load cycle, and the internal Write cycle. The Software
Data Protection consists of a specific three-byte load
sequence that allows wr iting to the se lected page and
will leave GLS29EE512 protected at the end of the
Page-W rite. T he page-load c ycle c onsists of loading 1
to 128 B ytes of data into th e page buff er. The internal
Write cycle consists of the TBLCO time-out and the
write timer operation. During the Write operation, the
only valid reads are Data# Polling and Toggle Bit.
The Page-Write operation allows the loading of up to
128 Bytes of data into the page buffer of
GLS29E E512 before the initiation of the internal W rite
cycle. During the internal Write cycle, all the data in
the page buffer is written simultaneously into the
memory array. Hence, the Page-Write feature of
GLS29EE512 allows the entire memory to be written
in as little as 2.5 seconds. During the internal Write
cycle, the host is free to perform additional tasks, such
as to fetch data from other locations in the system to
set up the write to the next page. In each Page-Write
operation, all the bytes that are loaded into the page
buffer must have the same page address, i.e. A7
through A16. Any byte not loaded with user data will
be written to FFH.
See Figures 4 and 5 for the Page-Write cycle timing
diagrams. If after the completion of the three-byte
SDP load sequence or the initial byte-load cycle, the
host loads a second b yte into the pag e buffer within a
byte-load cycle time (TBLC) of 100 μs, GLS29EE512
will stay in the page-load cycle. Additional bytes are
then loaded consecutively. The page-load cycle will
be terminated if no additional byte is loaded into the
page buffer within 200 μs (TBLCO) from the last byte-
load cycle, i.e., no subsequent WE# or CE# high-to-
low transition af ter the last rising edg e of WE# or C E#.
Data in the page buffer can be changed by a
subseque nt byte-load c ycle. The page-load p er io d can
continue indefinitely, as long as the host continues to
load the device within the byte-load cycle time of 100
μs. The page to be loaded is determined by the page
address of the last b yte loaded.
Software Chip-Erase
GLS29EE512 provides a Chip-Erase oper ation, which
allows the user to simultaneously clear the entire
memory arr ay to the “ 1” state. T his is useful when the
entire device must be quickly erased.
The Software Chip-Erase operation is initiated by
using a specific six-byte load sequenc e. After the load
sequence, the device enters into an internally timed