CY7C026-15AI - Cypress Semiconductor

PRELIMINARY

16K x 16/18 Dual-Port Static RAM

CY7C026

CY7C036

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

November 7

1997 - Revised June 26

1998

Features

• True Dual-Ported memory cells whic h allow simulta-

neous access of the same memory location

• 16K x 16 organization (CY7C026)

• 16K x 18 organization (CY7C036)

• 0.35-micr on CMOS f or optimum speed/power

• High-speed access: 12/15/ 20 ns

• Low operating pow er

—Activ e: ICC = 180 mA (typical)

—Standby: ISB3 = 0.05 mA (typi cal)

• Fully asynchronous operation

• Automatic power-down

• E xpandable data b us to 32/36 bits or more using Mas-

ter/Sla ve chi p select when usi ng more than one devi ce

• On-chip arbitration logic

• Semaphor es incl uded to permit sof tware handshaking

between por ts

•INT

flags for port-to-port communication

• S eparate upper-byte and lower-byte cont rol

• Pin select f or M aster or Slave

• Commercial and Industr ial temper ature ranges

• Available in 100-pin TQFP

• Pin-compatible and functionally equivalent to IDT70261

Notes:

1. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices

2. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 dev ices.

3. BUSY is an output in master mode and an input in slave mode.

R/WL

OEL

I/O8/9L–I/O15/17L I/O

Control

Address

Decode

A0L–A13L

CEL

OEL

R/WL

BUSYL

I/O

Control

CEL

Interrupt

Semaphore

Arbitration

SEML

INTL

M/S

UBL

LBL

I/O0L–I/O7/8L

R/WR

OER

I/O8/9L–I/O15/17R

CER

UBR

LBR

I/O0L–I/O7/8R

UBL

LBL

Logic Block Diagram

A0L–A13L True Dual -Ported

RAM Array

A0R–A13R

CER

OER

R/WR

BUSYR

SEMR

INTR

UBR

LBR

Address

Decode A0R–A13R

[1] [1]

[2] [2]

[3] [3]

8/9

14 14

F or the most recent information, visit the Cypress web site at www.cypress.com

CY7C026

CY7C036

PRELIMINARY

Functional Description

The CY7C026 and CY7036 ar e low- power CMOS 16K x 16/18

dual- port static RAMs. V arious arbitra tion sche mes are includ-

ed on the devices to handle situations when multiple proces-

sors access the sam e pi ece of data. Two ports are provided,

permitting independent, asynchronous access for reads and

wr it es to a ny l oc a ti on in m e m o ry. Th e d evi c e s can b e u tiliz ed

as standalone 16/18-bit dual-por t static RAMs or multiple de-

vices can be combined in order to function as a 32/36-bit or

wider mast er/sla v e dual-p ort sta tic RAM. An M/ S pi n is provi d-

ed for implementing 32/36-bit or wider memory applications

with out the need f or sepa ra te master and slav e de v ices or ad-

ditional discrete logic. Application areas include interproces-

sor/multiprocessor designs, communications status buffering,

and dual-port video/ graphics me mory.

Each port has independent control pins: chip enable (CE),

read or write enable (R /W) , and output enable (OE). Two flags are

provided on each port (BUSY and INT). BUSY signals that the port

is trying to access the same location currently being accessed by the

other por t . The interrupt flag (IN T) permits communication between

ports or systems by means of a mail bo x. The semaphores are used

to pass a flag, or token, from one port to the other to indicate that a

shared resource is in use. The semaphore logic is comprised of eight

share d latches. Only one side can cont rol the latch (semaphor e) at

any time. Control of a semaphore indicates that a shared resource is

in use. An automatic power-down f eature is controlled independently

on each port by the chip enable pin.

The CY7C026 and CY7036 ar e av ailab le in 100 -pin Thin Quad

Plastic Flatpack (TQ FP) packag es.

Pin Configurations

100 - Pi n TQFP (Top View)

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

A6L

A5L

A4L

INTL

A2L

A0L

GND

M/S

A0R

A1R

A1L

A3L

BUSYR

INTR

A2R

A3R

A4R

A5R

BUSYL

CY7 C 02 6 (16K x 16)

I/O10L

I/O11L

I/O15L

I/O13L

I/O14L

GND

I/O0R

VCC

I/O3R

GND

I/O12L

I/O1R

I/O2R

I/O4R

I/O5R

I/O6R

VCC

I/O9L

I/O8L

I/O7L

I/O6L

I/O5L

I/O4L

I/O0L

I/O2L

I/O1L

VCC

R/WL

UBL

LBL

GND

I/O3L

SEML

CEL

A13L

A12L

A11L

A10L

A9L

A8L

A7L

OEL

34 35 36 424139 403837 43 44 45 5048 494746

A6R

A7R

A8R

A9R

A10R

A11R

CER

A13R

UBR

GND

R/WR

GND

I/O14R

LBR

A12R

OER

I/O15R

I/O13R

I/O12R

I/O11R

I/O10R

I/O9R

I/O8R

I/O7R

SEMR

3332313029282726

CY7C026

CY7C036

PRELIMINARY

Pin Configurations (continued)

Selection Guide

CY7C026

CY7C036

-12

CY7C026

CY7C036

-15

CY7C026

CY7C036

-20

Maximum Access Time (ns) 12 15 20

Typ ical Operating Current (mA) 195 190 180

Typical St andby Curren t f or ISB1 (mA) (Both ports TTL level) 55 50 45

Typical St andby Curren t f or ISB3 (mA) (Bo th ports CMOS level) 0.05 0.05 0.05

Top View

100-Pin TQFP

100 99 9798 96

4241

4039

95 94

27 28 3029 31 32 3534 36 37 3833

89 88 8687 8593 92 84

A5L

A4L

INTL

A2L

A0L

BUSY L

GND

INTR

A0R

A1L

I/O11L

I/O12L

I/O16L

VCC

GND

I/O1R

I/O2R

VCC

9091

A3L

M/S

BUSY R

I/O15L

GND

I/O13L

I/O14L

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O6R

83 82 81 80 79 78 77 76

43 44 45 46 47 48 49 50

I/O9L

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

I/O10L

GND

I/O1L

I/O0L

OEL

SEM L

VCC

CEL

UBL

LBL

A11L

A10L

A9L

A8L

A7L

A6L

I/O0R

I/O7R

I/O16R

I/O9R

I/O10R

I/O11R

I/O12R

I/O13R

I/O14R

GND

I/O15R

OE R

R/W R

GND

SEMR

CER

UBR

LBR

A11R

A10R

A9R

A8R

A7R

A6R

A5R

I/O8L

I/O17L

I/O8R

I/O17R

R/W L

CY 7C036 (16K x 18 )

A13L

A13R

A12L

A12R

CY7C026

CY7C036

PRELIMINARY

Maximum Ratings

(Above whi ch the useful l ife ma y be impaired. For user guide-

li nes, not tested.)

Storage Temperature ..... .. ...................... ...–65°C to + 150°C

Ambient Temperature wit h

Power Applied............................................–55°C to + 125°C

Supply Voltage to Ground Potential.. ............ –0.3V to + 7.0V

DC Voltage Applied to Outputs

in High Z State.............................................. –0.5V to + 7.0V

DC Input Voltage[4]........................................–0.5V to + 7.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage ............. ..... ..... .. ................. >2001V

Latch-Up Current. .. ................... ............ ............ ...... >200 mA

Note:

4. Pulse width < 20 ns.

Pin Definitions

Left Port Right Port Descript ion

CELCERChip Enable

R/WLR/WRRead/Write Enable

OELOEROutput Enable

A0L–A13L A0R–A13R Address

I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Out put

SEML SEMRSem aphore Enabl e

UBLUBRUpper Byt e Select ( I/O 8–I/O15 f or x1 6 de v ices; I/O9–I/O17 for x18 de vices)

LBLLBRLow er Byte Select (I/O0–I/O7 for x16 de vices; I/O0–I/O8 for x18 devices)

INTLINTRInterr upt Flag

BUSYLBUSYRBusy Flag

M/S Master or Slave Select

VCC Power

GND Ground

NC No Connect

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +7 0°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

CY7C026

CY7C036

PRELIMINARY

Notes:

5. fMAX = 1/tRC = All i nputs cycli ng at f = 1/tRC (e xcept output enab l e). f = 0 mea ns no add ress or contr ol l ines c hange . Thi s appli es only to inpu ts at C MOS le v el standb y I SB3.

6. Tested initially and after any design or process changes that may affect these parameters.

Electrica l Characteristics Over the Opera ti ng Range

Symbol Parameter

CY7C026

CY7C036

Units

-12 -15 -20

Min Typ Max Min Typ Max Min Typ Max

VOH Output HIGH Voltage (VCC=5V) 2.4 2.4 2.4 V

VOL Output LOW Voltage 0.4 0.4 0.4 V

VIH Input HIGH Voltage 2.2 2.2 2.2 V

VIL Input LOW Voltage 0.8 0.8 0.8 V

IOZ Output Leakage Current –10 10 –10 10 –10 10 µA

ICC Operating Current

(VCC=Max, IOUT=0 mA)

Outputs Disabled

Com’l. 195 325 190 280 180 265 mA

Indust. 215 305 305 290 mA

ISB1 Standby Current

(Both Port s TTL Le v el) CEL

& CER ≥ VIH, f=fMAX

Com’l. 55 75 50 70 45 65 mA

Indust. 65 95 60 80 mA

ISB2 Standby Current

(One Port TTL Level) CEL |

CER ≥ VIH, f= fMAX

Com’l. 125 205 120 180 110 160 mA

Indust. 135 205 125 175 mA

ISB3 Standby Current

(Both Ports CMOS Level)

CEL & CER ≥ VCC–0 . 2 V, f= 0

Com’l. 0.05 0.25 0.05 0.25 0.05 0.25 mA

Indust. 0.05 0.25 0.05 0.25 mA

ISB4 Standby Current

(One Port CMOS Level)

CEL | CER ≥ VIH, f=fMAX[5]

Com’l. 115 185 110 160 100 140 mA

Indust. 125 175 115 155 mA

Capacitance[6]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C , f = 1 MHz,

VCC = 5.0V 10 pF

COUT Outpu t Capacitance 10 pF

AC Test Loads and Waveforms

3.0V

GND 90% 90%

10%

3ns 3ns

10%

ALL INPUTPULSES

(a) Normal Load (Load 1)

R1= 893Ω

OUTPUT

R2= 347Ω

C= 30pF

VTH =1.4V

OUTPUT

C= 30 pF

(b) Thévenin Equivalent (Load 1) (c)Three-State Delay(Load 2)

R1= 893Ω

R2= 347Ω

OUTPUT

C= 5pF

RTH =250

Ω

≤≤

(Used for tLZ, tHZ, tHZWE, & tLZWE

including scope and jig)

CY7C026

CY7C036

PRELIMINARY

Switching Charac teris t ics Ov er the Operating Range[7]

Parameter Description

CY7C026

CY7C036

Unit

–12 –15 –20

Min. Max. Min. Max. Min. Max.

READ CYCLE

tRC Read Cycle Time 12 15 20 ns

tAA Addr ess to Data Vali d 12 15 20 ns

tOHA Output Hold From Address Change 3 3 3 ns

tACE[8] CE LOW to Data Valid 12 15 20 ns

tDOE OE LOW to Data Valid 810 12 ns

tLZOE[9, 10, 11] OE LOW to Low Z 3 3 3 ns

tHZOE[9, 10, 11] OE HIGH to High Z 10 10 12 ns

tLZCE[9, 10, 11] CE LOW to Low Z 3 3 3 ns

tHZCE[9, 10, 11] CE HIGH to High Z 10 10 12 ns

tPU[11] CE LOW to Power-Up 0 0 0 ns

tPD[11] CE HIGH to Power-Down 12 15 20 ns

tABE[8] Byte Enable Access Time 12 15 20 ns

WRITE CYCLE

tWC W ri t e Cycle Tim e 12 15 20 ns

tSCE[8] CE LOW to Write End 10 12 15 ns

tAW Address Valid to Write End 10 12 15 ns

tHA Address Hold From Write End 0 0 0 ns

tSA[8] Address Set -Up to Write Start 0 0 0 ns

tPWE W rite Pu ls e Wid th 10 12 15 ns

tSD Data S e t- U p to W r ite En d 10 10 15 ns

tHD Data Hold From W rite End 0 0 0 ns

tHZWE[10, 11] R/W LOW to High Z 10 10 12 ns

tLZWE[10, 11] R/W HIGH to Lo w Z 3 3 3 ns

tWDD[12] Write Pulse to Data Delay 25 30 45 ns

tDDD[12] Write Data Valid to Read Data Valid 20 25 30 ns

Notes:

7. Test conditions assume signal transition time of 3 ns or less, timing reference lev els of 1.5V, input pulse leve ls of 0 to 3.0V, and output loading of the specified

IOI/IOH and 30-pF load capac itance.

8. To access RAM, CE=L, UB=L, S EM= H. To acce ss semaph ore, C E=H and SE M=L. Either condition mu st be v ali d f or the entir e t SCE time.

9. At any given temperature and voltage condition for any given device , tHZCE is less than tLZCE and tHZOE is less than tLZOE.

10. Test conditions used are Load 3.

11. This parameter is guaranteed but not tested.

12. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.

CY7C026

CY7C036

PRELIMINARY

Data Rete ntion Mode

The CY7C026 and CY7036 are designed wit h battery backup

in mind. Da ta retent ion voltage and supply cu rrent are g uaran-

teed over temperature. The following rul es ensure data reten-

tion:

1. Chip enab le (C E ) must be held HIGH during data retention, with-

in VCC to VCC – 0.2V.

2. CE must be kept between VCC – 0.2V and 70% of VCC

during the power-up and power-down transitions.

3. The RAM can begin operation >tRC after VCC reaches the

minimum operating voltage (4.5 v olts).

Notes:

13. Test conditions used are Load 2.

14. tBDD is a calculate d paramet er and is the gr eater of tWDD–tPWE (actual) or t DDD–tSD (actual).

15. CE = VCC, Vin = GN D to VCC, T A = 25°C . Thi s par ameter is gu aranteed but not tested.

BUSY TIMING[13]

tBLA BUSY LO W f rom Address Match 12 15 20 ns

tBHA BUSY HIGH from Address Mismatch 12 15 20 ns

tBLC BUSY LO W from CE LOW 12 15 20 ns

tBHC BUSY HIGH from CE HIGH 12 15 17 ns

tPS Port Set-Up for Priority 5 5 5 ns

tWB R/W HIGH after BUSY (Slave) 0 0 0 ns

tWH R/W HIGH after BUSY HIGH (Slave) 11 13 15 ns

tBDD[14] BUSY HIGH to Data Valid 12 15 20 ns

INTERRUPT TI MING[13]

tINS INT Set Time 12 15 20 ns

tINR INT Reset Time 12 15 20 ns

SEMAPHORE TIMING

tSOP SEM Flag Updat e Pulse (OE or SEM)10 10 10 ns

tSWRD SEM Flag Write to Read Tim e 5 5 5 ns

tSPS SEM Flag Contention Window 5 5 5 ns

tSAA SEM Address Access Time 12 15 20 ns

Switching Charac teris tics Ov er the Operating Range[7] (continued)

Parameter Description

CY7C026

CY7C036

Unit

–12 –15 –20

Min. Max. Min. Max. Min. Max.

Timing

Parameter Test Conditi ons[15] Max. Unit

ICCDR1 @ VCCDR = 2V 1.5 mA

Data Retention Mode

4.5V 4.5V

VCC > 2.0V

VCC to VCC –0.2V

VCC

tRC

VIH

CY7C026

CY7C036

PRELIMINARY

Switching Wa vef orms

Notes:

16. R/W is HIGH for read cycles.

17. Device is continuously selected CE = VIL and UB or LB = VIL. Thi s wa v ef orm cannot be used f or semaphor e reads .

18. OE = VIL.

19. Address valid prior to or coincident with CE transit ion LO W.

20. To access RAM, CE = VIL, UB or LB = V IL, SEM = VIH. To acces s semaphor e, CE = VIH, SEM = VIL.

tRC

tAA

tOHA

DATA VA LIDPREVIOUS DATA VALID

DATA OUT

ADDRESS

tOHA

Read Cycle No.1 (Either Port Address Access)[16,17,18]

tACE

tLZOE

tDOE

tHZOE

tHZCE

DATA VALID

tLZCE

tPU tPD

ISB

ICC

DATA O UT

CE and

LB or UB

CURRENT

Read Cycle No.2 (Ei ther Port CE/OE Access)[16,19,20]

UB or LB

DATA OUT

tRC

ADDRESS

tAA tOHA

tLZCEtABE

tHZCE

tACE

tLZCE

Read Cycle No. 3 (Ei ther Port) [16,18,19,20]

CY7C026

CY7C036

PRELIMINARY

Notes:

21. R/W m us t be HIG H during al l addres s tr ansiti ons.

22. A write occurs during the overlap (tSCE or t PWE) of a LO W CE or SEM and a LO W UB or LB.

23. tHA is measur ed f rom the ea rlier of CE or R /W or (SEM or R/W) going HI GH at t he end of write cycle .

24. If OE is LOW during a R/W control led write cycle , the write pulse widt h mus t be the larger of tPWE or (tHZWE + tSD) to allow the I/O driv ers to turn off and data to be placed on

the bus for the required tSD. If OE i s HI GH during an R/W controlled write cycl e, this re quireme nt doe s not app ly and the write p ulse ca n be as s hort as the s pecifi ed tPWE.

25. To access RAM, CE = VIL, SEM = VIH.

26. To access upper byte, CE = V IL, UB = VIL, SEM = VIH.

To ac cess l ower b y t e, CE = VIL, LB = VIL, SEM = VIH.

27. Transition is measured ±500 mV from s teady state with a 5- pF loa d (including scope and ji g). T his par ameter is sampled a nd not 100% tested.

28. During this period, the I/O pins are in the output state, and input signals must not be applied.

29. If the CE or SEM LO W trans ition oc curs s imu ltaneous ly with o r a fter the R/W LOW trans ition, the out puts r emain in t he hi gh-im pedance state.

Switching Wa vef orms (continued)

tAW

tWC

tPWE

tHD

tSD

tHA

R/W

DATA OUT

DATA IN

ADDRESS

tHZOE

tSA

tHZWE tLZWE

Write Cycle No. 1: R/ W Co ntrolled Tim ing

[21

24]

[27]

[24]

[25,26]

NOTE 28 NOTE 28

tAW

tWC

tSCE

tHD

tSD

tHA

R/W

DATA IN

ADDRESS

tSA

Write Cycle No. 2: CE Contr olled Timing[21,22,23,29]

[25,26]

CY7C026

CY7C036

PRELIMINARY

Notes:

30. CE = HIGH for the duration of the above timing (both write and read cycle).

31. I/O0R = I/O0L = LO W (r equest s emaph ore); CER = CEL = HIGH.

32. Semaphores are reset (available to both ports) at cycle start.

33. If tSPS is violat ed, th e semaphor e w ill de finitely be obt ained b y one s ide or the ot her, but whic h side will get the semaphore is unpredictable.

Switching Wa vef orms (continued)

tSOP

tSAA

VALID ADRESS VA LID ADRESS

tHD

DATAIN VALID DATAOUT VALID

tOHA

tAW tHA tACE

tSOP

tSCE

tSD

tSA tPWE

tSWRD tDOE

WRITE CYCLE READ CYCLE

R/W

I/O0

SEM

A0–A 2

Semaphor e Read Afte r Write Timing, Ei ther Side[30]

MATCH

tSPS

A0L–A2L

MATCH

R/WL

SEML

A0R–A2R

R/WR

SEMR

Timing Diagram of Semaphore Cont enti on[31,32,33]

CY7C026

CY7C036

PRELIMINARY

Note:

34. CEL = CER = LOW.

Switching Wa vef orms (continued)

VALID

tDDD

tWDD

MATCH

R/WR

DATA INR

DATA OUTL

tWC

ADDRESSR

tPWE

VALID

tSD tHD

ADDRESSL

tPS

tBLA tBHA

tBDD

BUSYL

Timing Dia gram of Read with BUSY (M/S=HIGH)[34]

tPWE

R/W

BUSY tWB tWH

Write Ti ming wit h Busy Input (M/S=LOW)

CY7C026

CY7C036

PRELIMINARY

Note:

35. If tPS is violated, the b us y si gnal will be asserted on one side o r t he oth er , b ut t her e is no guar a ntee t o which si de BU SY will be asserted.

Switching Wa vef orms (continued)

ADDRESS MATCH

tPS

tBLC tBHC

ADDRESS MATCH

tPS

tBLC tBHC

CERValid First:

ADDRESSL,R

BUSYR

CEL

CER

BUSYL

CER

CEL

ADDRESSL,R

Busy Timing Diagram No. 1 (CE Arbi tration)[35]

CELVa li d F ir st :

ADDRESS MATCH

tPS

ADDRESSL

BUSYR

ADDRESS MISMATCH

tRC or tWC

tBLA tBHA

ADDRESSR

ADDRESS MATCH ADDRESS MISMATCH

tPS

ADDRESSL

BUSYL

tRC or tWC

tBLA tBHA

ADDRESSR

Right AddressValid First:

Busy Timing Diagram No. 2 (Address Arbitrati on)

]

Left Address Valid First:

CY7C026

CY7C036

PRELIMINARY

Notes:

36. tHA depends on whi ch enab le pin ( CEL or R/WL) is deasserted first.

37. tINS or tI NR depends on whic h ena ble p in (CEL or R/ WL) is asserted last.

Switching Wa vef orms (continued)

Interrupt Timing Diagrams

WR ITE 3F FF

tWC

Right SideClears INTR:

tHA

READ 3FFF

tRC

tINR

WRITE 3FFE

tWC

Right SideSets INTL:

Left Side Sets INTR:

Left SideClears INTL:

READ 3FFE

tINR

tRC

ADDRESSR

CEL

R/WL

INTL

OEL

ADDRESSR

R/WR

CER

INTL

ADDRESSR

CER

R/WR

INTR

OER

ADDRESSL

R/WL

CEL

INTR

tINS

tHA

tINS

[36]

[37]

[36]

[37]

CY7C026

CY7C036

PRELIMINARY

Architecture

The CY7C026 and CY7036 consist of an array of 16K words

of 16 a nd 1 8 bit s each of dual- port RAM cel ls, I /O and addr ess

lines, and control signals (CE, OE , R/W). These control pins per-

mit independent access for reads or writes to any location in memory.

To handle simultaneous writes/reads to the same location, a BUSY

pin is pr ovided on each port. Two interrupt (INT) pins can be utilized

for port-to-por t com muni cation. Two semaph or e (SEM) control pins

are used f or allocating shared resources. With t he M/S pin, the devic-

es can function as a m ast er (BUSY pins ar e outputs) or as a slave

(BUSY pi ns are inputs). The devices also have an a utomatic pow-

er-down f eature controlled by CE. Each port is provided with its own

output enable control (OE), which a llow s d ata to be read from the

device.

Functional Description

Write Operati on

Data must be set up for a duration of tSD before the rising edge

of R/W in order to guarantee a valid write. A write operation is con-

trolled by either the R/W pin (see Write Cycle No. 1 wav eform) or the

CE pin (see Write Cycle No. 2 waveform). Required inputs for

non-contention operations are summarized in

Table 1

If a location is being written to by one port and the opposite

port attempts to read that location, a port-to-port flowthrough

delay must occur before the data is read on th e output; other-

wise t he data rea d is not det erminist ic. Data will be v alid on the

port t DDD aft er the data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE

and CE pins. Data will be a vailable t ACE after CE or tDOE after OE is

asser ted. If the user w ishes t o access a semaphore fla g, t hen the

SEM pin must be asserted instead of the CE pin, and OE must also

be asserted.

Interrupts

The upper two memory locations may be used for message

passing. The highest memory location (3FFF) is the mailbox

for the right port and the second-highest memory location

(3FFE) is the mail box f or the l eft port. When one port writes t o

the o ther port’ s mail box, a n interrupt is g enerated t o the owner .

The i nterrupt is reset when the o wner rea ds the conte nts of the

mailbox. The me ssage is user defined.

Each port can r ead the other por t’s mailbox without resetting

the interrupt. The active state of the busy signal (to a port)

pre v e nts the port from s etti ng the in terrupt to t he winni ng port.

Also, an active busy to a port prevents that port from reading

its own mailbox and, thus, resetting the interr upt to it.

If an application does not require message passing, do not

connect the interrupt pin to the processor’s interrupt request

input pin.

The operation of the interrupts and their interaction with Busy

are sum m arized in

Table 2.

Busy

The CY7C026 and CY7036 provide on-chip arbi tration to re-

solve simultaneous memory location access (contention). If

both por ts’ CEs are asserted and an address match occurs within

tPS of each other, the busy logic will determine which port has access.

If tPS is violated, one port will definitely gain permission to the location,

but it is not predictable which port will get that permission. BUSY will

be asserted tBLA a fter an a ddr ess m atch or tBLC after CE is taken

LOW.

Master/Slave

A M/S pin is provided in order to expand the word width by configuring

the device as either a master or a slave. The BUSY output of the

master is connected to the BUSY input of the slave. This will allow the

device to interf ace to a master device with no external components.

Wri ting to slave devices must be delayed unti l after the BUSY input

has settled (tBLC or tBLA), otherwise, the slav e chip may begin a write

cycle during a contention situation. When tied HIGH, the M/S pin al-

lows the device to be used as a master and, therefore, the BUSY line

is an output. BUSY can then be used to send the arbitration outcome

to a slav e .

Semaphore Operati on

The CY7C0 26 and CY7036 pr ovide eight semaphore latches,

which are separate from the dual-port memory locations.

Semaphores are used to reserve resources that are shared

between the two ports.The state of the semaphore indicates

that a resource is in use. For example, if the left port wants to

request a given resource, it sets a latch by wr iting a zero to a

semaphore locati on. The left port then verifies it s success in

setting the latch by reading it. After writing t o the semaphore,

SEM or O E must be deasserted for tSOP before attempti ng to read

the semaphore. The semaphore value will be available tSWRD + tDOE

after the rising edge of the semaphore write. If the left port was suc-

cessful (reads a zero), it assumes control of the shared resource,

otherwise (reads a one) it assumes the right port has contro l a nd

continues to poll the semaphore. When the right side has relin-

quished control of the semaphore (by writing a one), the left side will

succeed in gaining control of the semaphore. If the left side no longer

requires the semaphore, a one is written to cancel its request.

Semaphores are accessed by asserting SEM LOW. Th e SEM

pin functions as a chi p select for the semap hore latches (CE must

remain HIGH during S EM LOW). A0–2 represents the semaphore

addre ss. OE a nd R/W are used in the same manner as a normal

memory access. When writing or reading a semaphore, the other

address pins have no effect.

When writing to the semaphore, only I/O0 is used. If a zero is

written to the left port of an available semaphore, a one will appear at

the same semaphore address on the right port. That semaphore can

now onl y be mo dified by t he side showing zero (the left port in t his

case). If the left port now relinquishes control by writing a one to the

semaphore, the semaphore will be set to one for both sides. However,

if the right port had requested the semaphore (written a zero) while

the left port had control, the r ig ht port would immediately own the

semaphore as soon as the left port released it.

Table 3

shows sample

semaphore operations.

When reading a semaphore, all sixteen/eighteen data lines

output the semaphore value. The read value is latched in an

output register to prev ent the sem aphore from chang ing state

during a write from the other por t. If both por ts at tempt to ac-

cess th e sem aphore wit hin tSPS of each other, the semaphore will

definitely be obtained by one side or the other, but there is no guaran-

tee which side will control the semaphore.

CY7C026

CY7C036

PRELIMINARY

Tabl e 1. Non-Contending Read/Writ e

Inputs Outputs

CE R/W OE UB LB SEM I/O9–I/O17 I/O0–I/O8Operation

H X X X X H High Z High Z Deselec ted: Power-Down

X X X H H H High Z High Z Dese lec ted: Power-Down

L L X L H H Data In High Z Write to Upper Byte Only

L L X H L H High Z Data In Write to Lower Byte Only

L L X L L H Data In Data In Write to Both Bytes

L H L L H H Data Out High Z Read Upper Byte Only

L H L H L H High Z Data Out Read Lower Byte Only

L H L L L H Data Out Data Out Read Bot h Bytes

X X H X X X High Z High Z Outputs Disabled

H H L X X L Data Out Data Out Read Data in Semaphore Flag

X H L H H L Data Out Data Out Read Data in Semaphore Flag

H X X X L Data In Data In Write DIN0 into Semaphore Flag

X X H H L Data In Data In Write DIN0 into Semaphore Flag

L X X L X L No t A llo wed

L X X X L L Not Allo we d

Tabl e 2. Interrupt Oper ation Example (assumes BUSYL=BUSYR=HIGH)

Left Port Right Por t

Function R/WLCELOELA0L–13LINTLR/WRCEROERA0R–13R INTR

Set Right IN TR Flag L L X 3FFF X X X X X L[39]

Reset Right IN TR Flag X X X X X X L L 3FFF H[38]

Set Lef t I NT L Flag X X X X L[38] L L X 3FFE X

Reset Left INTL Flag X L L 3FFE H[39] X X X X X

Tabl e 3. Semap hore O peration Example

Function I/O0–I/O17 Left I/O0–I/O17 Right Status

No action 1 1 Semaphore fr ee

Left port write s 0 to semaphore 0 1 Left Por t has semaphore token

Right port writes 0 to semaphore 0 1 No change . Right side has no write access to semap hore

Left port write s 1 to semaphore 1 0 Right port obtains semaphore token

Left port write s 0 to semaphore 1 0 No change. Left por t has no write access to semaphore

Right port writes 1 to semaphore 0 1 Left port obt ains semaphore token

Left port write s 1 to semaphore 1 1 Semaphore fr ee

Right port writes 0 to semaphore 1 0 Right port has semaphore token

Right port writes 1 to semaphore 1 1 Semaphore free

Left port write s 0 to semaphore 0 1 Left port has semaphore token

Left port write s 1 to semaphore 1 1 Semaphore fr ee

Notes:

38. If BUSYR=L, then no c hange .

39. If BUSYL=L, then n o change .

CY7C026

CY7C036

PRELIMINARY

Orde ring Information

Document #: 38–00674–B

16K x16 Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

12 CY7C026-12AC A100 100-Pin Thin Quad Flat Pack Commercial

15 CY7C026-15AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C026-15AI A100 100-Pin Thin Quad Flat Pack Industrial

20 CY7C026-20AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C026-20AI A100 100-Pin Thin Quad Flat Pack Industrial

16K x18 Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

12 CY7C036-12AC A100 100-Pin Thin Quad Flat Pack Commercial

15 CY7C036-15AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C036-15AI A100 100-Pin Thin Quad Flat Pack Industrial

20 CY7C036-20AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C036-20AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C026

CY7C036

PRELIMINARY

of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights . Cypress Semiconductor does not authoriz e

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems appli cation implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Di ag r am

100-Pin Thin Plast ic Quad Flat Pack (TQFP) A100

51-85048-A