S34ML08G2
Distinctive Characteristics
Density
– 8 Gb (4 Gb x 2)
Architecture (For each 4 Gb device)
– Input / Output Bus Width: 8-bits
– Page Size: (2048 + 128) bytes; 128-byte spare area
– Block Size: 64 Pages or (128k + 8k) bytes
– Plane Size
– 2048 Blocks per Plane or (256M + 16M) bytes
–Device Size
– 2 Planes per Device or 512 Mbyte
NAND Flash Interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
Supply Voltage
– 3.3V device: Vcc = 2.7V ~ 3.6V
Security
– One Time Programmable (OTP) area
– Serial number (unique ID)
– Hardware program/erase disabled during power transition
Additional Features
– Supports Multiplane Program and Erase commands
– Supports Copy Back Program
– Supports Multiplane Copy Back Program
– Supports Read Cache
Electronic Signature
– Manufacturer ID: 01h
Operating Temperature
– Industrial: -40°C to 85°C
– industrial Plus: -40°C to 105°C
Performance
Page Read / Program
– Random access: 30 µs (Max)
– Sequential access: 25 ns (Min)
– Program time / Multiplane Program time: 300 µs (Typ)
Block Erase / Multiplane Erase
– Block Erase time: 3.5 ms (Typ)
Reliability
– 100,000 Program / Erase cycles (Typ)
(with 4-bit ECC per 528 bytes)
– 10 Year Data retention (Typ)
– Blocks zero and one are valid and will be valid for at least 1000
program-erase cycles with ECC
Package Options
– Lead Free and Low Halogen
– 48-Pin TSOP 12 x 20 x 1.2 mm
– 63-Ball BGA 11 x 9 x 1 mm
8Gb, 3 V, 4-bit ECC, x8 I/O, SLC NAND
Flash Memory for Embedded
SkyHigh Memory Limited
Document Number: 002-00484 Rev. *J
Suite 4401-02, 44/F One Island East,
18 Westlands Road Hong Kong
www.skyhighmemory.com
Revised May 06, 2019
S34ML08G2
Contents
1. General Description..................................................... 3
2. Connection Diagram.................................................... 3
3. Pin Description............................................................. 4
4. Block Diagrams............................................................ 5
5. Addressing ................................................................... 6
6. Read Status Enhanced ................................................ 6
7. Read ID.......................................................................... 7
7.1 Read Parameter Page ................................................... 8
8. Electrical Characteristics .......................................... 10
8.1 Valid Blocks ................................................................. 10
8.2 Recommended Operating Conditions.......................... 10
8.3 DC Characteristics....................................................... 10
8.4 Pin Capacitance............................................................ 11
Power Consumptions and Pin Capacitance8.5
for Allowed Stacking Configurations ............................. 11
Physical Interface9. ....................................................... 11
Physical Diagram............................................9.1 .............. 12
Ordering Information10. .................................................. 14
Document History11. ....................................................... 15
Document Number: 002-00484 Rev. *J
Page 2 of 15
S34ML08G2
1.
General Description
The SkyHigh
S34ML08G2 8-Gb NAND is offered in 3.3 VCC
with x8 I/O interface. This document contains information for
the
S34ML08G2 device, which is a dual-die stack of two S34ML04G2 die. For detailed specifications, please refer to the discrete die
datasheet:
S34ML01G2_04G2.
2.
Connection Diagram
Figure 1. 48-Pin TSOP1 Contact x8 Device (1 CE 8 Gb)
Note
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Figure 2. 63-BGA Contact, x8 Device, Single CE (Top View)
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
VSS
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VCC
NC
VCC
VSS
NC
VCC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
VSS
12
13
37
36
25
481
24
NAND Flash
TSOP1
(x8)
(1)
(1)
(1)
(1)
F8F7F6F5F4F3
E8E7E6E5E4E3
D8D7D6D5D4D3
C8C7C6C5C4C3
RB#WE#CE#VSSALEWP#
NCNCNCCLERE#VCC
NCNCNCNCNCNC
G8G7G6G5G4G3
NCVSSNCNCNCNC
H8H7H6H5H4H3
Vcc
NCNCNCI/O0NC
B9
A9
NC
NC
A2
NC
NCNCNCNCVCCNC
B10
A10
NC
NC
B1
A1
NC
NC
J8J7J6J5J4J3
I/O7I/O5VCC
NCI/O1NC
K8K7K6K5K4K3
VSS
I/O6I/O4I/O3I/O2VSS
L9
NC
L2
NC
L10
NC
L1
NC
M9
NC
M2
NC
M10
NC
M1
NC
Document Number: 002-00484 Rev. *J
Page 3 of 15
S34ML08G2
3. Pin Description
Notes
1. A 0.1 µF capacitor sh ould be connect ed b etwe en the VCC Sup ply Voltage pin and the VSS Groun d pin to decou ple the curre nt su rges f rom th e power supp ly. The PCB
track widths must be sufficient to carry the currents required during program and erase operations.
2. An internal voltage detector disables all functions whenever VCC is below 1.8V to protect the device from any involuntary program/erase during power transitions.
Table 1. Pin Description
Pin Name Description
I/O0 - I/O7 Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The I/O pins float to High-Z
when the device is deselected or the outputs are disabled.
CLE Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising edge of Write
Enable (WE#).
ALE Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising edge of Write
Enable (WE#).
Chip Enable. This input controCE# ls the selection of the device. When the device is not busy CE# low selects the memory.
Write Enable. This input latches Command, Address and Data.WE# The I/O inputs are latched on the rising edge of WE#.
RE# Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after
the falling edge of RE# which also increments the internal column address counter by one.
WP# Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification (program / erase).
R/B# Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock circuit prevents the
insertion of Commands when VCC is less than VLKO.
Ground.VSS
Not Connected.NC
Document Number: 002-00484 Rev. *J
Page 4 of 15
S34ML08G2
4. Block Diagrams
Figure 3. Functional Block Diagram — 8 Gb
Figure 4. Block Diagram — 1 CE (4 Gb x 8)
Address
Register/
Counter
Controller
Command
Interface
Logic
Command
Register
Data
Register
RE#
I/O Buffer
Y Decoder
Page Buffer
X
D
E
C
O
D
E
R
NAND Flash
Memory Array
WP#
CE#
WE#
CLE
ALE
I/O0~I/O7
Program Erase
HV Generation
8192 Mbit + 512 Mbit (8 Gb Device)
IO0~IO7
CE#
R/B#WE#
RE#
VSS
ALE
VCC
CLE
WP#
IO0~IO7 IO0~IO7
CE# CE#
WE# R/B#WE# R/B#
RE# RE#
VSS VSS
ALE ALE
VCC VCC
CLE CLE
WP# WP#
4 Gb x8
NAND Flash
Memory#1
4 Gb x8
NAND Flash
Memory#2
Document Number: 002-00484 Rev. *J
Page 5 of 15
S34ML08G2
5. Addressing
Notes
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane addre ss = actual page address, also known as the row address.
6. A30 for 8 Gb (4 Gb x 2 – DDP) (1CE).
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A30: block address
6. Read Status Enhanced
Read Status Enhanced is used to retrieve the status value for a previous operation in the following cases:
In the case of concurrent operations on a multi-die stack.
When two dies are stacked to form a dual-die package (DDP), it is possible to run one operation on the first die, then activate a
different operation on the second die, for example: Erase while Read, Read while Program, etc.
In the case of multiplane operations in the same die.
Table 2. Address Cycle Map
Bus Cycle I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
A5 (CAA4 (CA4)A3 (CA3)A2 (CA2)A1 (CA1)A0 (CA0)1st / Col. Add. 1 A7 (CA7)A6 (CA6)5)
LLowLowLowA11 (CA11)A10 (CA10)A9 (CA9)A8 (CA8)2nd / Col. Add. 2 ow
A1A16 (PA4)A15 (PA3)A14 (PA2)A13 (PA1)A12 (PA0)3rd / Row Add. 1 A19 (BA0)A18 (PLA0)7 (PA5)
A2A24 (BA5)A23 (BA4)A22 (BA3)A21 (BA2)A20 (BA1)4th / Row Add. 2 A27 (BA8)A26 (BA7)5 (BA6)
5th / Row Add. 3
(6) LowLowLowLowLowA30 (BA11)A29 (BA10)A28 (BA9)
Document Number: 002-00484 Rev. *J
Page 6 of 15
S34ML08G2
7. Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h.
Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy command (0x00)
before Read Status command (0x70).
For the S34ML08G2 device, five read cycles sequentially output the manufacturer code (01h), and the device code and 3rd, 4th, and
5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 5. Read ID Operation Timing — 8 Gb
5th ID Data
Table 3. Read ID for Supported Configurations
Density Org VCC 1st 2nd 3rd 4th 5th
56h95h90hDCh01h3.3Vx84 Gb
8 Gb (4 Gb x 2 – DDP with one 5Ah95hD1hD3h01h3.3Vx8CE#)
Table 4. Read ID Byte 5 Description
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
ECC Level
1 bit / 512 bytes
2 bit / 512 bytes
4 bit / 512 bytes
8 bit / 512 bytes
0 0
0 1
1 0
1 1
Plane Number
1
2
4
8
0 0
0 1
1 0
1 1
Plane Size
(without spare area)
64 Mb
128 Mb
256 Mb
512 Mb
1 Gb
2 Gb
4 Gb
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
0Reserved
CE#
WE#
CLE
RE#
ALE
tWHR
tAR
tREA
Read ID
Command
Address 1
Cycle
Maker
Code
Device
Code
3rd Cycle 5th Cycle4th Cycle
I/Ox 01h
90h 00h 95h 5AhD3h D1h
Document Number: 002-00484 Rev. *J
Page 7 of 15
S34ML08G2
7.1
Read Parameter Page
The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command register, followed by an
address input of 00h. The command register remains in Parameter
Page mode until further commands are issued to it.
Table
5
explains the parameter fields.
Note:
For 32nm SkyHigh NAND, for a particular condition, the Read Parameter Page command does not give the correct values.
To
overcome this issue, the host must issue a Reset
command before
the Read Parameter Page command. Issuance of Reset
before
the Read Parameter Page command will provide
the correct values
and will not output 00h values.
Table 5. Parameter Page Description
Byte O/M Description Values
Revision Information and Features Block
M0-3
Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
4Fh, 4Eh, 46h, 49h
M4-5
Revision number
Reserved (0)2-15
1 = supports ONFI version 1.01
0 Reserved (0)
02h, 00h
M6-7
Features supported
5-15 Reserved (0)
4 1 = supports odd to even page Copyback
3 1 = supports interleaved operations
2 1 = supports non-sequential page programming
1 1 = supports multiple LUN operations
0 1 = supports 16-bit data bus width
1Eh, 00h
M8-9
Optional commands supported
6-15 Reserved (0)
5 1 = supports Read Unique ID
4 1 = supports Copyback
3 1 = supports Read Status Enhanced
2 1 = supports Get Features and Set Features
1 1 = supports Read Cache commands
0 1 = supports Page Cache Program command
3Bh, 00h
Reserved (0)10-31 00h
Manufacturer Information Block
Device manufacturer (12 ASCII characters)M32-43 53h, 50h, 41h, 4Eh, 53h, 49h, 4Fh,
4Eh, 20h, 20h, 20h, 20h
Device model (20 ASCII characters)M44-63
53h, 33h, 34h, 4Dh, 4Ch, 30h, 38h,
47h, 32h, 20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
01hJEDEC manufacturer IDM64
Date codeO65-66 00h
Reserved (0)67-79 00h
Memory Organization Block
00h, 08h, 00h, 00hNumber of data bytes per pageM80-83
80h, 00hNumber of spare bytes per pageM84-85
00h, 00h, 00h, 00Number of data bytes per partial pageM86-89 h
00h, 00hNumber of spare bytes per partial pageM90-91
40h, 00h, 00h, 00hNumber of pages per blockM92-95
Number of blocks per logiM96-99 00h, 10h, 00h,cal unit (LUN) 00h
02hNumber of logical units (LUNs)M100
M101
Number of address cycles
Column address cycles4-7
Row address cycles0-3
23h
01hNumber of bits per cellM102
Document Number: 002-00484 Rev. *J
Page 8 of 15
S34ML08G2
Note
1. “O” Stands for Optional, “M” for Mandatory.
50h, 00hBad blocks maximum per LUNM103-104
Block enduranceM105-106 01h, 05h
01hGuaranteed valid blocks at beginning of targetM107
01h, 03hBlock endurance for guaranteed valid blocksM108-109
04hNumber of programs per pageM110
M111
Partial programming attributes
Reserved5-7
1 = partial page layout is partial page data followed by4
partial page spare
1-3 Reserved
0 1 = partial page programming has constraints
00h
04hNumber of bits ECC correctabilityM112
M113
Number of interleaved address bits
Reserved (0)4-7
Number of interleaved address bits0-3
01h
O114
Interleaved operation attributes
4-7 Reserved (0)
3 Address restrictions for program cache
2 1 = program cache supported
1 1 = no block address restrictions
0 Overlapped / concurrent interleaving support
04h
Reserved (0)115-127 00h
Electrical Parameters Block
I/O pin capacitanceM128 0Ah
M129-130
Timing mode support
Reserved (0)6-15
1 = supports timing mode 55
1 = supports timing mode 44
1 = supports timing mode 33
1 = supports timing mode 22
1 = supports timing mode 11
1 = supports timing mode 0, shall be 10
1Fh, 00h
O131-132
Program cache timing mode support
Reserved (0)6-15
1 = supports timing mode 55
4 1 = supports timing mode 4
3 1 = supports timing mode 3
2 1 = supports timing mode 2
1 1 = supports timing mode 1
0 1 = supports timing mode 0
1Fh, 00h
tM133-134 PROG BCh, 02hMaximum page program time (µs)
tM135-136 BERS 10h, 27hMaximum block erase time (µs)
tM137-138 R1Eh, 00hMaximum page read time (µs)
tM139-140 CCS C8h, 00hMinimum Change Column setup time (ns)
Reserved (0)141-163 00h
Vendor Block
00hVendor specific Revision numberM164-165
Vendor specific166-253 00h
Integrity CRCM254-255 16h, 26h
Redundant Parameter Pages
Value of bytes 0-255M256-511 Repeat Value of bytes 0-255
Value of bytes 0-255M512-767 Repeat Value of bytes 0-255
FFhAdditional redundant parameter pagesO768+
Table 5. Parameter Page Description (Continued)
Byte O/M Description Values
Document Number: 002-00484 Rev. *J
Page 9 of 15
S34ML08G2
8. Electrical Characteristics
8.1 Valid Blocks
Note
1. Each 4 Gb has maximum 80 bad blocks.
8.2 Recommended Operating Conditions
DC Characteristics8.3
Notes
1. All VCC pins, and VSS pins respectively, are shorted together.
2. Values listed in this table refer to the complete voltage range for VCC and to a single device in case of device stacking.
3. All current measurements are performe d wi th a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin.
4. Standby current measu rement can be performed after the device has completed the initialization process at power up.
Table 6. Valid Blocks
Device Symbol Min Typ Max Unit
NS34ML04G2 VB — Blocks40964016
NS34ML08G2 VB 8032 (1) — Blocks8192
Table 7. Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
V3.63.32.7VccVcc Supply Voltage
V000VssGround Supply Voltage
Table 8. DC Characteristics and Operating Conditions
Parameter Symbol Test Conditions Min Typ Max Units
IPower On Current CC0 ——FFh command input after power on 50 per
device mA
Operating Current
ISequential Read CC1
tRC = tRC (min)
CE# = VIL, Iout = 0 mA — mA3015
IProgram CC2
— mA3015Normal
— mA3015Cache
IErase CC3 —— mA3015
IStandby Current, (TTL) CC4
CE# = VIH,
WP# = 0V/Vcc —— mA1
IStandby Current, (CMOS) CC5
CE# = VCC-0.2,
WP# = 0/VCC
— µA5010
IInput Leakage Current LI VIN = 0 to VCC —— µA±10(max)
IOutput Leakage Current LO VOUT = 0 to VCC —— µA±10(max)
VInput High Voltage IH —V
CC — Vx 0.8 CC V+ 0.3
VInput Low Voltage IL —— V-0.3
CC Vx 0.2
VOutput High Voltage OH IOH —— V2.4= -400 µA
VOutput Low Voltage OL IOL —— V0.4= 2.1 mA
IOutput Low Current (R/B#) OL(R/B#) VOL — mA108= 0.4V
VErase and Program Lockout Voltage LKO ——— V1.8
Document Number: 002-00484 Rev. *J
Page 10 of 15
S34ML08G2
Pin Capacitance8.4
Note
1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].
8.5 Power Consumptions and Pin Capacitance for Allowed Stacking
Configurations
When multiple dies are stacked in the same package, the power consumption of the stack will increase according to the number of
chips. As an example, the standby current is the sum of the standby currents of all the chips, while the active power consumption
depends on the number of chips concurrently executing different operations.
When multiple dies are stacked in the same package the pin/ball capacitance for the single input and the single input/output of the
combo package must be calculated based on the number of chips sharing that input or that pin/ball.
9. Physical Interface
Table 9. Pin Capacitance (TA = 25°C, f=1.0 MHz)
Parameter Symbol Test Condition Min Max Unit
CInput IN VIN — pF10= 0V
CInput / Output IO VIL — pF10= 0V
Document Number: 002-00484 Rev. *J
Page 11 of 15
S34ML08G2
Physical Diagram9.1
48-Pin Thin Small9.1.1 Outline Package (TSOP1)
Figure 6. TS2 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
5007 \ f16-038 \ 6.5.13
TS2 48PACKAGE
MO-142 (D) DDJEDEC
MAXNOMMINSYMBOL
1.20------A
0.15---0.05A1
1.051.000.95A2
0.230.200.17b1
0.270.220.17b
0.16---0.10c1
0.21---0.10c
20.2020.0019.80D
18.5018.4018.30D1
12.1012.0011.90E
0.50 BASICe
0.700.600.50L
O8---0˚
0.20---0.08R
48N
NOTES:
DIMENSIONS ARE IN MILLIMETERS (mm).1.
(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1994).
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS
ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD
PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm.
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM
THE SEATING PLANE.
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
Document Number: 002-00484 Rev. *J
Page 12 of 15
S34ML08G2
63-Pin Ball Grid Array (BGA)9.1.2
Figure 7. VLD063 — 63-Pin BGA, 11 mm x 9 mm Package
g5013 \ 16-038.28 \ 6.5.13
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3, SPP-020.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE TOTAL NUMBER OF POPULATED SOLDER
BALL POSITIONS FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 “SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW “SD” OR “SE” = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
VLD 063PACKAGE
M0-207(M)JEDEC
11.00 mm x 9.00 mm
PACKAGE
NOTEMAXNOMMINSYMBOL
PROFILE1.00------A
BALL HEIGHT------0.25A1
BODY SIZE11.00 BSC.D
BODY SIZE9.00 BSC.E
MATRIX FOOTPRINT8.80 BSC.D1
MATRIX FOOTPRINT7.20 BSC.E1
MATRIX SIZE D DIRECTION12MD
MATRIX SIZE E DIRECTION10ME
BALL COUNT63n
BALL DIAMETER0.500.450.40b
BALL PITCH0.80 BSC.eE
BALL PITCH0.80 BSC.eD
SOLDER BALL PLACEMENT0.40 BSC.SD
SOLDER BALL PLACEMENT0.40 BSC.SE
DEPOPULATED SOLDER BALLSA3-A8,B2-B8,C1,C2,C9,C10
D1,D2,D9,D10,E1,E2,E9,E10
F1,F2,F9,F10,G1,G2,G9,G10
H1,H2,H9,H10,J1,J2,J9,J10
K1,K2,K9,K10
L3-L8,M3-M8
Document Number: 002-00484 Rev. *J
Page 13 of 15
S34ML08G2
10. Ordering Information
The ordering part number is formed by a valid combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
000IFT01208GS34ML
Packing Type
0
=
Tray
3
=
13” Tape and Reel
Model Number
00
=
Standard Interface / ONFI (x8)
Temperature Range
I =
Industrial (–40°C to + 85°C)
A = Industrial with AECQ-100 and GT Grade (-40˚C to +85˚C)
V
=
Industrial Plus (-40°C to +105°C)
B
= Industrial Plus with AECQ-100 and GT Grade (-40˚C to +105˚C)
Materials Set
F = Lead (Pb)-free
H = Lead (Pb)-free and Low Halogen
Package
B = BGA
T = TSOP
Bus Width
00
=
x8 NAND, single die
04
=
x16 NAND, single die
01
=
x8 NAND, dual die
05
=
x16 NAND, dual die
Technology
2 = SkyHigh NAND Revision 2 (32 nm)
Density
01G = 1
Gb
02G = 2
Gb
04G = 4
Gb
08G = 8
Gb
Device Family
S34ML
SkyHigh SLC NAND Flash Memory for Embedded
Valid Combinations
Device
Family Density Technology Bus
Width
Package
Type
Temperature
Range
Additional
Ordering Options
Packing
Type
Package
Description
BGA, TSOP0, 300I, A, V, BBH, TF01208GS34ML
Document Number: 002-00484 Rev. *J
Page 14 of 15
S34ML08G2
11. Document History
Document Title: S34ML08G2 8 Gb, 4-bit ECC, x8 I/O and 3 V VCC NAND Flash Memory for Embedded
Document Number: 002-00484
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
- 04/11/2013XILA** Initial release.
Spansion Publication Number: S34ML08G2
- 05/17/2013XILA*A
Performance: Reliability - updated
Addressing: Address Cycle Map table - updated Bus Cycle data
Read ID: Read ID for Supported Configurations table - updated 8 Gb Density
for 2nd, 3rd, 4th, and 5th
Read Parameter Page: Parameter Page Description table: corrected values
for Bytes 8-9 and 254-255
- 08/09/2013XILA*B
Read ID: Read ID Operation Timing - 8 Gb figure: added values to I/Ox
Physical Interface: Updated TS2 48 - 48-lead Plastic Thin Small Outline, 12 x
20 mm, Package Outline figure
- 01/08/2015XILA*C
Performance: Package Options - added 63-Ball BGA 11 x 9 x 1 mm
Connection Diagram: Added figure - 63-BGA Contact, x8 Device, Single CE
Physical Interface: Added 63-Pin Ball Grid Array (BGA)
Ordering Information: Valid Combinations table - added BH to Package Type
and BGA to Package Description
Updated to Cypress template10/15/2015XILA4955117*D
11/19/2015XILA5017336*E
Fixed formatting issues
Removed Cover page and Spansion Revision History
Distinctive Characteristics: Added industrial Plus temperature range
Ordering Information: Added A, V, B temperature ranges
04/25/2016XILA5160512*F
Added Recommended Operating Conditions section.
Updated DC Characteristics section - updated “VCC supply Voltage (erase and
program lockout)” to "Erase and Program Lockout voltage”.
Updated “Read parameter page” section.
Updated “Ordering Information” section.
Updated copyright information at the end of the document.
Upd06/08/2017AESATMP85767403*G ated logo and Copyright.
Updated09/26/2017MNAD5893557*H Figure 6.
Updated Sa01/17/2018MNAD6033716*I les page and Copyright information.
*J MNAD 05/06/2019 Updated to SkyHigh format
Document Number: 002-00484 Rev. *J
Page 15 of 15
