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(DS8585 Rev. P) 03/19

SLP 1.5

TX0IN

TX1IN

GND

V-

TXAOUT

TXBOUT

V+

SYMBOL

LOGIC INPUT

POWER

OUTPUT

POWER

FUNCTION

CMOS OR TTL, V+ IS OK

CMOS OR TTL

GROUND

-12 TO -15 VOLTS

LINE DRIVER TERMINAL A

LINE DRIVER TERMINAL B

+12 TO +15 VOLTS

DESCRIPTION

TX1IN TX0IN SLP1.5 TXAOUT TXBOUT SLOPE

-5V

N/A

10ms

1.5ms

10ms

1.5ms

N/A

March 2019

ARINC 429

Line Driver

HI-8585, HI-8586

DESCRIPTION

!Direct ARINC 429 line driver interface

in a small package

!On-chip band-gap reference to set

output levels

!On-chip line driver slope control and

selection by logic input

!Low current 12 to 15 volt supplies

!CMOS / TTL logic pins

!Plastic and ceramic package options -

surface mount and DIP

!Thermally enhanced SOIC packages

!Industrial & extended temperature

ranges

FEATURES

PIN CONFIGURATION

SUPPLY VOLTAGES

FUNCTION TABLE

The HI-8585 and HI-8586 are CMOS integrated circuits

designed to directly drive the ARINC 429 bus in an 8-pin

package. Two logic inputs control a differential voltage

between the output pins producing a +10 volt One, a

-10 volt Zero, and a 0 volt Null.

The CMOS/TTL control inputs are translated to ARINC

specified amplitudes using on board band-gap reference.

A logic input is provided to control the slope of the differen-

tial output signal. Timing is set by on-chip resistor and

capacitor and tested to be within ARINC requirements.

The HI-8585 has 37.5 ohms in series with each line driver

output. The HI-8586 provides the option to bypass part of

the output resistance so that series resistance can be

used in external protection circuitry.

The HI-8585 or the HI-8586 along with the HI-8588 or the

Hi-8591 line receivers offer the smallest options available

to get on and off the ARINC bus.

PIN DESCRIPTION TABLE

V+ = 12V to 15V

V- = -12V to -15V

SLP1.5

TX0IN

TX1IN

GND V-

TXAOUT

TXBOUT

V+

4 5

HOLT INTEGRATED CIRCUITS

www.holtic.com

APPLICATION INFORMATION

Figure 1 is a block diagram of the line driver. The +5V and

-5V levels are generated internally using a on-chip band-

gap reference. Currents for slope control are set by zener

voltages across on-chip resistors.

The TX0IN and TX1IN inputs receive logic signals from a

control transmitter chip such as the HI-6010, HI-3282 or

HI-8282. TXAOUT and TXBOUT hold each side of the

ARINC bus at Ground until one of the inputs becomes a

One. If for example TX1IN goes high, a charging path is

enabled to 5V on an “A” side internal capacitor while the

“B” side is enabled to -5V. The charging current is se-

lected by the SLP1.5 pin. If the SLP1.5 pin is high, the

capacitor is nominally charged from 10% to 90% in 1.5µs.

If SLP1.5 is low, the rise and fall times are 10µs.

A unity gain buffer receives the internally generated slopes

and differentially drives the ARINC line. Current is limited

by the series output resistors at each pin. There are no

fuses at the outputs of the HI-8585 as exists on the

Hi-8382.

The HI-8585 has 37.5 ohms in series with each output and

the HI-8586 has 2 ohms in series with each output. The

HI-8586 is for applications where external series resis-

tance is required, typically for lightning protection devices.

Both the HI-8585 and HI-8586 are built using high-speed

CMOS technology. Care should be taken to ensure the

V+ and V- supplies are locally decoupled and that the

input waveforms are free from negative voltage spikes

which may upset the chip’s internal slope control circuitry.

Figure 2 shows a possible application

of the HI-8585/86 interfacing an ARINC

transmit channel from the HI-6010.

HI-8585, HI-8586

FUNCTIONAL DESCRIPTION

TXAOUT

CURRENT

CONTROL

-5V

ONE

NULL

ZERO

CONTROL

LOGIC

TXBOUT

CURRENT

CONTROL

-5V

SLP1.5

ESD

PROTECTION

AND

VOLTAGE

TRANSLATION

TX0IN

TX1IN

FIGURE 1 - LINE DRIVER BLOCK DIAGRAM

HI-8585 = 37.5 OHMS

HI-8586 = 2 OHMS

HI-8585 = 37.5 OHMS

HI-8586 = 2 OHMS

ONE

NULL

ZERO

CONTROL

LOGIC

“A” SIDE

“B” SIDE

GND

TXBOUT

TXAOUT TX1IN

TX0IN

ARINC

Channel

RINB

RINA

TESTA

TESTB

{

HARDWIRED

DRIVEN FROM LOGIC

ROUTB

ROUTA

VCC

V-

-15V

SLP1.5

TXD0

TXD1

RXD0

RXD1

HI-6010

8 BIT BUS

ARINC

Channel

4 5

HI-8588

FIGURE 2 - APPLICATION DIAGRAM

15V

V+

HI-8585

HOLT INTEGRATED CIRCUITS

V+ = +12V to +15V, V- = -12V to -15V, T = Operating Temperature Range (unless otherwise stated)

HI-8585, HI-8586

NOTE: Stresses above absolute maximum

ratings or outside recommended operating

conditions may cause permanent damage to

the device. These are stress ratings only.

Operation at the limits is not recommended.

Voltages referenced to Ground

Supply voltages

V+ .................................................. 20V

V- .................................................. -20V

DC current per input pin ............... +10mA

Power dissipation at 25°C

plastic DIP .......... 1.0W, derate 10mW/°C

ceramic DIP ........ 0.5W, derate 7mW/°C

Solder Temperature (Reflow) .......... 260°C

Storage Temperature ...... -65°C to +150°C

Junction Temperature ...................... 175°C

ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS

Supply Voltages

V+.................................+11.4V to +16.5V

V-.................................. -11.4V to -16.5V

Temperature Range

Industrial .............-40°C to +85°C

Extended ...........-55°C to +125°C

DC ELECTRICAL CHARACTERISTICS

PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Input voltage (TX1IN, TX0IN, SLP1.5)

high VIH 2.1 - V+ volts

low VIL - - 0.5 volts

Input current (TX1IN, TX0IN, SLP1.5)

source IIH VIN = 0V - - 0.1 mA

sink IIL VIN = 5V - - 0.1 mA

ARINC output voltage (Differential)

one VDIFF1 no load; TXAOUT - TXBOUT 9.00 10.00 11.00 volts

zero VDIFF0 no load; TXAOUT - TXBOUT -11.00 -10.00 -9.00 volts

null VDIFFN no load; TXAOUT - TXBOUT -0.50 0 0.50 volts

ARINC output voltage (Ref. to GND)

one or zero VDOUT no load & magnitude at pin 4.50 5.00 5.50 volts

null VNOUT no load -0.25 0 0.25 volts

Operating supply current SLP1.5 = V+

V+ IDD TX1IN & TX0IN = 0V: no load - 6.0 14.0 mA

V- IEE TX0IN & TX1IN = 0V: no load -14.0 -6.0 - mA

ARINC output impedence ZOUT

HI-8585 - 37.5 - ohms

HI-8586 - - 2 ohms

HOLT INTEGRATED CIRCUITS

AC ELECTRICAL CHARACTERISTICS

Notes:

1. Guaranteed but not tested

FIGURE 3 - LINE DRIVER TIMING

10V

-10V

trx

10%

90%

10%

90%

trx

phlx

plhx

10%

plhx

pin 3

pin 2

tfx

pin 6 - pin 7

DIFF

HI-8585, HI-8586

V+ = 15.0V, V- = -15V, T = Operating Temperature Range (unless otherwise stated)

PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Line Driver propagation delay

Output high to low

Output low to high

Line Driver transition times

Output high to low

Output low to high

phlx

plhx

1.0

2.0

500

1.5

µs

logic CIN - - 10 pF

pin 1 = logic 1

SLP 1.5 = V+

pin 1 = logic 1

Output high to low

Output low to high

5.0

15.0

10.0

µs

pin 1 = logic 1

SLP 1.5 = GND

Low Speed

High Speed

defined in Figure 3, no load

pin 1 = logic 1

Input capacitance (1)

HOLT INTEGRATED CIRCUITS

Notes:

1. All data taken in still air on devices soldered to single layer copper PCB (3" X 4.5" X .062").

2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8.

3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF.

4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF

as this is considered unrealistic for high speed operation.

5. 8 Lead Plastic ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink not soldered to the PCB.

6. 8 Lead Plastic ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink soldered to the PCB.

7. Similar results would be obtained with TXAOUT shorted to TXBOUT.

8. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.

9. Data will vary depending on air flow and the method of heat sinking employed.

10. Current values are per supply.

PACKAGE THERMAL CHARACTERISTICS

SUPPLY CURRENT (mA) 2 JUNCTION TEMP, Tj (°C)

Ta = 25oC Ta = 85oC Ta=125oC Ta = 25oC Ta = 85oC Ta=125oC

Low Speed 316.8 17.2 16.9 58 116 157

High Speed 427.3 26.7 25.9 75 132 169

Low Speed 17.4 17.5 16.9 68 126 166

High Speed 27.6 27.1 25.9 97 147 186

Low Speed 17.1 17.2 16.7 52 110 151

High Speed 27.3 27.1 26.2 57 112 157

SUPPLY CURRENT (mA) 2 JUNCTION TEMP, Tj (°C)

Ta = 25oC Ta = 85oC Ta=125oC Ta = 25oC Ta = 85oC Ta=125oC

Low Speed 353.6 50.7 52.2 131 181 217

High Speed 446.9 38.7 42.5 135 181 219

Low Speed 46.4 47.6 68.1 167 191 221

High Speed 42.1 43.8 67.1 177 212 223

Low Speed 48.5 45.6 46.1 112 161 186

High Speed 46.8 41.1 40.5 116 168 197

MAXIMUM ARINC LOAD 9, 10

TXAOUT and TXBOUT Shorted to Ground 7, 8, 9, 10

8 Lead Plastic ESOIC 5

8 Lead Plastic ESOIC 6

ARINC 429

DATA RATE

ARINC 429

DATA RATE

PACKAGE STYLE 1

8 Lead Plastic DIP

8 Lead Plastic ESOIC 5

8 Lead Plastic ESOIC 6

PACKAGE STYLE 1

HEAT SINK - ESOIC PACKAGES

An 8-pin thermally enhanced SOIC package is used for the

HI-8585/HI-8586 products. The ESOIC package includes

a metal heat sink located on the bottom surface of the

device. This heat sink should be soldered down to the

printed circuit board for optimum thermal dissipation. The

heat sink is electrically isolated from the chip and can be

soldered to any ground or power plane. However, since

the chip’s substrate is at V+, connecting the heat sink to

this power plane is recommended to avoid coupling noise

into the circuit.

HI-8585, HI-8586

HOLT INTEGRATED CIRCUITS

Legend: ESOIC - Thermally Enhanced Small Outline Package (SOIC) with built-in heat sink

ORDERING INFORMATION

HI - 85XX xx x x

37.5 Ohms 0

2 Ohms 35.5 Ohms

PART

NUMBER

8585

8586

OUTPUT SERIES RESISTANCE

BUILT-IN REQUIRED EXTERNALLY

PACKAGE

DESCRIPTION

8 PIN PLASTIC DIP (8P)

8 PIN PLASTIC NARROW BODY ESOIC (8HNE)

8 PIN CERDIP (8D) not available Pb-free

PART

NUMBER

TEMPERATURE

RANGE

FLOW BURN

-40°C TO +85°C NoI

-55°C TO +125°C

Yes

PART

NUMBER

PART

NUMBER

LEAD

FINISH

100% Matte Tin (Pb-free, RoHS compliant)

Tin / Lead (Sn / Pb) Solder

Blank

HI-8585, HI-8586

Legend: SOIC - Small Outline Package (No Heat-Sink)

HI - 8585 PS I - N

37.5 Ohms 0

PART

NUMBER

8585

OUTPUT SERIES RESISTANCE

BUILT-IN REQUIRED EXTERNALLY

PACKAGE

DESCRIPTION

8 PIN PLASTIC NARROW BODY SOIC (8HN)

PART

NUMBER

TEMPERATURE

RANGE

FLOW BURN

-40°C TO +85°C NoI

PART

NUMBER

PART

NUMBER

LEAD

FINISH

Tin / Lead (Sn / Pb) Solder - No heat-sink

HOLT INTEGRATED CIRCUITS

REVISION HISTORY

HI-8585, HI-8586

P/N Rev Date Description of Change

DS8585 M 05/08/08

N 09/09/11 Replaced references of setting ARINC output levels with zener diodes to using a band-gap

reference circuit.

O 02/08/17 Update package drawings. Update solder reflow temperature.

P 03/11/19 Add Tjmax to Absolute Maximum Ratings.

Clarified temperature ranges and added HI-8585PSI-N to Ordering Information

HOLT INTEGRATED CIRCUITS

HI-8585 / HI-8586 PACKAGE DIMENSIONS

8-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB

(Narrow Body, Thermally Enhanced)

millimeters (inches)

Package Type: 8HNE

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

Electrically isolated heat

sink pad on bottom of

package

Connect to any ground or

power plane for optimum

thermal dissipation

DETAIL A

0° to 8°

PIN 1

SEE DETAIL A

Top View Bottom View

3.048 ± 0.305

(0.120 ± 0.012)

2.235 ± 0.305

(0.088 ± 0.012)

0.075 ± 0.075

(0.003 ± 0.003)

1.27

(0.50)BSC

3.90

(0.154)

0.175 ± 0.075

(0.007 ± 0.003)

0.835 ± 0.435

(0.033 ± 0.017)

1.25

(0.049)

BSC

6.00

(0.236)BSC

4.90

(0.193)BSC

0.410 ± 0.100

(0.016 ± 0.004) min

8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB

(Narrow Body)

millimeters (inches)

Package Type: 8HN

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

See Detail A

0° to 8°

Detail A

PIN 1

6.00

(0.236)

3.90

(0.154)

4.90

(0.193)

0.175 ± 0.075

(0.007 ± 0.003)

1.27

(0.050)

0.835 ± 0.435

(0.033 ± 0.017)

1.25

(0.049)

0.175 ± 0.075

(0.007 ± 0.003)

0.41 ± 0.10

(0.016 ± 0.004)

BSC

BSC BSC

min.

HOLT INTEGRATED CIRCUITS

HI-8585 / HI-8586 PACKAGE DIMENSIONS

8-PIN CERDIP inches (millimeters)

Package Type: 8D

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

.380 ± .004

(9.652 ± .102)

.005 min

(.127 min)

.314 ± .003

(7.976 ± .076)

.200 max

(5.080 max)

.248 ± .003

(6.299 ± .076)

.039 ± .006

(.991 ± .154)

.163 ± .037

(4.140 ± .940)

.018 ± .006

(.457 ± .152)

.056 ± .006

(1.422 ± .152)

.015 min

(.381min)

.350 ± .030

(8.890 ± .762)

.010 ± .006

(.254 ± .152)

Base Plane

Seating Plane

.100 BSC

(2.54)

8-PIN PLASTIC DIP

.385 ± .015

(9.799 ± .381)

.025 ± .010

(.635 ± .254)

.335 ± .035

(8.509 ± .889)

.250 ± .010

(6.350 ± .254)

.100 BSC

(2.54)

.135 ± .015

(3.429 ± .381)

.055 ± .010

(1.397 ± .254)

.1375 ± .0125

(3.493 ± .318)

.019 ± .002

(.483 ± .102)

.0115 ± .0035

(.292 ± .089)

.300 ± .010

(7.620 ± .254)

inches (millimeters)

Package Type: 8P

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

HOLT INTEGRATED CIRCUITS