HEF4040BPN - NXP Semiconductors / Philips Semiconductors

1. General description

The HEF4040B is a 12-stage binary rippl e counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The

counter advances on the HIGH-to-LOW transitio n of CP. A HIGH on MR clears all counter

stages and forces all outputs LOW, independent of CP. Each counter stage i s a static

toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its

Schmitt trigger action.

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is

also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.

2. Features

Tolerant of slow clock rise and fall time

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Operates across the full industrial temperature range −40 °C to +85 °C

Complies with JEDEC standard JESD 13-B

3. Applications

Frequency dividing circuits

Time delay circuits

Control counters

4. Ordering information

HEF4040B

12-stage binary ripple counter

Rev. 06 — 25 November 2009 Product data sheet

Table 1. Ordering information

All types operate from

−

C to +85

Type number Package

Name Description Version

HEF4040BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

HEF4040BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 06 — 25 November 2009 2 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

5. Functional diagram

Fig 1. Functional di agram

Fig 2. Logic diag ram

001aad58

12-STAGE COUNTER

Q10

Q11

001aae61

FF 1

FF 2

FF 12

Q1 Q11

Fig 3. Timing diagram

001aad587

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

CP input

MR input

Q10

Q11

Product data sheet Rev. 06 — 25 November 2009 3 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 4. Pin configuratio n

HEF4040B

Q11 VDD

Q5 Q10

Q4 Q9

Q6 Q7

Q3 Q8

Q2 MR

Q1 CP

VSS Q0

001aae614

Table 2. Pin description

Symbol Pin Description

VSS 8 ground supply voltage

Q0 to Q11 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 parallel output

CP 10 clock input (HIGH-to-LOW edge -triggered)

MR 11 master reset input (active HIGH)

VDD 16 supply voltage

Product data sheet Rev. 06 — 25 November 2009 4 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

7. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

8. Recommended operating conditions

9. Static characteristics

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +18 V

IIK input clamping current VI<−0.5 V or VI>V

DD + 0.5 V - ±10 mA

VIinput voltage −0.5 VDD + 0.5 V

IOK output clamping current VO<−0.5 V or VO>V

DD + 0.5 V - ±10 mA

II/O input/output current - ±10 mA

IDD supply current - 50 mA

Tstg storage temperature −65 +150 °C

Tamb ambient temperature −40 +85 °C

Ptot total power dissipation DIP16 package [1] - 750 mW

SO16 package [2] - 500 mW

P power dissipation per output - 100 mW

Table 4. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air −40 - +85 °C

Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V

VDD = 10 V - - 0.5 μs/V

VDD = 15 V - - 0.08 μs/V

Table 5. Static characteristics

VSS = 0 V; VI = VSS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °CUnit

Min Max Min Max Min Max

VIH HIGH-level input voltage |IO| < 1 μA 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level input voltage |IO| < 1 μA 5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

Product data sheet Rev. 06 — 25 November 2009 5 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

10. Dynamic characteristics

VOH HIGH-level output voltage |IO| < 1 μA 5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level output voltage |IO| < 1 μA 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-level output current VO = 2.5 V 5 V −1.7 - −1.4 - −1.1 - mA

VO = 4.6 V 5 V −0.52 - −0.44 - −0.36 - mA

VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA

VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA

IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1 .1 - 0.9 - mA

VO = 1.5 V 15 V 3.6 - 3 .0 - 2.4 - mA

ILI input leakage current 15 V - ±0.3 - ±0.3 - ±1.0 μA

IDD supply current IO = 0 A 5 V - 20 - 20 - 150 μA

10 V - 40 - 40 - 300 μA

15 V - 80 - 80 - 600 μA

CIinput capacitance - - - - 7.5 - - pF

Table 5. Static characteristics …continued

VSS = 0 V; VI = VSS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °CUnit

Min Max Min Max Min Max

Table 6. Dynamic characteristics

VSS = 0 V; Tamb = 25

C; unless otherwise specified; for test circuit see Figure 6.

Symbol Parameter Conditions VDD Extrapolation formula [1] Min Typ Max Unit

tPHL HIGH to LOW

propagation delay CP →Q0

see Figure 5 5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns

10 V 34 ns + (0.23 ns/ pF ) C L-4590ns

15 V 27 ns + (0.16 ns/ pF ) C L-3570ns

Qn → Qn + 1 5 V [2] (0.55 ns/pF)CL-3570ns

10 V [2] (0.23 ns/pF)CL-1530ns

15 V [2] (0.16 ns/pF)CL -1020ns

MR → Qn

see Figure 5 5 V 63 ns + (0.55 ns/pF)CL- 90 180 ns

10 V 29 ns + (0.23 ns/ pF ) C L-4080ns

15 V 22 ns + (0.16 ns/ pF ) C L-3060ns

tPLH LOW to HIGH

propagation delay CP →Q0

see Figure 5 5 V 58 ns + (0.55 ns/pF)CL- 85 170 ns

10 V 29 ns + (0.23 ns/ pF ) C L-4080ns

15 V 22 ns + (0.16 ns/ pF ) C L-3060ns

Qn → Qn + 1 5 V [2] (0.55 ns/pF)CL-3570ns

10 V [2] (0.23 ns/pF)CL-1530ns

15 V [2] (0.16 ns/pF)CL-1020ns

Product data sheet Rev. 06 — 25 November 2009 6 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

[1] The typical values of the propagation delay and transition times are calcula t ed from the extrapolation formulas shown (CL in pF)

[2] For loads other than 50 pF at the nth output, use the slope given.

[3] tt is the same as tTHL and tTLH.

tttransition time see Figure 5 5 V [3] 10 ns + (1.00 ns/pF)C L- 60 120 ns

10 V 9 ns + (0.42 ns/pF )C L-3060ns

15 V 6 ns + (0.28 ns/pF )C L-2040ns

tWpulse width CP input HIGH;

minimum width;

see Figure 5

5 V 50 25 - ns

10 V 30 15 - ns

15 V 20 10 - ns

MR input HIGH;

minimum width;

see Figure 5

5 V 40 20 - ns

10 V 30 15 - ns

15 V 20 10 - ns

trec recovery time MR input;

see Figure 5 5 V 40 20 - ns

10 V 30 15 - ns

15 V 20 10 - ns

fmax maximum

frequency CP input;

see Figure 5 5 V 10 20 - MHz

10 V 15 30 - MHz

15 V 25 50 - MHz

Table 6. Dynamic characteristics …continued

VSS = 0 V; Tamb = 25

C; unless otherwise specified; for test circuit see Figure 6.

Symbol Parameter Conditions VDD Extrapolation formula [1] Min Typ Max Unit

Table 7. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf

≤

20 ns; Tamb = 25

Symbol Parameter VDD Typical formula for PD (μW) where:

PDdynamic power

dissipation 5 V PD = 400 × fi + Σ(fo × CL) × VDD2fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

Σ(fo × CL) = sum of the outputs.

10 V PD = 200 0 × fi + Σ(fo × CL) × VDD2

15 V PD = 520 0 × fi + Σ(fo × CL) × VDD2

Product data sheet Rev. 06 — 25 November 2009 7 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

11. Waveforms

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times.

Measurement points are given in Table 8, test circuit in Figure 6 and test data in Table 9

Fig 5. W a v ef orms showing propagation delays for MR to Qn and CP to Q0, minimum MR and CP pulse widths

MR input

Qn + 1 output

CP input

VSS

Q0 or Qn

output

tPHL

1/fmax

trec

001aaj76

tPLH

tTLH tTHL

tPLH tPHL

tPHL

VSS

VOH

VOL

VOH

VOL

Table 8. Measurement points

Supply voltage Input Output

VDD VIVMVM

5 V to 15 V VDD or VSS 0.5VDD 0.5VDD

Product data sheet Rev. 06 — 25 November 2009 8 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

a. Input waveforms

b. Test circuit

Test data is given in Table 9.

Definitions test circuit:

DUT = Device Under Test;

CL = load capacitance, including the jig and probe capacitance;

RL = load resistance, which should be equal to the output impedance of the pulse generator.

Fig 6. Test circuit for measuring switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aaj78

VDD

VIVO

001aag18

DUT

Table 9. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD ≤20 ns 50 pF

Product data sheet Rev. 06 — 25 November 2009 9 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

12. Package outline

Fig 7. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05 0.2542.54 7.62 8.25

7.80

10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12 0.010.1 0.3 0.32

0.31

0.39

0.33 0.030.17 0.02 0.13

IP16: plastic dual in-line package; 16 leads (300 mil) SOT38

-4

Product data sheet Rev. 06 — 25 November 2009 10 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

Fig 8. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

O16: plastic small outline package; 16 leads; body width 3.9 mm SOT109

-1

Product data sheet Rev. 06 — 25 November 2009 11 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

13. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4040B_6 20091125 Product data sheet - HEF4040B_5

Modifications: •Section 2 “Features”, Δt/ΔV values updated.

HEF4040B_5 20090709 Product data sheet - HEF4040B_4

HEF4040B_4 20090304 Product data sheet - HEF4040B_CNV_3

HEF4040B_CNV_3 19950101 Product specification - HEF4040B_CNV_2

HEF4040B_CNV_2 19950101 Product specification - -

Product data sheet Rev. 06 — 25 November 2009 12 of 13

NXP Semiconductors HEF4040B

12-stage binary ripple counter

14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short dat a sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the shor t data sheet, the

full data sheet shall pre va il.

14.3 Disclaimers

General — In formation in this document is believed to be accurate and

reliable. However, NXP Semiconductors does no t give any represent ations or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ra tings System of IEC 60134) may cause pe rmanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

14.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specif ication for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

NXP Semiconductors HEF4040B

12-stage binary ripple counter

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of rele ase: 25 Novemb er 2009

Document identifier: HEF4040B_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

16. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15 Contact information. . . . . . . . . . . . . . . . . . . . . 12

16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13