0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
VIN
CIN
Enable
RON
RFBT
CFF
CSS RFBB COUT
LMZ14202H
VOUT
FB
RON
SS
VIN
EN
GND
VOUT
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LMZ14202H
SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
LMZ14202H SIMPLE SWITCHER
®
6V to 42V, 2A High Output Voltage Power Module
1 Features 2 Applications
1• Integrated Shielded Inductor • Intermediate Bus Conversions to 12-V and 24-V
Rail
• Simple PCB Layout • Time-Critical Projects
• Flexible Start-Up Sequencing Using External Soft-
Start and Precision Enable • Space Constrained / High Thermal Requirement
Applications
• Protection Against Inrush Currents • Negative Output Voltage Applications
• Input UVLO and Output Short Circuit Protection
• –40°C to 125°C Junction Temperature Range 3 Description
• Single Exposed Pad and Standard Pinout for Easy The LMZ14202H SIMPLE SWITCHER®power
Mounting and Manufacturing module is an easy-to-use step-down DC-DC solution
• Low Output Voltage Ripple capable of driving up to 2-A load with exceptional
power conversion efficiency, line and load regulation,
• Pin-to-Oin Compatible Family: and output accuracy. The LMZ14202H is available in
– LMZ14203H/2H/1H (42 V Maximum 3-A, 2-A, an innovative package that enhances thermal
1-A) performance and allows for hand or machine
– LMZ14203/2/1 (42 V Maximum 3-A, 2-A, 1-A) soldering.
– LMZ12003/2/1 (20 V Maximum 3-A, 2-A, 1-A) The LMZ14202H can accept an input voltage rail
• Fully Enabled for WEBENCH®Power Designer between 6 V and 42 V and deliver an adjustable and
highly accurate output voltage as low as 5 V. The
• Electrical Specifications LMZ14202H only requires three external resistors
– Up to 2-A Output Current and four external capacitors to complete the power
– Input Voltage Range 6 V to 42 V solution. The LMZ14202H is a reliable and robust
design with the following protection features: thermal
– Output Voltage as Low as 5 V shutdown, input undervoltage lockout, output
– Efficiency up to 97% overvoltage protection, short-circuit protection, output
• Performance Benefits current limit, and allows start-up into a prebiased
– High Efficiency Reduces System Heat output. A single resistor adjusts the switching
frequency up to 1 MHz.
Generation
– No Compensation Required Device Information(1)(2)
– Low Package Thermal Resistance PART NUMBER PACKAGE BODY SIZE (NOM)
– Low Radiated EMI (EN 55022 Class B Tested) LMZ14202H TO-PMOD (7) 10.16 mm × 9.85 mm
NOTE: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. (1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Peak reflow temperature equals 245°C. See SNAA214 for
more details.
Simplified Application Schematic Efficiency VOUT =12VTA= 25°C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ14202H
SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
www.ti.com
Table of Contents
1 Features.................................................................. 18 Application and Implementation ........................ 16
8.1 Application Information............................................ 16
2 Applications ........................................................... 18.2 Typical Application ................................................. 16
3 Description............................................................. 19 Power Supply Recommendations...................... 21
4 Revision History..................................................... 210 Layout................................................................... 21
5 Pin Configuration and Functions......................... 310.1 Layout Guidelines ................................................. 21
6 Specifications......................................................... 310.2 Layout Example .................................................... 22
6.1 Absolute Maximum Ratings ...................................... 310.3 Power Dissipation and Board Thermal
6.2 ESD Ratings.............................................................. 3Requirements........................................................... 23
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 25
6.4 Thermal Information.................................................. 411.1 Documentation Support ........................................ 25
6.5 Electrical Characteristics........................................... 411.2 Community Resources.......................................... 25
6.6 Typical Characteristics.............................................. 611.3 Trademarks........................................................... 25
7 Detailed Description............................................ 14 11.4 Electrostatic Discharge Caution............................ 25
7.1 Overview................................................................. 14 11.5 Glossary................................................................ 25
7.2 Functional Block Diagram....................................... 14 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 14 Information........................................................... 25
7.4 Device Functional Modes........................................ 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (August 2015) to Revision H Page
• Added the new bullet to the Power Module SMT Guidelines............................................................................................... 22
Changes from Revision F (June 2015) to Revision G Page
• Changed the title of the document ......................................................................................................................................... 1
Changes from Revision E (October 2013) to Revision F Page
• Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description
section, Device Functional Modes,Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
• Removed Easy-to-Use PFM 7 Pin Package image................................................................................................................ 1
Changes from Revision D (February 2013) to Revision E Page
• Changed 10 mils................................................................................................................................................................... 21
• Added Power Module SMT Guidelines................................................................................................................................. 21
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Exposed Pad
Connect to GND
5 SS
6 FB
3 EN
1 VIN
2 RON
4 GND
7 VOUT
LMZ14202H
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SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
5 Pin Configuration and Functions
NDW Package
7-Lead PFM
Top View
Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 VIN Power Supply input — Additional external input capacitance is required between this pin and the
exposed pad (EP).
2 RON Analog ON-time resistor — An external resistor from VIN to this pin sets the ON-time and
frequency of the application. Typical values range from 100 kΩto 700 kΩ.
3 EN Analog Enable — Input to the precision enable comparator. Rising threshold is 1.18 V.
4 GND Ground Ground — Reference point for all stated voltages. Must be externally connected to EP.
5 SS Analog Soft-Start — An internal 8-µA current source charges an external capacitor to produce the
soft-start function.
6 FB Analog Feedback — Internally connected to the regulation, overvoltage, and short-circuit
comparators. The regulation reference point is 0.8 V at this input pin. Connect the
feedback resistor divider between the output and ground to set the output voltage.
7 VOUT Power Output Voltage — Output from the internal inductor. Connect the output capacitor between
this pin and the EP.
— EP Ground Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package
during operation. Must be electrically connected to pin 4 external to the package.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
VIN, RON to GND –0.3 43.5 V
EN, FB, SS to GND –0.3 7 V
Junction Temperature 150 °C
Peak Reflow Case Temperature 245 °C
(30 s)
Storage Temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For soldering specifications, refer to the following document: SNOA549
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN 6 42 V
EN 0 6.5 V
Operation Junction Temperature −40 125 °C
6.4 Thermal Information LMZ14202H
NDW (TO-
THERMAL METRIC(1) UNIT
PMOD)
7 PINS
4-layer Printed-Circuit-Board, 7.62 cm × 7.62 cm (3 in × 3 in) area, 16
1-oz Copper, No air flow
Junction-to-ambient thermal
RθJA °C/W
resistance 4-layer Printed-Circuit-Board, 6.35 cm × 6.35 cm (2.5 in × 2.5 in) 18.4
area, 1-oz Copper, No air flow
Junction-to-case (top)
RθJC(top) No air flow 1.9 °C/W
thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Limits are for TJ= 25°C unless otherwise specified. Minimum and Maximum limits are ensured through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 24 V, VOUT = 12 V, RON = 249 kΩ
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SYSTEM PARAMETERS
ENABLE CONTROL
1.18
VEN EN threshold trip point VEN rising V
over the junction temperature 1.1 1.25
(TJ) range of –40°C to +125°C
EN threshold
VEN-HYS 90 mV
hysteresis
SOFT-START
10
ISS SS source current VSS = 0 V µA
over the junction temperature 8 15
(TJ) range of –40°C to +125°C
ISS-DIS SS discharge current -200 µA
CURRENT LIMIT
3.2
ICL Current limit threshold DC average A
over the junction temperature 2.4 3.95
(TJ) range of –40°C to +125°C
VIN UVLO
EN pin floating
VINUVLO Input UVLO 3.75 V
VIN rising
EN pin floating
VINUVLO-HYST Hysteresis 130 mV
VIN falling
ON/OFF TIMER
ON timer minimum
tON-MIN 150 ns
pulse width
tOFF OFF timer pulse width 260 ns
(1) Minimum and Maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
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Electrical Characteristics (continued)
Limits are for TJ= 25°C unless otherwise specified. Minimum and Maximum limits are ensured through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 24 V, VOUT = 12 V, RON = 249 kΩ
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
REGULATION AND OVERVOLTAGE COMPARATOR
VIN = 24 V, VOUT = 12 0.803
V
VSS >+ 0.8 V over the junction temperature 0.782 0.822
TJ= -40°C to 125°C
In-regulation feedback (TJ) range of –40°C to +125°C
VFB V
IOUT = 10 mA to 2 A
voltage VIN = 24 V, VOUT = 12 V VSS >+ 0.8 V
TJ= 25°C 0.786 0.803 0.818
IOUT = 10 mA to 2 A
VIN = 36 V, VOUT = 24 0.803
V
VSS >+ 0.8 V over the junction temperature 0.780 0.824
TJ= -40°C to 125°C
In-regulation feedback (TJ) range of –40°C to +125°C
VFB V
IOUT = 10 mA to 2 A
voltage VIN = 36 V, VOUT = 24 V VSS >+ 0.8 V
TJ= 25°C 0.787 0.803 0.819
IOUT = 10 mA to 2 A
Feedback overvoltage
VFB-OVP 0.92 V
protection threshold
Feedback input bias
IFB 5 nA
current
Nonswitching Input
IQVFB= 0.86 V 1 mA
Current
Shut Down Quiescent
ISD VEN= 0 V 25 μA
Current
THERMAL CHARACTERISTICS
TSD Thermal Shutdown Rising 165 °C
Thermal Shutdown
TSD-HYST 15 °C
Hysteresis
PERFORMANCE PARAMETERS
ΔVOUT Output Voltage Ripple VOUT = 5 V, CO= 100 µF 6.3 V X7R 8 mV PP
ΔVOUT/ΔVIN Line Regulation VIN = 16 V to 42 V, IOUT= 3 A .01%
ΔVOUT/ΔIOUT Load Regulation VIN = 24 V, IOUT = 0 A to 2 A 1.5 mV/A
ηEfficiency VIN = 24 V, VOUT = 12 V IOUT = 1 A 93%
ηEfficiency VIN = 24 V, VOUT = 12 V IOUT = 2 A 92%
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0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 42V
LMZ14202H
SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
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6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-uF X7R Ceramic; CO= 47 uF; TA= 25°C.
Figure 1. Efficiency VOUT = 5 V TA= 25°C Figure 2. Power Dissipation VOUT = 5 V TA= 25°C
Figure 3. Efficiency VOUT = 12 V TA= 25°C Figure 4. Power Dissipation VOUT = 12 V TA= 25°C
Figure 5. Efficiency VOUT = 15 V TA= 25°C Figure 6. Power Dissipation VOUT = 15 V TA= 25°C
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0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 34V
VIN = 36V
VIN = 42V
0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 28V
VIN = 30V
VIN = 36V
VIN = 42V
0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
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SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-uF X7R Ceramic; CO= 47 uF; TA= 25°C.
Figure 7. Efficiency VOUT = 18 V TA= 25°C Figure 8. Power Dissipation VOUT = 18 V TA= 25°C
Figure 9. Efficiency VOUT = 24 V TA= 25°C Figure 10. Power Dissipation VOUT = 24 V TA= 25°C
Figure 11. Efficiency VOUT = 30 V TA= 25°C Figure 12. Power Dissipation VOUT = 30 V TA= 25°C
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0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 42V
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SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-uF X7R Ceramic; CO= 47 uF; TA= 25°C.
Figure 13. Efficiency VOUT = 5 V TA= 85°C Figure 14. Power Dissipation VOUT = 5 V TA= 85°C
Figure 15. Efficiency VOUT = 12 V TA= 85°C Figure 16. Power Dissipation VOUT = 12 V T = 85°C
Figure 17. Efficiency VOUT = 15 V TA= 85°C Figure 18. Power Dissipation VOUT = 15 V TA= 85°C
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0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 34V
VIN = 36V
VIN = 42V
0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 28V
VIN = 30V
VIN = 36V
VIN = 42V
0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
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SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-uF X7R Ceramic; CO= 47 uF; TA= 25°C.
Figure 19. Efficiency VOUT = 18 V TA= 85°C Figure 20. Power Dissipation VOUT = 18 V TA= 85°C
Figure 21. Efficiency VOUT = 24 V TA= 85°C Figure 22. Power Dissipation VOUT = 24 V TA= 85°C
Figure 23. Efficiency VOUT = 30 V TA= 85°C Figure 24. Power Dissipation VOUT = 30 V TA= 85°C
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-20 0 20 40 60 80 100 120 140
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
VIN = 34V
VIN = 36V
VIN = 42V
-20 0 20 40 60 80 100 120 140
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
VIN = 34V
VIN = 36V
VIN = 42V
-20 0 20 40 60 80 100 120 140
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
VIN = 30V
VIN = 36V
VIN = 42V
-20 0 20 40 60 80 100 120 140
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
VIN = 30V
VIN = 36V
VIN = 42V
-20 0 20 40 60 80 100 120 140
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
VIN = 15V
VIN = 24V
VIN = 42V
-20 0 20 40 60 80 100 120 140
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
VIN = 15V
VIN = 24V
VIN = 42V
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SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-uF X7R Ceramic; CO= 47 uF; TA= 25°C.
Figure 25. Thermal Derating VOUT = 12 V, RθJA = 16°C/W Figure 26. Thermal Derating VOUT = 12 V, RθJA = 20°C/W
Figure 27. Thermal Derating VOUT = 24 V, RθJA = 16°C/W Figure 28. Thermal Derating VOUT = 24 V, RθJA = 20°C/W
Figure 29. Thermal Derating VOUT = 30 V, RθJA = 16°C/W Figure 30. Thermal Derating VOUT = 30 V, RθJA = 20°C/W
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100 mV/Div
1 ms/Div
1.0 A/Div IOUT
VOUT=12V
100 mV/div 1 µs/div
VOUT=12V
0 10 20 30 40 50 60
0
5
10
15
20
25
30
35
40
THERMAL RESISTANCE JA(°C/W)
BOARD AREA (cm2)
0LFM (0m/s) air
225LFM (1.14m/s) air
500LFM (2.54m/s) air
Evaluation Board Area
0.0 0.5 1.0 1.5 2.0
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
OUTPUT VOLTAGE REGULATION (%)
OUTPUT CURRENT (A)
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
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SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-uF X7R Ceramic; CO= 47 uF; TA= 25°C.
Figure 32. Line and Load Regulation TA= 25°C
Figure 31. Package Thermal Resistance RθJA
4-Layer Printed-Circuit-Board With 1-oz Copper
Figure 34. Output Ripple
Figure 33. Output Ripple VIN = 24 V, IOUT = 2 A, Polymer Electrolytic COUT, BW = 200
VIN = 12 V, IOUT = 2 A, Ceramic COUT, BW = 200 MHz MHz
Figure 35. Load Transient Response VIN = 24 V, VOUT = 12 V Figure 36. Load Transient Response VIN = 24 V, VOUT = 12 V
Load Step from 10% to 100% Load Step from 30% to 100%
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30 33 36 39 42 45
2.0
2.5
3.0
3.5
4.0
4.5
DC CURRENT LIMIT LEVEL (A)
INPUT VOLTAGE (V)
Fsw = 250kHz
Fsw = 400kHz
Fsw = 600kHz
200 300 400 500 600 700 800
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
POWER DISSIPATION (W)
SWITCHING FREQUENCY (kHz)
VIN = 30V
VIN = 36V
VIN = 42V
5 10 15 20 25 30 35 40 45
2.0
2.5
3.0
3.5
4.0
4.5
DC CURRENT LIMIT LEVEL (A)
INPUT VOLTAGE (V)
Fsw = 250kHz
Fsw = 400kHz
Fsw = 600kHz
200 300 400 500 600 700 800
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
POWER DISSIPATION (W)
SWITCHING FREQUENCY (kHz)
VIN = 15V
VIN = 24V
VIN = 36V
VIN = 42V
5 10 15 20 25 30 35 40 45
2.0
2.5
3.0
3.5
4.0
4.5
DC CURRENT LIMIT LEVEL (A)
INPUT VOLTAGE (V)
Fsw = 250kHz
Fsw = 400kHz
Fsw = 600kHz
200 300 400 500 600 700 800
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
POWER DISSIPATION (W)
SWITCHING FREQUENCY (kHz)
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 42V
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-uF X7R Ceramic; CO= 47 uF; TA= 25°C.
Figure 37. Current Limit vs. Input Voltage Figure 38. Switching Frequency vs. Power Dissipation
VOUT = 5 V TA= 25°C VOUT = 5 V TA= 25°C
Figure 39. Current Limit vs. Input Voltage Figure 40. Switching Frequency vs. Power Dissipation
VOUT = 12 V TA= 25°C VOUT = 12 V TA= 25°C
Figure 41. Current Limit vs. Input Voltage Figure 42. Switching Frequency vs. Power Dissipation
VOUT = 24 V TA= 25°C VOUT = 24 V TA= 25°C
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0.1 1 10 100
0
10
20
30
40
50
60
70
80
CONDUCTED EMISSIONS (dBV)
FREQUENCY (MHz)
Emissions
CISPR 22 Quasi Peak
CISPR 22 Average
5V/Div 1 ms/Div
VOUT
ENABLE
0 200 400 600 800 1000
0
10
20
30
40
50
60
70
80
RADIATED EMISSIONS (dBV/m)
FREQUENCY (MHz)
Emissions (Evaluation Board)
EN 55022 Limit (Class B)
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-uF X7R Ceramic; CO= 47 uF; TA= 25°C.
Figure 44. Radiated EMI of Evaluation Board, VOUT = 12 V
Figure 43. Start-Up
VIN = 24 V IOUT = 2 A
Figure 45. Conducted EMI, VOUT = 12 V
Evaluation Board BOM and 3.3-µH 2×10-µF LC line filter
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0.47 PF
15 PHCo
CIN
Cvcc
CBST
FB
EN
SS
Vin
Linear reg
RON Timer
Css
RON
RFBT
RFBB
CFF
Regulator IC
VO
Internal
Passives
VOUT
GND
VIN 1
2
3
4
5
6
7
RENT
RENB
LMZ14202H
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7 Detailed Description
7.1 Overview
7.1.1 COT Control Circuit Overview
Constant On Time control is based on a comparator and an ON-time one-shot, with the output voltage feedback
compared to an internal 0.8-V reference. If the feedback voltage is below the reference, the high-side MOSFET
is turned on for a fixed ON-time determined by a programming resistor RON. RON is connected to VIN such that
ON-time is reduced with increasing input supply voltage. Following this ON-time, the high-side MOSFET remains
off for a minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the ON-time
cycle is repeated. Regulation is achieved in this manner.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Output Overvoltage Comparator
The voltage at FB is compared to a 0.92-V internal reference. If FB rises above 0.92 V the ON-time is
immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage
is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top
MOSFET ON-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain
on until inductor current falls to zero.
7.3.2 Current Limit
Current limit detection is carried out during the OFF-time by monitoring the current in the synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds ICL the current
limit comparator disables the start of the next ON-time period. The next switching cycle will occur only if the FB
input is less than 0.8 V and the inductor current has decreased below ICL. Inductor current is monitored during
the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds ICL, further ON-
time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due to the
longer OFF-time.
NOTE
The DC current limit varies with duty cycle, switching frequency, and temperature.
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Feature Description (continued)
7.3.3 Thermal Protection
The junction temperature of the LMZ14202H should not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typical) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing VOto fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 145 °C (typical Hyst = 20 °C) the
SS pin is released, VOrises smoothly, and normal operation resumes.
7.3.4 Zero Coil Current Detection
The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which
inhibits the synchronous MOSFET when its current reaches zero until the next ON-time. This circuit enables the
DCM operating mode, which improves efficiency at light loads.
7.3.5 Prebiased Start-Up
The LMZ14202H will properly start up into a prebiased output. This is start-up situation is common in multiple rail
logic applications where current paths may exist between different power rails during the start-up sequence. The
pre-bias level of the output voltage must be less than the input UVLO set point. This will prevent the output
prebias from enabling the regulator through the high-side MOSFET body diode.
7.4 Device Functional Modes
7.4.1 Discontinuous Conduction and Continuous Conduction Modes
At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it will operate in continuous conduction mode (CCM). When operating in DCM the
switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to
zero before the end of the OFF-time. During the period of time that inductor current is zero, all load current is
supplied by the output capacitor. The next ON-time period starts when the voltage on the FB pin falls below the
internal reference. The switching frequency is lower in DCM and varies more with load current as compared to
CCM. Conversion efficiency in DCM is maintained because conduction and switching losses are reduced with
the smaller load and lower switching frequency.
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VIN
CIN
VIN
RON
RFBT
CFF
CSS RFBB COUT
LMZ14202H
VOUT
FB
RON
SS
VIN
EN
GND
VOUT
10 PF4700 pF
0.022 PF
* RENT
* RENB
* See equation 1
to calculate values
VOUT RFBT RFBB RON COUT COUT-ESR VIN
12V 34 k: 2.43 k: 249 k: 47 PF 1-75 m: 15 - 42V
15V 34 k: 1.91 k: 287 k: 47 PF 1-65 m: 18 - 42V
18V 34 k: 1.58 k: 374 k: 33 PF 1-60 m: 22 - 42V
24V 34 k: 1.18 k: 499 k: 33 PF 1-60 m: 28 - 42V
30V 34 k: 931: 619 k: 33 PF 1-75 m: 34 - 42V
5V 34 k: 6.49 k: 100 k: 100 PF 1-145 m: 8 - 42V
LMZ14202H
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ14202H is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 2 A. The following design procedure can be used to select
components for the LMZ14202H. Alternately, the WEBENCH software may be used to generate complete
designs.
When generating a design, the WEBENCH software uses iterative design procedure and accesses
comprehensive databases of components. For more details, go to www.ti.com.
8.2 Typical Application
Figure 46. Typical Application Schematic
8.2.1 Design Requirements
For this example the following application parameters exist.
• VIN Range = Up to 42 V
• VOUT =5Vto30V
• IOUT =2A
Refer to the table in Figure 46 for more information.
8.2.2 Detailed Design Procedure
8.2.2.1 Design Steps for the LMZ14202H Application
The LMZ14202H is fully supported by WEBENCH which offers the following:
• Component selection
• Electrical simulation
• Thermal simulation
• Build-it prototype board for a reduction in design time
The following list of steps can be used to manually design the LMZ14202H application.
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Typical Application (continued)
1. Select minimum operating VIN with enable divider resistors.
2. Program VOwith divider resistor selection.
3. Program turnon time with soft-start capacitor selection.
4. Select CO.
5. Select CIN.
6. Set operating frequency with RON.
7. Determine module dissipation.
8. Lay out PCB for required thermal performance.
8.2.2.1.1 Enable Divider, RENT and RENB Selection
The enable input provides a precise 1.18-V reference threshold to allow direct logic drive or connection to a
voltage divider from a higher enable voltage such as VIN. The enable input also incorporates 90 mV (typical) of
hysteresis resulting in a falling threshold of 1.09V. The maximum recommended voltage into the EN pin is 6.5 V.
For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to
limit this voltage.
The function of the RENT and RENB divider shown in the Functional Block Diagram is to allow the designer to
choose an input voltage below which the circuit will be disabled. This implements the feature of programmable
under voltage lockout. This is often used in battery-powered systems to prevent deep discharge of the system
battery. It is also useful in system designs for sequencing of output rails or to prevent early turnon of the supply
as the main input voltage rail rises at power up. Applying the enable divider to the main input rail is often done in
the case of higher input voltage systems such as 24-V AC/DC systems where a lower boundary of operation
should be established. In the case of sequencing supplies, the divider is connected to a rail that becomes active
earlier in the power-up cycle than the LMZ14202H output rail. The two resistors should be chosen based on the
following ratio:
RENT / RENB = (VIN-ENABLE/ 1.18 V) – 1 (1)
The EN pin is internally pulled up to VIN and can be left floating for always-on operation. However, it is good
practice to use the enable divider and turn on the regulator when VIN is close to reaching its nominal value. This
will ensure smooth start-up and will prevent overloading the input supply.
8.2.2.1.2 Output Voltage Selection
Output voltage is determined by a divider of two resistors connected between VOand ground. The midpoint of
the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal
operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The high-side MOSFET
ON-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the
voltage at FB is above 0.8 V, ON-time cycles will not occur.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO= 0.8 V × (1 + RFBT / RFBB) (2)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO/ 0.8 V) - 1 (3)
These resistors should be chosen from values in the range of 1 kΩto 50 kΩ.
A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for
best transient response and minimum output ripple.
A table of values for RFBT , RFBB , and RON is included in the simplified applications schematic.
8.2.2.1.3 Soft-Start Capacitor, CSS, Selection
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to
prevent overshoot.
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Typical Application (continued)
Upon turnon, after all UVLO conditions have been passed, an internal 8-uA current source begins charging the
external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula:
tSS = VREF × CSS / Iss = 0.8 V × CSS / 8uA (4)
This equation can be rearranged as follows:
CSS = tSS × 8 μA / 0.8 V (5)
Use of a 4700-pF capacitor results in 0.5ms soft-start duration. This is a recommended value. Note that high
values of CSS capacitance will cause more output voltage droop when a load transient goes across the DCM-
CCM boundary. Use Equation 22 below to find the DCM-CCM boundary load current for the specific operating
condition. If a fast load transient response is desired for steps between DCM and CCM mode the soft-start
capacitor value should be less than 0.018µF.
As the soft-start input exceeds 0.8 V the output of the power stage will be in regulation. Note that the following
conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal 200 μA current
sink:
• The enable input being “pulled low”
• Thermal shutdown condition
• Overcurrent fault
• Internal VINUVLO
8.2.2.1.4 Output Capacitor, CO, Selection
None of the required output capacitance is contained within the module. At a minimum, the output capacitor must
meet the worst-case RMS current rating of 0.5 x ILR P-P, as calculated in Equation 23. Beyond that, additional
capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF is
generally required. Experimentation will be required if attempting to operate with a minimum value. Low ESR
capacitors, such as ceramic and polymer electrolytic capacitors are recommended.
8.2.2.1.4.1 Capacitance
Equation 6 provides a good first pass approximation of COfor load transient requirements:
CO≥ISTEP x VFB x L x VIN/ (4 x VOx (VIN — VO) x VOUT-TRAN) (6)
As an example, for 2-A load step, VIN = 24 V, VOUT = 12 V, VOUT-TRAN = 50 mV:
CO≥2 A x 0.8 V x 15 μH x 24 V / (4 x 12 V x ( 24 V — 12 V) x 50 mV) (7)
CO≥20 μF (8)
8.2.2.1.4.2 ESR
The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger VOUT peak-to-
peak ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the
overvoltage protection monitored at the FB pin. The ESR should be chosen to satisfy the maximum desired VOUT
peak-to-peak ripple voltage and to avoid overvoltage protection during normal operation. The following equations
can be used:
ESRMAX-RIPPLE ≤VOUT-RIPPLE / ILR P-P
where
• ILR P-P is calculated using Equation 23 below (9)
ESRMAX-OVP < (VFB-OVP - VFB) / (ILR P-P x AFB )
where
• AFB is the gain of the feedback network from VOUT to VFB at the switching frequency. (10)
As worst-case, assume the gain of AFB with the CFF capacitor at the switching frequency is 1.
The selected capacitor should have sufficient voltage and RMS current rating. The RMS current through the
output capacitor is:
I(COUT(RMS))=ILR P-P /√12 (11)
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Typical Application (continued)
8.2.2.1.5 Input Capacitor, CIN, Selection
The LMZ14202H module contains an internal 0.47 µF input ceramic capacitor. Additional input capacitance is
required external to the module to handle the input ripple current of the application. This input capacitance should
be as close as possible to the module. Input capacitor selection is generally directed to satisfy the input ripple
current requirements rather than by capacitance value. Worst-case input ripple current rating is dictated by
Equation 12:
I(CIN(RMS))≊1 / 2 x IOx√(D / 1-D)
where
• D ≊VO/ VIN (12)
(As a point of reference, the worst-case ripple current will occur when the module is presented with full load
current and when VIN =2xVO).
Recommended minimum input capacitance is 10-uF X7R ceramic with a voltage rating at least 25% higher than
the maximum applied input voltage for the application. It is also recommended that attention be paid to the
voltage and temperature deratings of the capacitor selected. It should be noted that ripple current rating of
ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor
manufacturer for this rating.
If the system design requires a certain maximum value of input ripple voltage ΔVIN to be maintained then
Equation 13 may be used.
CIN ≥IOx D x (1–D) / fSW-CCM xΔVIN (13)
If ΔVIN is 1% of VIN for a 24V input to 12V output application this equals 240 mV and fSW = 400 kHz.
CIN≥2 A x 12 V/24 V x (1– 12 V/24 V) / (400000 x 0.240 V) (14)
CIN≥5.2 μF (15)
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines.
8.2.2.1.6 ON-Time, RON, Resistor Selection
Many designs will begin with a desired switching frequency in mind. As seen in the Typical Characteristics
section, the best efficiency is achieved in the 300kHz-400kHz switching frequency range. Equation 16 can be
used to calculate the RON value.
fSW(CCM) ≊VO/ (1.3 x 10-10 x RON) (16)
This can be rearranged as
RON ≊VO/ (1.3 x 10 -10 x fSW(CCM) (17)
The selection of RON and fSW(CCM) must be confined by limitations in the ON-time and OFF-time for the COT
Control Circuit Overview section.
The ON-time of the LMZ14202H timer is determined by the resistor RON and the input voltage VIN. It is calculated
as follows:
tON = (1.3 x 10-10 x RON) / VIN (18)
The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON should
be selected such that the ON-time at maximum VIN is greater than 150 ns. The ON-timer has a limiter to ensure
a minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by Equation 19:
fSW(MAX) = VO/ (VIN(MAX) x 150 nsec) (19)
This equation can be used to select RON if a certain operating frequency is desired so long as the minimum ON-
time of 150 ns is observed. The limit for RON can be calculated as follows:
RON ≥VIN(MAX) x 150 nsec / (1.3 x 10 -10) (20)
If RON calculated in Equation 17 is less than the minimum value determined in Equation 20 a lower frequency
should be selected. Alternatively, VIN(MAX) can also be limited in order to keep the frequency unchanged.
Additionally, the minimum OFF-time of 260 ns (typical) limits the maximum duty ratio. Larger RON (lower FSW)
should be selected in any application requiring large duty ratio.
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0 200 400 600 800 1000
0
10
20
30
40
50
60
70
80
RADIATED EMISSIONS (dBV/m)
FREQUENCY (MHz)
Emissions (Evaluation Board)
EN 55022 Limit (Class B)
0.0 0.5 1.0 1.5 2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
-20 0 20 40 60 80 100 120 140
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
VIN = 15V
VIN = 24V
VIN = 42V
LMZ14202H
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Typical Application (continued)
8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Modes Selection
Operating frequency in DCM can be calculated as follows:
fSW(DCM)≊VOx (VIN-1) x 15 μH x 1.18 x 1020 x IO/ (VIN–VO) x RON2(21)
In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the
OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The
CCM operating frequency can be calculated using Equation 16 above.
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB≊VOx (VIN–VO) / ( 2 x 15μH x fSW(CCM) x VIN) (22)
The inductor internal to the module is 15 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ILR). ILR can be calculated with:
ILR P-P=VOx (VIN- VO) / (15 µH x fSW x VIN)
where
• VIN is the maximum input voltage and fSW is determined from Equation 16. (23)
If the output current IOis determined by assuming that IO= IL, the higher and lower peak of ILR can be
determined. Be aware that the lower peak of ILR must be positive if CCM operation is required.
8.2.3 Application Curves
Figure 47. Efficiency VOUT = 12 V Figure 48. Thermal Derating VOUT = 12 V, RθJA = 16°C/W
Figure 49. Radiated Emissions (EN 55022 Class B)
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9 Power Supply Recommendations
The LMZ14202H device is designed to operate from an input voltage supply range between 4.5 V and 42 V. This
input supply should be well regulated and able to withstand maximum input current and maintain a stable
voltage. The resistance of the input supply rail should be low enough that an input current transient does not
cause a high enough drop at the LMZ14202H supply voltage that can cause a false UVLO fault triggering and
system reset. If the input supply is more than a few inches from the LMZ14202H, additional bulk capacitance
may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but
a 47-μF or 100-μF electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout.
The high current loops that do not overlap have high di/dt content that will cause observable high frequency
noise on the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14202H.
Therefore place CIN1 as close as possible to the LMZ14202H VIN and GND exposed pad. This will minimize
the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor
should consist of a localized top side plane that connects to the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the GND
pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior. Provide the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, RFBT and RFBB, and the feed forward capacitor CFF, should be close to the FB pin.
Because the FB node is high impedance, maintain the copper area as small as possible. The traces from
RFBT, RFBB, and CFF should be routed away from the body of the LMZ14202H to minimize noise pickup.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing
so will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to
inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter
of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep
the junction temperature below 125°C.
10.1.1 Power Module SMT Guidelines
The recommendations below are for a standard module surface mount assembly
• Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
– For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern
– For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher
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VIN
GND
VIN
VO
Cin1 CO1
Loop 1 Loop 2
LMZ14202H VOUT
High
di/dt
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Layout Guidelines (continued)
• Stencil Thickness – 0.125 mm to 0.15 mm
• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
• Refer to application note SNAA214 for Reflow information
• Maximum number of reflows allowed is one
Figure 50. Sample Reflow Profile
Table 1. Sample Reflow Profile Table
MAX TEMP REACHED TIME ABOVE REACHED TIME ABOVE REACHED TIME ABOVE REACHED
PROBE (°C) MAX TEMP 235°C 235°C 245°C 245°C 260°C 260°C
1242.5 6.58 0.49 6.39 0.00 – 0.00 –
2242.5 7.10 0.55 6.31 0.00 7.10 0.00 –
3241.0 7.09 0.42 6.44 0.00 – 0.00 –
10.2 Layout Example
Figure 51. Critical Current Loops to Minimize
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0.0 0.5 1.0 1.5 2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
POWER DISSIPATION (W)
OUTPUT CURRENT (A)
VIN = 15V
VIN = 24V
VIN = 30V
VIN = 36V
VIN = 42V
RON
EN
SS
GND
FB
VIN
1 2 3 4 5 6 7
Top View
VIN
COUT
VOUT
RENT
RON
CSS
GND
Thermal Vias
VOUT
CIN
GND
RENB
CFF
RFBT
RFBB
GND Plane
EPAD
LMZ14202H
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Layout Example (continued)
Figure 52. PCB Layout
10.3 Power Dissipation and Board Thermal Requirements
For a design case of VIN = 24 V, VOUT = 12 V, IOUT =2A,TA(MAX) = 85°C , and TJUNCTION = 125°C, the device
must see a maximum junction-to-ambient thermal resistance of:
RθJA-MAX < (TJ-MAX - TA(MAX))/PD
This RθJA-MAX will ensure that the junction temperature of the regulator does not exceed TJ-MAX in the particular
application ambient temperature.
To calculate the required RθJA-MAX we need to get an estimate for the power losses in the IC. Figure 53 is taken
from the Typical Characteristics section and shows the power dissipation of the LMZ14202H for VOUT = 12 V at
85°C TA.
Figure 53. Power Dissipation VOUT = 12 V, TA= 85°C
Using the 85°C TApower dissipation data PDfor VIN = 24 V and VOUT = 12 V is estimated to be 1.8 W. The
necessary RθJA-MAX can now be calculated.
RθJA-MAX < (125°C - 85°C) / 1.8W (24)
RθJA-MAX < 22.2°C/W (25)
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0 10 20 30 40 50 60
0
5
10
15
20
25
30
35
40
THERMAL RESISTANCE JA(°C/W)
BOARD AREA (cm2)
0LFM (0m/s) air
225LFM (1.14m/s) air
500LFM (2.54m/s) air
Evaluation Board Area
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Power Dissipation and Board Thermal Requirements (continued)
To achieve this thermal resistance the PCB is required to dissipate the heat effectively. The area of the PCB will
have a direct effect on the overall junction-to-ambient thermal resistance. In order to estimate the necessary
copper area we can refer to the following Figure 54.Figure 54 is taken from the Typical Characteristics section
and shows how the RθJA varies with the PCB area.
Figure 54. Package Thermal Resistance RθJA 4-Layer Printed-Circuit-Board With 1-oz Copper
For RθJA-MAX< 22.2°C/W and only natural convection (that is, no air flow), the PCB area will have to be at least 30
cm2. This corresponds to a square board with approximately 5.5cm × 5.5cm (2.17in × 2.17in) copper area, 4
layers, and 1-oz copper thickness. Higher copper thickness will further improve the overall thermal performance.
Note that thermal vias should be placed under the IC package to easily transfer heat from the top layer of the
PCB to the inner layers and the bottom layer.
For more guidelines and insight on PCB copper area, thermal vias placement, and general thermal design
practices refer to Application Note AN-2020 (SNVA419).
24 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14202H
LMZ14202H
www.ti.com
SNVS691H –JANUARY 2011–REVISED OCTOBER 2015
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documents, please see the following:
•AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module,SNVA425
•Evaluation Board Application Note AN-2024,SNVA422
•AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules,SNVA424
•AN-2020 Thermal Design By Insight, Not Hindsight,SNVA419
•Evaluation Board Application Note AN-2024,SNVA422
•Design Summary LMZ1 and LMZ2 Power Modules,SNAA214
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LMZ14202H
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMZ14202HTZ/NOPB ACTIVE TO-PMOD NDW 7 250 RoHS (In
Work) & Green
(In Work)
CU SN Level-3-245C-168 HR -40 to 125 LMZ14202
HTZ
LMZ14202HTZE/NOPB ACTIVE TO-PMOD NDW 7 45 RoHS (In
Work) & Green
(In Work)
CU SN Level-3-245C-168 HR -40 to 125 LMZ14202
HTZ
LMZ14202HTZX/NOPB ACTIVE TO-PMOD NDW 7 500 RoHS (In
Work) & Green
(In Work)
CU SN Level-3-245C-168 HR -40 to 125 LMZ14202
HTZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2017
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMZ14202HTZ/NOPB TO-
PMOD NDW 7 250 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2
LMZ14202HTZX/NOPB TO-
PMOD NDW 7 500 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMZ14202HTZ/NOPB TO-PMOD NDW 7 250 367.0 367.0 45.0
LMZ14202HTZX/NOPB TO-PMOD NDW 7 500 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2018
Pack Materials-Page 2
MECHANICAL DATA
NDW0007A
www.ti.com
TZA07A (Rev D)
TOP SIDE OF PACKAGE
BOTTOM SIDE OF PACKAGE
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