© Semiconductor Components Industries, LLC, 2015
July, 2018 − Rev. 1 1Publication Order Number:
TCP−4182UB/D
TCP-4182UB
8.2 pF Passive Tunable
Integrated Circuits (PTIC)
Introduction
ON Semiconductor’s PTICs have excellent RF performance and
power consumption, making them suitable for any mobile handset or
radio application. The fundamental building block of our PTIC
product line is a tunable material called ParaScant, based on Barium
Strontium Titanate (BST). PTICs have the ability to change their
capacitance from a supplied bias voltage generated by the Control IC.
The 8.2 pF ultra−high tuning PTICs are available as wafer-level chip
scale packages (WLCSP).
Key Features
•Ultra−High Tuning Range and Operation up to 24 V
•Usable Frequency Range: from 700 MHz to 2.7 GHz
•High Quality Factor (Q) for Low Loss
•High Power Handling Capability
•Compatible with PTIC Control IC TCC-10x, 20x
•WLCSP Package: 0.609 x 1.009 x 0.310 mm (4 bump)
•These devices are Pb−Free and RoHS Compliant
Typical Applications
•Multi-band, Multi-standard, Advanced and Simple Mobile Phones
•Tunable Antenna Matching Networks
•Tunable RF Filters
•Active Antennas
Device Package Shipping†
ORDERING INFORMATION
www.onsemi.com
TCP−4182UB−DT WLCSP4
(Pb−Free) 4000 Units /
7” Tape & Reel
FUNCTIONAL BLOCK DIAGRAM
PTIC Functional Block Diagram
MARKING DIAGRAM
PTIC
Bias
RF1 RF2
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer t o our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
WLCSP4
1.009x0.609
CASE 567LZ
TCP−4182UB
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3
TYPICAL SPECIFICATIONS
Representative Performance Data at 255C
Table 2. PERFORMANCE DATA
Parameter Min Typ Max Units
Operating Bias Voltage 1.0 24 V
Capacitance (Vbias = 2 V) 7.38 8.20 9.02 pF
Capacitance (Vbias = 24 V) 1.570 1.745 1.919 pF
Tuning Range (1 V - 24 V) 4.80 5.30 6.00
Tuning Range (2 V - 24 V) 4.20 4.70 5.30
Leakage Current (WLCSP) 0.5 mA
Operating Frequency 700 2700 MHz
Quality Factor @ 700 MHz, 10 V 100
Quality Factor @ 2.4 GHz, 10 V 70
IP3 (Vbias = 2 V) [1,3] 70 dBm
IP3 (Vbias = 24 V) [1,3] 85 dBm
2nd Harmonic (Vbias = 2 V) [2,3] -75 dBm
2nd Harmonic (Vbias = 24 V) [2,3] -85 dBm
3rd Harmonic (Vbias = 2 V) [2,3] -40 dBm
3rd Harmonic (Vbias = 24 V) [2,3] -70 dBm
Transition Time (Cmin ³ Cmax) [4] 80 ms
Transition Time (Cmax ³ Cmin) [4] 70 ms
1. f1 = 850 MHz, f2 = 860 MHz, Pin 25 dBm/Tone
2. 850 MHz, Pin +34 dBm
3. IP3 and Harmonics are measured in the shunt configuration in a 50 W environment
4. RFIN and RFOUT are both connected to DC ground
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4
Representative performance data at 255C for 8.2 pF WLCSP Package
Figure 2. Capacitance Figure 3. Harmonic Power*
Figure 4. IP3* Figure 5. Q*
*Data shown is representative only.
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Units
Input Power +40 dBm
Bias Voltage +25 (Note 5) V
Operating Temperature Range −30 to +85 °C
Storage Temperature Range −55 to +125 °C
ESD − Human Body Model Class 1B JEDEC HBM Standard (Note 6)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
5. WLCSP: Recommended Bias Voltage not to exceed 24 V.
6. Class 1B defined as passing 500 V, but may fail after exposure to 1000 V ESD pulse.
TCP−4182UB
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5
ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE
The following assembly considerations should be observed:
Cleanliness
These chips should be handled in a clean environment.
Electro-static Sensitivity
ON Semiconductor’s PTICs are ESD Class 1B sensitive.
The proper ESD handling procedures should be used.
Mounting
The WLCSP PTIC is fabricated for Flip Chip solder
mounting. Connectivity to the RF and Bias terminations on
the PTIC die is established through SAC305 solder balls
with 65 mm nominal height (45 mm to 85 mm height
variation). The PTIC die is RoHS-compliant and compatible
with lead-free soldering profile.
Molding
The PTIC die is compatible for over-molding or
under-fill. Figure 6. Reflow Profile
ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES
When configuring the PTIC in your specific circuit
design, at least one of the RF terminals must be connected
to DC ground. If minimum transition times are required, DC
ground on both RF terminals is recommended. To minimize
losses, the PTIC should be oriented such that RF2 is at the
lower RF impedance of the two RF nodes. A shunt PTIC, for
example, should have RF2 connected to RF ground.
Figure 7. PTIC Orientation Functional Block
Diagram
Bias
RF ANT
RF1
(PTIC Pad)
RF2
(PTIC Pad)
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PART NUMBER DEFINITION
Table 4. PART NUMBERS
Part Number
Capacitance
Package*
2 V 24 V
TCP−4182UB-DT 8.20 1.822 4-bump WLCSP
*See PTIC package dimensions on following page.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
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7
PACKAGE DIMENSIONS
WLCSP4, 1.009x0.609
CASE 567LZ
ISSUE O
SEATING
PLANE
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
4. BACKSIDE TAPE APPLIED TO IMPROVE
PIN 1 MARKING.
2X DIM
AMIN MAX
0.275
MILLIMETERS
A1
D1.009 BSC
E
b1 0.044 0.094
e0.420 BSC
0.345
È
E
D
A B
PIN A1
REFERENCE
0.05 C
B
A
0.06 C
A1 C
0.045 0.085
0.609 BSC
0.05 C
2X TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 3
e
e1 0.400 BSC
12
b0.079 0.129
A
DETAIL A
DET AIL A
A0.05 BC
0.03 C
4X b
e1
4X b1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
RECOMMENDED
DETAIL C
DETAIL C
NOTE 4
TAPE
DIMENSIONS: MILLIMETERS
PACKAGE
OUTLINE
A1
0.13
4X
0.55
0.55
0.15
4X
TCP−4182UB/D
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