intel. 270010 1M (128K x 8) CHMOS EPROM m JEDEC Approved EPROM Pinouts w Fast Programming 32-Pin DIP, 32-Pin PLCC Quick-Pulse Programming Simple Upgrade from Lower , Algorithm Densities _ Programming Time as Fast as 15 u Complete Upgrade Capability to Higher Seconds Densities a High-Performance 120 ns; + 10% V, m Versatile EPROM Features. , cc CMOS and TTL Compatibility 30 mA icc Active Two Line Control w Surface Mount Packaging Available Smailest 1 Mbit Footprint in SMT Intels 27C010 is a 5V only, 1,048,576-bit, Erasable Programmable Read Only Memory, organized as 129,536 words of 8 bits. It is pin compatible with lower density DIP EPROMs (JEDEC) and provides for simple upgrades to 8 Mbits in the future in both DIP and PLCC..- The 27C010 represents state-of-the-art 1: micron CHMOS manufacturing technology while providing un- equaled performance. Its 120 ns speed (tacc) offers no-wait-state operation with high performance CPUs in applications ranging from numerical control to office automation to telecommunications. Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic DIP (CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the design is in full production, the plastic DIP (PDIP) one-time programmable part provides a lower cost alterna- tive that is well adapted for auto insertion. In addition to the JEDEC 32-pin DIP package, Intel also offers a 32-lead PLCC version of the 270010. This one-time-programmable surface mount device is ideal where board space consumption is a major concern or where surface mount manufacturing technology is being implemented across an entire production line. * The 27C010 is equally at home in both a TTL or CMOS environment. it programs as fast as 15 seconds using Intels industry leading Quick-Pulse Programming algorithm. DATA OUTPUTS Veco 09-07 GND o_> (TN, OE OUTPUT ENABLE Pam CHIP ENABLE AND PROG LOGIC ! DECODER -GATING Ao-Ais > > ADDRESS { " x : oaa.s INPUTS | >") 1,048,576-BIT >| DECODER : CELL MATRIX P_ e 290174-1 Figure 1. Block Diagram November 1990 5-38 Order Number: 290174-004270010 Pin Names Ao-A1g | ADDRESSES cE CHIP ENABLE cE OUTPUT ENABLE Qo-07 | OUTPUTS PGM =| PROGRAM NC NO INTERNAL CONNECT 27C010 4Mbit | 2Mbit | 512K | 256K 256K 512K 2Mbit | 4Mbit | SMbit Veep Vpp VppC]t 32D Voc Voc | Voc Voc Ate Ais Aye OQ2 310 Pou PEN Ate Aig Ais Ais Ais | Vpp ACs sone Veco | Veco Aq | Az AN7 Ar2 Ai2 Ai2 | At Ayes 2D Ay, Ata Ais Aia | Ata Aw Az A; Ay Az 47s 28 As Aug Aig Aig | Ais Aig 46 Ae Ag As apis 27.0) Ag As |. As Ag Ae Ae As As As As asQ]7 2605 Ay Ag Ag Ag Aa Ag Ag Ag Ag Ag aae 2s Ay Ay Ay Au | An Ay Ag Ag Ag Ag aso 24D OE OE | OE/Vpp| SE | OE | OE/Vpp Ao Ao Ao Ao 4,10 23 Ayo Aio A110 Avo Aio Ato Ay Ai Ay Ay Aci 2DE te cE | CE cE Ao Ao Ao Ao Aol 12 21107 O7 07 O7 O7 O7 Oo Oo Oo Oo Oo F413 20F) 0, Os Os Os O6 O6 0, 0; O1 O; o,Cj14 197505 Os Os Os Os Os Oa Oo Oo Oo Oo TJ 15- 18 0, On O4 % 4 Os GND | GND | GND | GND GUO Ee whid, 03 03 03; | 03 0; 290174-2 Figure 2. DIP Pin Configuration Ay aucasexxs)} tf | tf | ti] ti td t N27CO10 (128Kx8) | Aya | Ays | Ave | Yep | Yeo | Pow] Ne 1 / WEE EEE t Le] v > a } 8 = { z { 32 LEAD PLCC 0.450" x 0.550" TOP VIEW w G > S | ! = a t t EFEEEEEAo * t wo Nelalalcialataloiay ; Ye 0, GND \ 4 TAAL | { ~le PS] 290174-3 Figure 3. PLCC Lead Configuration 5-39intel. 270010 EXTENDED TEMPERATURE (EXPRESS) EPROMs The Intel EXPRESS EPROM family receives addi- tional processing to enhance product characteris- tics. EXPRESS processing is available for several densities allowing the appropriate memory size to match system requirements. EXPRESS EPROMs are available with 168 +8 hour, 125C dynamic burn-in using Intels standard bias configuration. This processing meets or exceeds most industry burn-in specifications. The EXPRESS product family is available in both 0C to +70C and 40C to +85C operating temperature range versions. Like -all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AQL. This allows reduc- tion or elimination of incoming testing. EXPRESS EPROM FAMILY OPTIONS . Packaging PRODUCT DEFINITIONS Speed , CERDIP Type) Operating Temperature) Burn-in 125C (hr) 150V10 QTL Q OC to 70C 168 +8 T 40C to 85C None L 40C to 85C 168 +8 READ OPERATION DC CHARACTERISTICS _. Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for: TD27C010(2) Symbol Parameter LD27C010 Test Condition Min Max ; Ioc() Voc Operating Current (mA) 30 OE = CE = Vi, Tambient = 40C Vcc Operating Current 30. | OE=CTE=WMYy at High Temperature (mA) Vpp = Voc, Tambient = 85C NOTES: 1. Maximum current is with outputs Op to O7 unloaded. 2. D refers to the CERDIP package. Vpe al By Voc 1 AygQQ2 31 he Ay Qs spine. ays 2B Ay, ays Bars acs 27s ag 7 2DAy me 7 asa, AsCh9 24 F OE A, O10 23D Ao At 2 Ave Poses HE. fal aias aser Leese 290174-4 CE = +5V R=1kN Vog= +5V Vpp = +5V. GND = OV CE = GND PGM = +5V Ais Binary Sequence from Ag to Aig 290174-5 Burn-in Bias and Timing Diagrams -40intel. 270010 ABSOLUTE MAXIMUM RATINGS* - Operating Temperature ............. 0C to 70C(1) Temperature Under Bias ........ ++ 10C to 80C Storage Temperature.......... ++. 65C to 125C Voltage on Any Pin (except Ag, Voc and Vpp) with Respect toGND ........0.6V to 6.5V(2, 8) Voltage on Ag with Respect to GND ............. 0.6V to 13.0V(2) Vpp Program Voltage with Respect to GND........... 0.6V to 14V(2) Voc Supply Voltage with Respect to GND .......... 0.6V to 7.0V(2) NOTICE: This is a production data sheet. The specifi. cations are subject to change without notice. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. READ OPERATION DC CHARACTERISTICS(1) Voc = 5.0V + 10% Symbol Parameter Notes Min Typ Max Unit Test Condition lu Input Load Current 7 0.01 1.0 vA | Vin = OV to 5.5V lLo Output Leakage Current +10 vA | Vout = OV to 5.5V Isg Voc Standby Current 1.0 mA | CE = Vin 100 pA | CE = Vcc +0.2V lec Voc Operating Current 3 30 mA | CE=Vi f = 5 MHz, Iqyy = OMA Ipp Vpp Operating Current 3 10 bA | Vpp = Voc los Output Short Circuit Current 4,6 100 mA Vic Input Low Voltage -0.5 0.8 Vv Vin Input High Voltage 2.0 Voc + 0.5 Vv Vou Output Low Voltage 0.45 v lo. = 2.1mA Vou Output High Voltage 2.4 v loH = 400 pA Vpp Vpp Operating Voltage 5 Voc 0.7 Voc Vv NOTES: 1. Operating temperature is for commercial product detined by this specification. Extended temperature options are available in EXPRESS versions. 2. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods <20 ns. Maximum DC voltage on input/output pins is Voc + 0.5V which, during transitions, may overshoot to Voc + 2.0V for periods <20 ns. 3. Maximum active power usage is the sum Ipp + loc. Maximum current is with outputs Oo to O7 unloaded. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. Vpp may be connected directly to Voc, or may be one diode voltage drop below Vcc. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 6. Sampled, not 100% tested. 7. Typical limits are at Voc = 5V, Ta = 25C. 8. Absolute Maximum Ratings apply to NC pins. 5-41intel. 276010 READ OPERATION AC CHARACTERISTICS(1) Voc = 5.0V + 10% 27C010-150V 10 27C010-200V10 Versions(4) Veco 10% | 27C010-120V10 P27C010-150V10 | P27C010-200V10 . N27C010-150V10 | N27C010-200v10 | Units Symbol Parameter Notes Min Max Min Max Min Max tacc Address to Output Delay ; 120 150 . 200 ns toe CE to Output Delay 2 120 150 200 ns toe GE to Output Delay 2 55 60 70 ns tor OE High to Output High Z| 3 30 50 60 | -ns tou Output Hold from 3 0 0 0 ns Addresses, CE or OE Change-Whichever is First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE may be delayed up to tce~tog after the falling edge of CE without impact on tog. 3. Sampled, not 100% tested. : 4. Model Number Prefixes: No Prefix = CERDIP, P = PDIP, N = PLCC. 5-42intel. 276010 CAPACITANCE(1) T, = 25C, f = 1MHz Symbol Parameter -| Typ) +-Max | Unit | Conditions Cin " Input Capacitance 4 8 pF | Vin = OV Cout Output Capacitance | 8. | .12 PF | Vout = OV Cyvpp Vpp Capacitance - 18 25 pF Vpp = OV NOTES: 1. Sampled, not 100% tested. 2. Typical values are for Ta= 25C and nominal supply voltages. AC INPUT/OUTPUT REFERENCE WAVEFORM AC TESTING LOAD CIRCUIT - 1.3 . 2.4 55 - . . : 1N914 wr KX > test Ponts ; oureut 0.8 te 0.8 0.45 =) . Re : 290174-6 DEVICE . UNDER OUT AC test inputs are driven at Vo (2.4V Tr) for a Logic 1 and TEST c Voi (0.45V Tr) for @ Logic 0. Input timing begins at Viq (2.0V L, tT and Vi, (0.8V tT). Output timing ends at V4 and Vi, Input L Rise and Fall Times (10% to 90%) < 10 ns. = 290174-7 CL = 100 pF re C, Includes Jig Capacitance Ry = 3.3 KN. . : AC WAVEFORMS vu y steel ADDRESSES ADDRESS Vie N amoee _ Yiu Vie - . eooe / oe tee | oe rm LAL | face tor ., won II, wan OuTPuTs . . VALID OUTPUT te CQ 2 290174-8 5-43intel. 270010 DEVICE OPERATION The Mode Selection tabie lists 27C010 operating modes. Read Mode requires a single 5V power supply. All inputs, except Vcc and Vpp, and Ag during intgligent Identifier Mode, are TTL or CMOS. "Table 1. Mode Selection Mode Notes cE OE PGM | Ag | Ao Vpp Vcc Outputs Read 1 Vic | Vie X Xx xX | Veco | Vec Dout Output Disable Viv | Vie X Xx X | Vec-| Voc High Z Standby Viw |X x Xx X | Voc | Voc | HighZ Program 2. 1 Ve] Vin | Vin. xX X | Veep | Yop | Din Program Verify Vit Vit Vin x xX Vpp Vcp Dout Program Inhibit Vin x x x xX Vpp Vop High Z intgligent Manufacturer 2,3 Vit ViL Xx Vip Vit Voc Voc 89H Identifier | Device vi | vi | x | Vo | va | Voc | Veo | 35H NOTES: 1. X can be Vi_ or Vix. 2. See DC Programming Characteristics for Vop, Vpp and Vip voltages. 3. AyAg, Ayo-At6 = Vit Read Mode The 27C010 has two control functions: both must be enabled to obtain data at the outputs. CE is the pow- er control and device select. controls the output buffers to gate data to the outputs. With addresses stable, the address access time (tacc) equals the delay from CE to output (toe). Outputs display valid data tog after OEs falling edge, assuming tacc and tce times are met. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. Two Line Output Control EPROMs are often used in larger memory arrays. Intel provides two control inputs to accommodate multiple memory connections. Two-line control pro- vides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these two control inputs, an ad- dress decoder should enable CE, while OE should be connected to all memory devices and the sys- tems READ control line. This assures that only se- lected memory devices have active outputs while deselected memory devices are in Standby Mode. Standby Mode Standby Mode substantially reduces Vcc current. When = Vin, the outputs are in a high imped- ance state, independent of OE. 5-44intel. 270010 Program Mode Caution: Exceeding 14V on Vpp will permanently. damage the device. Initially, and after each erasure, all EPROM bits are . in the 1 state. Data is introduced by selectively Programming Os into the desired bit locations: Al- though only Os are programmed, the data word can contain both 1s and Os. Ultraviolet light era- sure is the only way to change 0s to 1s. Program Mode is entered when Vpp is raised to 12.75V. Data is introduced by applying an 8-bit word to the output pins. Pulsing POM low while CE = Vi and OE = Vjy programs that data into the device. Program Verify A verify should be performed following a program operation to determine that bits have been correctly: programmed. With Vcc at 6.25V, a substantial pro- gram margin is ensured. The verify is performed with after falis low. Program Inhibit Program Inhibit Mode allows parallel programming of multiple EPROMs with different data. CE-high in- hibits programming of non-targeted devices. Except for CE, parallel EPROMs may have common inputs. inteligent Identifier Mode The intgligent Identifier. Mode will determina an EPROMs manufacturer and device type, allowing programming equipment to automatically match a device with its proper programming algorithm. This mode is activated when_a programmer forces 12V +0.5V on Ag. With CE, OE, Ay-Ag, and Aio- Aig at Vi_, Ao = Vit will present the manufacturer code and Ap = Viy the device code. This rhode functions in the 25C +5C ambient temperature range required during programming. UPGRADE PATH Future upgrade to 2-Mbit, 4-Mbit, and 8-Mbit densi- ties are easily accomplished due to the standardized pin configuration of the 27C010. When the 270010 is in Read Mode, the PGM input becomes non-func- CE at and PGM at Vy. Valid data is available tog . E tional. The PGM and NC pins may be Vj, or Vi. This : allows: address lines A17Ajg to be routed directly to these inputs in anticipation of future density up- grades. A jumper between Vcc and Aj4g allows fur- ther upgrade using the Vpp pin. Systems designed for. 1-Mbit program memories today can be upgrad- ed to higher densities (2-Mbit, 4-Mbit, and 8-Mbit) in th future with no circuit board changes. SYSTEM CONSIDERATIONS EPROM power switching characteristics require _. areful device decoupling. System designers are in- terested in-3 supply current issues: standby current levels (Igg), active current levels (Icc), and transient current peaks produced by falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor . selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its Voc and GND. This high fre- quency, low inherent-inductance capacitor should .be placed as close as possible to the device. Addi- tionally, for every 8 devices, a 4.7 uF electrolytic sapacitor should be placed at the arrays power sup- ply connection between Voc and GND. The bulk ca- Pacitor will overcome voltage slumps caused by PC board trace inductances. ERASURE CHARACTERISTICS Erasure begins when EPROMs are exposed to light with wavelengths shorter than approximately 4000 - Angstroms (A). It should be noted that sunlight and certain fluorescent lamps have wavelengths in the 3000A-4000A range. Data shows that constant ex- posure to room level fluorescent lighting can erase an EPROM in approximately 3 years, while it takes approximately 1 week when exposed to direct sun- light. If the device is exposed to these lighting condi- tions for extended periods, opaque labels should be ~ placed over the window to prevent unintentional era- sure. - : The recommended erasure procedure is exposure to. ultraviolet light of wavelength 2537A. The inte- grated dose (UV intensity < exposure time) for era- sure should be a minimum of 15 Wsec/cem2. Erasure time is approximately 15 to 20 minutes using an ul- traviolet lamp with a 12000 .W/cm2 power rating. The EPROM should be placed within 1 inch of the lamp tubes. An EPROM can be permanentty dam- aged if the integrated dose exceeds 7258 Wsec/ em? (1 week @ 12000 W/cm2). , 5-4527C010 INCREMENT ADDRESS Voc = Vpp = 5.0V COMPARE ALL BYTES TO ORIGINAL DATA PAS: FAILED Ss DEVICE PASSED 290174-9 Figure 4. Quick-Puise Programming Algorithm Quick-Pulse Programming Algorithm The Quick-Pulse programming algorithm programs Intels 27C010. Developed to substantially reduce programming throughput, this algorithm can program the 27C010 as fast as 15 seconds. Actual program- ming time depends on programmer overhead. The Quick-Pulse programming algorithm employs a 100 ys pulse followed by a byte verification to deter- 5-46 mine when the addressed byte has been successful- ly programmed. The algorithm terminates if 25 at- tempts fail to program a byte. The entire program pulse/byte verify sequence is performed with Vpp = 12.75V and Vcc = 6.25V. When programming is complete, all bytes are com- pared to the original data with Voc = Vpp = 5.0V.intgl. 270010 DC PROGRAMMING CHARACTERISTICS T, = 25C +5C Symbol Parameter Notes | Min Typ | Max | Unit Test Condition lu Input Load Current : 1 BA | Vin = Vicor Vin Icp Voc Program Current - 4 40 | mA | CE = PGM= Vy Ipp Vpp Program Current 4 50 | mA | CE = PGM= Vy VIL Input Low Voltage -0.1 0.8 Vv Vin Input High Voltage 2.4 6.5 Vv VoL Output Low Voltage (Verify) , 0.45 Vv lol = 2.4mA Vou Output High Voltage (Verify) 35 V | lon = -2.5mA Vip Ag intgligent Identifier Voltage 11.5 12.0 | 12.5 Vv Vpp _- | Vpp Program Voltage 2,3 12.5 | 12.75 | 13.0 v Vop Voc Supply Voltage (Program) 2 6.0 6.25 6.5 Vv AC PROGRAMMING CHARACTERISTICS(4) 1, = 25C +5C Symbol Parameter Notes Min Typ Max Unit tvcs Vop Setup Time 2 2 ps tyes Vpp Setup Time 2 2 en) toes CE Setup Time 2 ps tas Address Setup Time 2 BS tos Data Setup Time 2 ps tpw PGM Program Pulse Width _ 95 100 105 BS tov Data Hold Time 2 ps toes ' OE Setup Time 2 > BS toe Data Valid from OE 5 150 ns tore OE High to Output High Z 5,6 0 : 130 ns taH Address Hold Time 0 ps NOTES: 1. Maximum current is with outputs O9-O7 unloaded. 2. Vcp must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 3. When programming, a 0.1 uF capacitor is required across Vpp and GND to suppress spurious voltage transients which can damage the device. 4. See AC Input/Output Reference Waveform for timing measurements. 5. toe and tprp are device characteristics but must be accommodated by the programmer. 6. Sampled, not 100% tested. 5-47intel. 270010 PROGRAMMING WAVEFORMS ventry, } , . te ADDRESSES ADDRESS STABLE Va t + as >t . tan m HIGH Z f - DATA DATA IN STABLE . DATA OUT VALID | Vie we lore tos __pf ae 12.75V 2, Vep $.0v tyes 6.25V 7 Veco ] 5.0v bets Vin ce Vie tces __] Vj) estenneronsmnemmanad 2 _ PGM Vu tow foes toe Vin - _ OE \ : 2 Ma 290174-10 REVISION HISTORY Number : Description Revised general datasheet structure, text to improve clarity. 04 Added PDIP package : Combined TTL/NMOS and CMOS Read Operation DC Characteristics tables. Deleted 4 Meg and 8 Meg PLCC pinout references. 5-48