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ENPIRION
EN5336QI
3A Voltage Mode Synchronous Buck PWM
DC-DC Converter with Integrated Inducto
r
External Output Voltage Programming
Description
This Enpirion solution is a Power System on
Silicon DC-DC converter. It is specifically
designed to meet the precise voltage and fast
transient requirements of present and future
high-performance, low-power processor, DSP,
FPGA, memory boards and system level
applications in a distributed power architecture.
Advanced circuit techniques, ultra high switching
frequency, and very advanced, high-density,
integrated circuit and proprietary inductor
technology deliver high-quality, ultra compact,
non-isolated DC-DC conversion. This device
requires only an input, output, and small soft-
start programming capacitor and a resistor
divider.
The Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified board design, layout and
manufacturing requirements. In addition, a
reduction in the number of vendors required for
the complete power solution helps to enable an
overall system cost savings.
All Enpirion products are RoHS compliant and
lead-free manufacturing environment compatible.
Typical Application Circuit
XFB
47µF
15 nF
VOUT
POK
PGNDAGND
SS
PVIN
AVIN
XOV
VOUT
VIN
22µF
Figure 1. Simple Layout.
Features
• Integrated INDUCTOR, MOSFETS, Controller
• Footprint 1/3rd that of competing solutions.
• Minimal external components.
• Up to 10W continuous output power.
• 5MHz operating frequency.
• High efficiency, up to 93%.
• VOUT accuracy 2% over line, load and temp.
• Wide input voltage range of 2.375V to 5.5V.
• External resistor divider output voltage select.
• Output enable pin and Power OK signal.
• Programmable soft-start time.
• Programmable over-current protection.
• Programmable over-voltage protection.
• Thermal shutdown, short circuit, and UVLO.
• RoHS compliant, MSL level 3, 260C reflow.
Applications
• Point of load regulation for low-power
processors, network processors, DSPs,
FPGAs, and ASICs
• Notebook computers, servers, workstations
• Broadband, networking, LAN/WAN, optical
• Low voltage, distributed power architectures
with 2.5V, 3.3V or 5V rails
• DSL, STB, DVR, DTV, iPC
• Ripple sensitive applications
Ordering Information
Part Number Temp Rating
(°C) Package
EN5336QI-T -40 to +85 44-pin QFN T&R
EN5336QI-E QFN Evaluation Board
Rev 1.0 November 2006 EN5336QI
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Pin Configuration
Below is a top view diagram of the EN5336QI package.
Figure 2. Pin-out diagram, top view.
NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or
voltage. Failure to follow this guideline may result in part malfunction or damage.
NOTE: All perimeter pins must be soldered to PCB.
Rev 1.0 November 2006 EN5336QI
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Pin Descriptions
PIN NAME FUNCTION
1-7 NC
NO CONNECT – Do not electrically connect these pins to each other or to any other electrical
signal. CAUTION!: May be internally connected.
8-14 VOUT
Regulated converter output. Connect these pins to the load and place output capacitor from
these pins the PGND pins 17-18
15-16 NC
NO CONNECT – Do not electrically connect these pins to each other or to any other electrical
signal.
CAUTION!: Internally connected to switching node. Take care to route signals away from
these pins.
17-20 PGND
Input/Output power ground. Connect these pins to the ground electrode of the Input and
output filter capacitors. Refer to layout guideline section for details.
21-24 PVIN Input power supply. Connect to input power supply. Decouple with input capacitor to PGND.
25-26 NC
NO CONNECT – Do not electrically connect these pins to each other or to any other electrical
signal. CAUTION!: May be internally connected.
27 ROCP
Optional Over Current Protection adjust pin. Place ROCP resistor between this pin and AGND
(pin 40) to adjust the over current trip point.
28 AVIN Analog voltage input for the controller circuits. Connect this pin to the input power supply.
29 AGND Analog ground for the controller circuits.
30-31 NC
NO CONNECT – Do not electrically connect these pins to each other or to any other electrical
signal. CAUTION!: May be internally connected.
32 XFB Feedback pin for external voltage divider network.
33 XOV Over voltage programming feedback pin.
34 NC
NO CONNECT – Do not electrically connect this pin to any electrical signal.
CAUTION!: May be internally connected.
35 POK
Power OK is an open drain transistor for power system state indication. POK is a logic high
when VOUT is with -10% to +20% of VOUT nominal.
36 NC
NO CONNECT – Do not electrically connect this pin to any electrical signal.
CAUTION!: May be internally connected.
37 SS
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value
of this capacitor determines the startup time.
38 EAIN Optional Error Amplifier input. Allows for customization of the control loop response.
39 EAOUT Optional Error Amplifier output. Allows for customization of the control loop response.
40 COMP Optional Error Amplifier Buffer output. Allows for customization of the control loop response.
41 ENABLE
Input Enable. Applying a logic high, enables the output and initiates a soft-start. Applying a
logic low disables the output.
42-44 NC
NO CONNECT – Do not electrically connect these pins to each other or to any other electrical
signal. CAUTION!: May be internally connected.
Rev 1.0 November 2006 EN5336QI
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Block Diagram
(+)
(-)
Error
Amp
VOUT
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)
PWM
Comp
PVIN
ENABLE
Compensation
Network
Bandgap
Reference
PGND
Voltage
Selector XFB
EAIN
EAOUT
ROCP
SS
Reference
Voltage
selector
COMP
Over Voltage
power
Good
Logic
Over
Voltage VOUT
POK
XOV
Figure 3. System block diagram.
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation
beyond recommended operating conditions is not implied. Stress beyond
Absolute maximum ratings may cause permanent damage to the device. Exposure
to absolute maximum rated conditions for extended periods may affect device
reliability.
PARAMETER SYMBOL MIN MAX UNITS
Input Supply Voltage VIN -0.5 7.0 V
Input Voltage – Enable -0.5 VIN V
Input Voltage – XFB, XOV -0.5 VIN V
Voltages on: EAIN, EAOUT, COMP -0.5 2.5 V
Storage Temperature Range TSTG -65 150 °C
Maximum Operating Junction Temperature TJ-ABS Max 150 °C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C
ESD Rating (based on Human Body Model) 2000 V
Rev 1.0 November 2006 EN5336QI
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Thermal Characteristics
PARAMETER SYMBOL MIN TYP MAX UNITS
Operating Junction Temp TJ-40 +125 °C
Thermal Shutdown TSD 150 °C
Thermal Shutdown Hysteresis TSDH 25 °C
Thermal Resistance: Junction to Case θJC 3 °C/W
Thermal Resistance: Junction to Ambient θJA 25 °C/W
Electrical Characteristics
NOTE: VIN=5.5V over operating temperature range unless otherwise noted. Typical values are at TA =
25°C.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Input
Voltage VIN 2.375 5.5 V
Regulated
Feedback Voltage VXFB 0.75
V
Shut-Down Supply
Current ISENABLE=0V 100
µA
Switching Frequency FOSC 5 MHz
Thermal Overload
Trip Point TJ 150 °C
VOUT
Output Voltage
Regulation VOUT Over line, load and temperature -2.0 2.0 %
Maximum Continuous Output Curren t
Maximum Continuous
Output Current IOUT_Max_Cont 3 A
Over Current Trip
Piont IOCP 4.5 A
Enable Operation
Disable Threshold VDISABLE
Max voltage to ensure the converter is
disabled 0.8 V
Enable Threshold VENABLE
2.375V ≤ VIN ≤ 5.5V
5.5V < VIN
1.8
2.0 V
Voltage Select Operation
Power OK Operation
POK low voltage VPOK 0.4 V
Max POK Voltage VPOK 5.5 V
Rev 1.0 November 2006 EN5336QI
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Typical Performance Characteristics
50
55
60
65
70
75
80
85
90
95
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
Lo a d C urre nt (A )
Effic ien cy (%)
VIN=5.0V
V
OUT
= 3.3V
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
= 1.5V
V
OUT
= 1.2V
50
55
60
65
70
75
80
85
90
95
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
Lo a d C urre nt (A )
Effic ien cy (%)
VIN=5.0V
V
OUT
= 3.3V
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
= 1.5V
V
OUT
= 1.2V
50
55
60
65
70
75
80
85
90
95
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
Lo a d C urre nt ( A )
Efficiency (%)
V
IN
=3.3V
V
OUT
= 0.8V
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
= 1.5V
V
OUT
= 1.2V
50
55
60
65
70
75
80
85
90
95
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
Lo a d C urre nt ( A )
Efficiency (%)
V
IN
=3.3V
V
OUT
= 0.8V
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
= 1.5V
V
OUT
= 1.2V
Efficiency versus Load, VIN = 5.0V Efficiency versus Load, VIN = 3.3V
Load transient, 0 – 3A, VIN/VOUT = 5.5V/1.2V Load transient, 0 – 3A, VIN/VOUT = 5.5V/3.3V
Start-up waveform, VIN/VOUT = 5.5V/1.2V Shut-down waveform, VIN/VOUT = 5.5V/1.2V
Rev 1.0 November 2006 EN5336QI
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Theory of Operation
Synchronous Buck Converte r
The EN5336QI is a synchronous, programmable
power supply with integrated power MOSFET
switches and integrated inductor. The nominal
input voltage range is 2.4-5.5V. The output
voltage is programmed using an external resistor
divider network. The feedback control loop is a
voltage-mode controller with a type III
compensation network. The part uses a low-
noise PWM topology. Up to 3A of continuous
output current can be drawn from this converter.
The 5MHz operating frequency enables the use
of small-size input and output capacitors, and a
wide controller bandwidth.
The power supply has the following protection
features:
• Programmable over-current protection (to
protect the IC from excessive load current)
• Thermal shutdown with hysteresis.
• Over-voltage protection
• Under-voltage lockout circuit to disable the
converter output when the input voltage is
less than approximately 2.2V
Additional features include:
• Soft-start circuit, limiting the in-rush
current when the converter is powered up.
Power good circuit indicating whether the output
voltage is within 90% and the programmed OVP
trip-point percentage of the programmed voltage.
Device Programming Options
The EN5336QI output voltage is programmed
using a simple resistor divider network. Figure 4
shows the resistor divider configuration.
The EN5336QI output voltage and over voltage
thresholds are determined by the voltages
presented at the XFB and XOV pins respectively.
These voltages are set by way of resistor dividers
between VOUT and AGND with the midpoint going
to XFB and XOV.
It is recommended that Rb1 and Rb2 resistor
values be ~2kΩ. Use the following equation to
set the resistor Ra1 for the desired output
voltage:
VRbVVout
Ra 75.0 1*)75.0(
1
−
=
If over-voltage protection is desired, use the
following equation to set the resistor Ra2 for the
desired OVP trip-point:
VRbVOVPtrip
Ra 90.0 2*)90.0(
2
−
=
By design, if both resistor dividers are the same,
the OV trip-point will be 20% above the nominal
output voltage.
XFB
CSS
VOUT
POK
PGNDAGND
SS
PVIN
AVIN
XOV
VOUT
VIN
22µF
47µF
Ra1
Ra2
Rb1
Rb2
Figure 4. VOUT and OVP resistor divider networks.
NOTE: if no OVP divider is present, there will
be no over-voltage protection and POK will
remain “high” as long as VOUT remains above
90% of the nominal VOUT setting.
Input Capacitor Selection
The EN5336QI requires between 10uF and 20uF
of input capacitance. Low-cost, low-ESR ceramic
capacitors should be used as input capacitors for
this converter. The dielectric must be X5R or
X7R rated. In some applications, lower value
capacitors are needed in parallel with the larger,
capacitors in order to provide high frequency
decoupling. It is recommended to use 10V rated
1210 MLCC capacitors.
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Table 2. Recommended input capacitors.
Description MFG P/N
22uF, 10V,
X7R, 1210 Murata GRM32ER71A226KE20L
Taiyo Yuden LMK325BJ226KM-T
47uF, 10V,
X5R, 1210 Murata GRM32ER71A476KE20L
Taiyo Yuden LMK325BJ476KM-T
Output Capacitor Selection
The EN5336QI has been optimized for use with
approximately 47µF of output capacitance. Low
ESR ceramic capacitors are required with X5R or
X7R rated dielectric formulation. Y5V or
equivalent dielectric formulations must not be
used as these loose capacitance with frequency,
temperature and bias voltage.
Output ripple voltage is determined by the
aggregate output capacitor impedance. Output
impedance, denoted as Z, is comprised of
effective series resistance, ESR, and effective
series inductance, ESL:
Z = ESR + ESL.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
nTotal ZZZZ 1
...
111
21
+++=
Typical ripple versus capacitance is given below:
Output Capacitor
Configuration
Typical Output Ripple (mVp-p)
(as measured on EN5336QI
Evaluation Board)
1 x 47uF 20
5 x 10 uF 10
Table 3. Recommended output capacitors.
Description MFG P/N
10uF, 6.3V,
X7R, 1206 Murata GRM319R60J106KE19D
Taiyo Yuden LMK316BJ106KD-T
22uF, 6.3V,
X5R, 1206 Murata GRM31CR60J226KE19L
Taiyo Yuden LMK316BJ226KL-T
47uF, 6.3V,
X5R, 1206 Murata GRM31CR71A476ME19L
Taiyo Yuden LMK316BJ476KL-T
Enable Operation
The ENABLE pin provides a means to shut down
the device, or enable normal operation. A logic
low will disable the converter and cause it to shut
down. A logic high will enable the converter into
normal operation. When the ENABLE pin is
asserted high, the device will undergo a normal
soft start.
Soft-Start Operation
Soft start is a method to reduce in-rush current
when the device is enabled. The output voltage
is ramped up slowly upon start-up. The output
rise time is controlled by choice of a soft-start
capacitor, which is placed between the SS pin
(pin 37) and the AGND pin (pin 29).
Rise Time: TR = Css* 80KΩ
During start-up of the converter, the reference
voltage to the error amplifier is gradually
increased to its final level by an internal current
source of typically 10uA. Typical soft-start rise
time is 1mS to 3mS. Typical SS capacitor values
are in the range of 15nF to 30 nF.
POK Operation
The POK signal is an open drain signal from the
converter indicating the output voltage is within
the specified range. The POK signal will be a
logic high when the output voltage is above 90%
of VOUT and below the user programmed OVP
trip-point. If the output voltage goes outside of
this range, the POK signal will be a logic low until
the output voltage has returned to within this
range. In the event of an over-voltage condition
the POK signal will go low and will remain in this
condition until the output voltage has dropped to
95% of the programmed output voltage before
returning to the high state.
NOTE: If no over voltage protection is used, POK
will remain “high” as long as VOUT remains above
90% of the nominal VOUT setting.
Rev 1.0 November 2006 EN5336QI
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Over-Current Protection
The current limit function is achieved by sensing
the current flowing through the sense P-
MOSFET. When the sensed current exceeds the
current limit, both NFET and PFET switches are
turned off. If the over-current condition is
removed, the over-current protection circuit will
enable the PWM operation. If the over-current
condition persists, the soft start capacitor will
eventually discharge and cause the converter to
go through a full soft-start cycle. This circuit is
designed to provide high noise immunity.
It is possible to adjust the over-current set point
by connecting a resistor between ROCP (pin 27)
and GND (increase the trip point) or PVIN
(decrease the trip point). The nominal over
current trip point is set to 4.5A. The voltage at the
ROCP pin is designed to be 0.8V.
In some cases, such as the start-up of FPGA
devices, it is desirable to blank the over-current
protection feature. In order to disable over-
current protection, the ROCP pin should be tied
to PVIN.
Over-Voltage Prote ction
When the output voltage exceeds 120% of the
programmed output voltage, the PWM operation
stops, the lower N-MOSFET is turned on and the
POK signal goes low. When the output voltage
drops below 95% of the programmed output
voltage, normal PWM operation resumes and
POK returns to its high state.
Thermal Overload Protection
Thermal shutdown will disable operation once
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approx 25ºC, the converter will re-start with a
normal soft-start.
Input Under-voltage Lock-out
Circuitry is provided to ensure that when the
input voltage is below the specified voltage
range, the converter will not start-up. Circuits for
hysteresis, input de-glitch and output leading
edge blanking are included to ensure high noise
immunity and prevent false tripping.
Compensation
The EN5336QI is internally compensated
through the use of a type 3 compensation
network and is optimized for use with about 47µF
of output capacitance and will provide excellent
loop bandwidth and transient performance for
most applications. (See the section on Capacitor
Selection for details on recommended capacitor
types.) Voltage mode operation provides high
noise immunity at light load.
In some cases modifications to the compensation
may be required. For more information, contact
Enpirion Applications Engineering support.
Design Considerations for Lead-Frame Based M odules
Exposed Metal on Bottom Of Pac ka ge
Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance,
and in overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the
lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached.
This results in several small pads being exposed on the bottom of the package.
Rev 1.0 November 2006 EN5336QI
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Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to
the PC board. The PCB top layer under the EN5336QI should be clear of any metal except for the
large thermal pad. The “grayed-out” area in Figure 4 represents the area that should be clear of any
metal (traces, vias, or planes), on the top layer of the PCB.
Figure 4. Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or
electrically connected to the PWB.
Rev 1.0 November 2006 EN5336QI
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Figure 5. Recommended solder mask opening for PWB.
Rev 1.0 November 2006 EN5336QI
Package Dimensions
Figure 6. EN5336QI Package dimensions.
Contact Information
Enpirion, Inc.
685 Route 202/206
Suite 305
Bridgewater, NJ 08807
Phone: 908-575-7550
Fax: 908-575-0775
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is
believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may
result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment
used in hazardous environment without the express written authority from Enpirion.
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