M41T00M - STMicroelectronics

1/15May 2000

M41T00

Serial Access TI MEKEEPER®

■2.0V to 5.5V SUPPLY VOLTAGE

■COUNTERS for SECONDS, MINUTES,

HOU RS , DA Y, DATE, MONTH, YEAR S and

CENTURY

■YEAR 2000 COMPLIA NT

■SOFTWARE CLOCK CALIBRATION

■AUTOMATIC SWITCH-OVER and DESELECT

CIRCUITRY

■I2C BU S COMP ATIBLE

■ULTRA-LOW BATTER Y SUPPL Y C U RRE NT

of 1µA

■LOW OPERATING CURRENT of 300µA

■OPER ATI NG TEM P ERAT URE of –40 to 85°C

■AUTOMATIC LEAP YEAR COMPENSATION

■SPECIAL SOFTWARE PROGRAMMABLE

OUTPUT

DESCRIPTION

Th e M41T00 TIMEKEEPER® RAM is a low power

Serial TIMEKEEPER wi th a built- in 3 2 .768kHz os-

cillator (external crystal controlled). Eight bytes of

the RAM are u sed for the clock/c alendar function

and are configured i n binary coded decimal (BCD)

format. Addresses and data are transferred serial-

ly via a two-line bi-direct ional bus. The built-in ad-

dress register is incremented automatically after

each write or re ad data byte.

Figure 1. Logic Diagram

AI00530

OSCI

VCC

M41T00

VSS

SCL

OSCO

SDA

FT/OUT

VBAT

SO8 (M)

150mil Width

Table 1. Signal Names

OSCI Oscillator Input

OCSO Oscillator Output

FT/OUT Frequency Test / Output Driver

(Open Drain)

SDA Serial Data Address Input / Output

SCL Serial Clock

VBAT Batter y Supp ly Voltage

VCC Supply Voltage

VSS Ground

M41T00

2/15

Figure 2. SOIC Connections

SDAVSS SCL

FT/OUTOSCO

OSCI VCC

VBAT

AI00531

M41T00

Table 2. Absolute Maximum Ratings

No te : St ress es g reate r th an those l i sted under "Absolute Maximum Rat ing s" may cause p erm anent damage t o t he devic e. T hi s is a stress

rating only and f uncti onal oper ation of t he dev i ce at the se or any other cond i tions abov e t hose i ndi cated in th e oper ational section o f

this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.

CAUTION: Nega tive unde rshoo ts bel ow –0. 3V are not al l owed on any pi n whil e i n th e Batter y Back- up m ode.

Symbol Parameter Value Unit

TAAmbient Operating Temperature –40 to 85 °C

TSTG Storage Temperature (VCC Off, Oscillator Off) –55 to 125 °C

VIO Input or Output Voltages –0.3 to 7 V

VCC Supply Voltage –0.3 to 7 V

IOOutput Current 20 mA

PDPower Dissipation 0.25 W

The M41T00 clock has a built-in power sense cir-

cuit which detects power failures and automatical-

ly switches to the battery supply during power

failures. The energy needed to sustain the RAM

and clock oper ati ons can be supplied from a small

lithiu m coin cel l.

Typical data retention time is in excess of 5years

with a 50mA/h 3V lithium cell. The M41T00 is sup-

plied in 8 lead Plastic Small Outline package.

OPERATION

The M41T 00 clock operates as a sl ave device on

the serial bus. Access is obtained by implementing

a start condition f ollowe d by the correc t slave ad-

dress (D0h). The 8 bytes contained in the device

can then be accessed sequentially in the following

order:

1. Sec onds R egister

2. Minutes Register

3. Century/Hours Register

4. Day Register

5. Date Register

6. Month Register

7. Years Register

8. Control Register

The M41T00 clock continually monitors VCC for an

out of tolerance condition. Should VCC fall below

VSO, the device termina tes an ac ces s in progress

and resets the device address counter. Inputs to

the device will not be recognized at this time to

prevent erroneous data from being written to the

device from an out of tolerance system. When VCC

falls below VSO, the device automatically switches

over to the ba tt ery a nd powers dow n into an ultra

low current mode of operation to conserve batte ry

life. Upon power-up, the device switches from bat-

ter y to VCC at VSO and recognizes inputs.

3/15

M41T00

Table 3. Register Map

Note: 1. W hen CEB is set to ’1’, CB will toggle from ’0’ to ’1 ’ or from ’1’ to ’ 0’ at the turn of the century (de pendent upon the initial value set).

When CEB is set to ’0’, CB will not toggle.

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

0 ST 10 Seconds Seconds Seconds 00-59

1 X 10 Minutes Minutes Minutes 00-59

2CEB (1) CB 10 Hours Hours Century/Hour 0-1/00-23

3 XXXXX Day Day 01-07

4 X X 10 Date Date Date 01 -31

5 X X X 10 M. Month Month 01-12

6 10 Years Years Year 00-99

7 OUT FT S Calibration Control

Figu re 3. Blo ck D ia gra m

AI00603

SECONDS

OSCILLATOR

32.768 kHz

VOLTAGE

SENSE and

SWITCH

CIRCUITRY

SERIAL

BUS

INTERFACE

DIVIDER

CONTROL

LOGIC

ADDRESS

MINUTES

CENTURY/HOURS

DAY

DATE

MONTH

YEAR

CONTROL

OSCI

OSCO

FT/OUT

VCC

VSS

VBAT

SCL

SDA

1 Hz

Key s: S = SIGN Bit

FT = FREQUENCY TEST Bit

ST = STOP Bit

OUT = Output level

X = Don’ t care

CEB = Cent ury Enable Bit

CB = Cent ury Bi t

M41T00

4/15

Table 5. Capacitance (1, 2)

(TA = 25 °C, f = 1 MHz)

No te : 1. Effectiv e capa citan ce measure d wi th po wer supp l y at 5V.

2. Sampled only, not 100% tested.

3. Outputs des el ected.

Symbol Parameter Min Max Unit

CIN Input Capacitance (SCL) 7 pF

COUT (3) Output Capacitance (SDA, FT/OUT) 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 250 1000 ns

Figure 4. AC Testing Load Circuit

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Table 4. AC M easu remen t Conditions

Note that Output Hi-Z is defined as the point where data is no longer

driven.

Input Rise and Fall Times ≤ 5ns

Input Pulse Voltages 0.2VCC to 0.8VCC

Input and Output Timing Ref.

Voltages 0.3VCC to 0.7VCC

2-WIRE BUS C HARACTERISTICS

This bus is intended for communication between

different ICs. It consists of tw o line s: one bi-direc-

tional fo r dat a signals (SDA) and one for clock sig-

nals (SCL). Both the SDA and the SCL lines must

be connected to a positive supply voltage via a

pull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the bus

is not busy.

– During dat a transfer, the data li ne must rema in

stable whenever the clock line is High. Changes

in the data line while the clock line is High will be

interpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer. A change in the state of the

data line, from High to Low, while the clock is High,

defines the START condi tion.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition .

Data valid. The state of the data line represents

valid data when after a start condition, the data line

is stable for the duration of th e High period o f the

clock signal. The data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condition

and terminated with a stop condition. The num ber

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each rec eiver acknowl-

edges with a nin th bit.

By definition, a device that gives out a message is

called "transmitt er", the rec eiving device that gets

the message is called "receiver". The device that

controls the message is called "master". The de-

vices that are controlled by the master are called

"slaves".

5/15

M41T00

Table 6. DC Characteristics

(TA = –40 to 85°C; VCC = 2.0V to 5.5V)

No te : 1. STMicro el ectronics recomm ends t he RAYOVAC BR12 25 or BR1632 (or eq ui valent) as the ba ttery suppl y.

Table 7. Power Down/Up Trip Points DC Characteristics (1)

(TA = –40 to 85°C)

Note: 1. All voltages referenced to VSS.

2. Swit ch-ov er and de selec t point .

Table 8. Crystal Electrical Characteristics

(Externally Supplied)

Note: Load capacitors ar e inte grated within the M41T 00. Circuit board layout con sidera tions for t he 32.7 68kHz c rysta l of minim um trace

le ngths and isol atio n from RF generati ng signals should be taken into acc ount .

STM i croe l ectro nics recomm ends the KDS DT -38 Tuning Fork Type quart z c rystal f or i n dus tr i al temperature opera tions .

KDS can be contacted at 91 3-49 1-6825 or http:// www . kdsj. co.jp for further in formatio n on this crystal type.

Symbol Parameter Test Condition Min Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current Switch Frequency = 100kHz 300 µA

ICC2 Supply Current (Standby) SCL, SDA = VCC – 0.3V 70 µA

VIL Input Low Voltage –0.3 0.3 VCC V

VIH Input High Voltage 0.7 VCC VCC + 0.8 V

VOL Output Low Voltage IOL = 3mA 0.4 V

VBAT(1) Battery Supply Voltage 2 3 3.5 V

IBAT Battery Supply Current TA = 25°C, VCC = 0V,

Oscillator ON, VBAT = 3V 0.8 1 µA

Symbol Parameter Min Typ Max Unit

VSO (2) Battery Back-up Switchover Voltage VBAT – 0.70 VBAT – 0.50 VBAT – 0.30 V

Symbol Parameter Min Typ Max Unit

fOResonant Frequency 32.768 kHz

RSSeries Resis tance 35 kΩ

CLLoad Capacitance 12.5 pF

M41T00

6/15

Table 9. Power Down/Up AC Chara cteri stics (1)

(TA = –40 to 85°C)

Note: 1. VCC f al l tim e sho ul d not e xc eed 5mV/µs.

Symbol Parameter Min Max Unit

tPD SCL and SDA at VIH before Power Down 0ns

REC SCL and SDA at VIH after Power Up 10 µs

Acknowledge. E ac h byte of eight bits is followed

by one acknowledge bit. This acknowledge bit is a

low level pu t on the bus b y the receiver, whereas

the master generates an extra acknowledge relat-

ed clock pulse.

A slave receiver which is addressed is obliged to

generate an acknowledge after the reception of

each byte. Also, a master receiver must generate

an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times must

be taken into account. A master receiver must sig-

nal an end-of-d ata to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. In this case, the

transmitter must leave the data line High to enable

the master to generate the STOP condition.

Figure 5. Power Down/Up Mode AC Waveforms

AI00596

VCC

tREC

tPD

VSO

SDA

SCL DON'T CARE

7/15

M41T00

Table 10. AC Characteristics

(TA = –40 to 85°C; VCC = 2.0V to 5.5V)

Note: 1. Transmitter must internally provide a h old time to b ridge the undefine d region (300ns max.) of the falling edge of SCL.

Symbol Parameter Min Max Unit

fSCL SCL Clock Frequency 0 100 kHz

tLOW Clock Low Period 4.7 µs

tHIGH Clock High Period 4 µs

tRSDA and SCL Rise Time 1 µs

tFSDA and SCL Fall Time 300 ns

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 4µs

SU:STA START Condition Setup Time

(only relevant for a repeated start condition) 4.7 µs

tSU:DAT Data Setup Time 250 ns

tHD:DAT (1) Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 4.7 µs

tBUF Time the bus must be free before a new transmission can start 4.7 µs

WRITE MODE

In this mode the master transmitter transmits to

the M41T00 slave receiver. Bus protocol is shown

in Figure 10. Following the START condition and

slave address, a logic ’0’ (R/W = 0) is placed on the

bus and indicates to the addressed device that

word addres s A n will foll ow and is t o be writt en t o

the on -chi p address pointer. Th e data word to be

written t o the memory is strobed in next and the in-

ternal address pointer is incremented to the next

memory location within the RAM on the reception

of an acknowledge clock. The M41T00 slave re-

ceiver will send an acknowledge clock to the mas-

ter transmitter after it has received the slave

address and again after it has received the word

address and each data byte (see Figure 9) .

READ MODE

In this mode, the mas ter reads the M41T 00 slave

after setting the slave address (see Figure 11).

Following the write mode control bit (R/W = 0) and

the acknowledge bi t, the word address An is writ-

ten to the on-chip address pointer. Next the

START condition and slave address are repeated,

followed by the READ mode control bit (R/W =1).

At this point, the master transmitter becomes the

master receiver. The data byte which was ad-

dressed will be transmitted and the master receiv-

er will send an acknowledge bit to the slave

transmitter. The address pointer is only increment-

ed on reception of an acknowledge bit. The

M41 T00 slave transmitter will now place the data

byte at address An+1 on the bus. The master re-

ceiver reads and ackno wledge s the n ew byte and

the address pointer is incremented to An+2.

This cycle of reading consecutive addresses will

continue until the master receiver sends a STOP

condition to the slave transmitter.

An alternate READ mode may also be implement-

ed, whereby the master reads the M41T00 slave

without first w ri tin g to the (vol atile) address point-

er. The first address that is read is the last one

stored in the p ointer, see Figure12.

M41T00

8/15

Figure 6. Serial Bus Data Transfer Sequen ce

Figure 7. Acknowled gment Sequen ce

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCLK FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

CLOCK OPERATION

The eight byte clock register (see Table 3) is used

to both set t he clock and to read the date and time

from the clock, in a binary coded decimal format.

Seconds, Minutes, and Hours are contained within

the first three registers. Bits D6 and D7 of clock

ENABLE Bit (CEB) and the CENTURY Bit (CB).

Setting CEB to a ’ 1’ will cause CB to toggle, either

from ’0’ to ’1’ or from ’1’ to ’0’ at the turn of t he cen-

tury (depending upon its initial state). If CEB is set

to a ’0’, CB will not toggle. Bits D0 through D2 of

4, 5 and 6 contain the Date (day of month), Month

and Years. The f inal register is the C ontrol Regis-

ter (this is described in the Clock Calibration sec-

tion). Bit D7 of register 0 contains the STOP Bit

(ST). Setting this bit to a ’ 1’ will cause the oscillator

to stop. If the device is expected to spend a signif-

icant amount of time on the shelf, the oscillator

may be stopped to reduce current drain. When re-

set to a ’ 0’ the oscillator restarts within one second.

The seven Clock Registers may be read one b yte

at a time, or in a sequential block. The Control

dependently. Pro vision has been made to assure

that a clock update does not occur while any of the

seven clock addresses are being read. If a clock

address is being read, an update of the clock reg-

isters will be delayed by 250ms to allow the read

to be completed before the update occurs. This

will pr ev e nt a tran s it ion of dat a d ur ing t he re ad .

Note: This 250ms delay affects only the clock reg-

ister update and does not alter the actual clock

time.

9/15

M41T00

CLOCK CALIBRATION

The M41T00 is driven by a quartz controlled oscil-

lator with a nominal frequency of 32,768Hz. The

devices are tested not to exceed 35ppm (parts per

million) oscillator frequency error at 25°C, which

equates to about ±1.53 minutes per month. With

the calibration bits properly set, the accuracy of

each M41T 00 improves to better than +2/–1 ppm

at 25°C.

The oscillation rate of any crystal changes with

temperature (see Figure 14). Most clock chips

compensate for crystal frequency and tempera-

ture shift error with cumbersome trim capacitors.

The M41T00 design, however, employs periodic

counter correction. The calibra tion circuit adds or

subtracts counts from the oscillator divider circuit

at th e divide by 256 stage, as shown in Fig ure 13.

The number of ti mes pulses are blanked (subtract-

ed, negative calibration) or split (added, positive

calibration) depends upon the value loaded into

the five bit Calibration byte found in the Control

tracting counts slows the clock down.

The Calibration byte occupies the five lower order

bits (D4-D0) in the Control register (Addr 7). This

byte can be s et t o repres ent any va lue be twee n 0

and 31 in binary f orm . Bit D5 is a Sign bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64minute

cycle. The first 6 2 m inutes in the cycle m ay , onc e

per minute, h ave one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minutes in the 6 4 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, e ach calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step i n t he cal ibrat ion registe r. Ass um ing that

the oscillator is in fact running at exactly 32,768Hz,

each of the 31 increments in the Calibration b yte

would represent +10.7 or –5.35 seconds per

month which corres ponds to a total range of +5. 5

or –2.75 minutes per month.

Figure 8. Bus Timing Requirements Sequence

Note: P = STOP and S = START

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

Figure 9. Slave Address Location

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

M41T00

10/15

Figu re 10 . Wri te Mo de S equence

Figure 11. Read Mode Sequence

Figure 12. Alt ernate Read Mode Sequence

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (n)

SLAVE

ADDRESS

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (n)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

11/15

M41T00

For example , a reading o f 512 .01024Hz woul d in-

dicate a +20ppm oscillator frequency error, requir-

ing a –10(XX001010) to be loaded into the

Calibration Byte for correction. Note that setting or

changing the Calibration Byte does n ot affect the

Frequenc y test output frequency.

OUTPUT DRIVER PIN

When the FT bit is not set, the FT/OUT pin be-

comes an output driver that reflects the contents of

D7 of the control register. In other words, when D6

of location 7 is a zero and D7 of location 7 is a zero

and then the FT/OUT pin will be driven low.

Note: The FT/OUT pin is open drain which re-

quires an external pull-up resistor.

POWER-ON DEFAULTS

Upon initial application of power to the device, the

FT bit will be set to a '0' and the OUT bit will be set

to a '1'. All other Register bits will initially power-on

in a random state.

Two methods are available for ascertaining how

much calibration a given M41T00 may require.

The first involves simply setting the clock, letting it

run for a month and comparing it to a known accu-

rate reference (like WWV broadcasts). While that

may seem crude, it allows the designer to give the

end user the ability to calibrate his clock as his en-

vironment may require, even after the final product

is packaged in a non-user serviceable enclosure.

All the designer has to do is provide a simple utility

that acc essed the Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of

some test equipment. When the Frequency Test

(FT) bit, the seventh-most significant bit in the

Control Register, is set to a '1', and the oscillator is

running at 32,768Hz, the FT/OUT pin of the device

will toggle at 512Hz. Any deviation from 512Hz in-

dicates the degree and direction of oscillator fre-

quency shift at the test temperature.

Figu re 13. Cl oc k C al ib rat i on

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M41T00

12/15

Figure 14. Crysta l Accuracy Acro ss Temp eratur e

AI00999

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= -0.038 (T - T0)2 ± 10%

Fppm

T0 = 25 °C

13/15

M41T00

Table 11. Ordering Information Scheme

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

Example: M41T00 M 6 TR

Device Type

M41T

Package

M = SO8 150mil Width

Temperature Range

6 = –40 to 85°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

Table 12. Revision History

Date Revision Details

March 1999 First Issue

05/15/00 AC Characteristic conditions changed (Table 10)

M41T00

14/15

Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

Figure 15. SO 8 - 8 le ad Pla stic Small Outli ne, 150 mils b o dy width, Package Outline

Drawing is not to scale.

SO-a

LA1 α

h x 45˚

15/15

M41T00

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