Surface Mount RF PIN Switch
and Limiter Diodes
Technical Data
Features
Diodes Optimized for:
Low Current Switching
Low Distortion Attenuating
Power Limiting/Circuit
Protection
Surface Mount SOT-23 and
SOT-323 Packages
Single and Dual Versions
Tape and Reel Options
Available
Low Failure in Time (FIT)
Rate[1]
Lead-free Option Available
Note:
1. For more information see the
Surface Mount PIN Reliability Data
Sheet.
HSMP-382x Series and
HSMP-482x Series
Package Lead Code
Identification, SOT-323
(Top View)
Description/Applications
The HSMP-382x series is
optimized for switching applica-
tions where ultra-low resistance is
required. The HSMP-482x diode is
ideal for limiting and low induc-
tance switching applications up to
1.5 GHz.
A SPICE model is not available
for PIN diodes as SPICE does not
provide for a key PIN diode
characteristic, carrier lifetime.
Package Lead Code
Identification, SOT-23
(Top View)
COMMON
CATHODE
#4
COMMON
ANODE
#3
SERIES
#2
SINGLE
#0
DUAL ANODE
HSMP-4820
DUAL ANODE
HSMP-482B
Absolute Maximum Ratings[1] TC = +25°C
Symbol Parameter Unit SOT-23 SOT-323
IfForward Current (1 µs Pulse) Amp 1 1
PIV Peak Inverse Voltage V 50 50
TjJunction Temperature °C 150 150
Tstg Storage Temperature °C -65 to 150 -65 to 150
θjc Thermal Resistance[2] °C/W 500 150
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to
the device.
2. TC = +25°C, where TC is defined to be the temperature at the package pins where
contact is made to the circuit board.
2
Typical Parameters at T
C
= 25°C
Part Number Series Resistance Carrier Lifetime Reverse Recovery Time Total Capacitance
HSMP- RS ()τ (ns) Trr (ns) CT (pF)
382x 1.5 70 7 0.60 @ 20 V
Test Conditions f = 100 MHz IF = 10 mA VR = 10 V
IF = 10 mA IF = 20 mA
90% Recovery
Electrical Specifications T
C
= 25°C
Package Minimum Maximum Maximum
Part Number Marking Lead Breakdown Series Resistance Total Capacitance
HSMP- Code[1] Code Configuration Voltage VBR (V) RS ()C
T (pF)
3820 F0 0 Single 50 0.6 0.8
3822 F2 2 Series
3823 F3 3 Common Anode
3824 F4 4 Common Cathode
Test Conditions VR = VBR f = 100 MHz f = 1 MHz
Measure IF = 10 mA VR = 20 V
IR 10 µA
High Frequency (Low Inductance, 500 MHz 3 GHz) PIN Diodes
Minimum Maximum Typical Maximum Typical
Part Package Breakdown Series Total Total Total
Number Marking Lead Voltage Resistance Capacitance Capacitance Inductance
HSMP- Code Code Configuration VBR (V) RS ()C
T (pF) CT (pF) LT (nH)
4820 FA A Dual Anode 50 0.6 0.75 1.0 1.0
482B FA A Dual Anode
Test Conditions VR = VBR IF = 10 mA f = 1 MHz f = 1 MHz f = 500 MHz
Measure VR = 20 V VR = 0 V 3 GHz
IR 10 µA
Note:
1. Package marking code is white, except for HSMP-482B, which is laser marked.
3
Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode
Figure 3. RF Resistance at 25°C vs.
Forward Bias Current.
100
10
1
0.1
RF RESISTANCE (OHMS)
I
F
– FORWARD BIAS CURRENT (mA)
0.01 0.1 1 10 100
1.4
1.2
1.0
0.8
0.6 0 1020304050
V
R
– REVERSE VOLTAGE (V)
CAPACITANCE (pF)
Figure 4. Capacitance vs. Reverse
Voltage.
120
115
110
105
100
95
90
85
11030
I
F
– FORWARD BIAS CURRENT (mA)
Figure 5. 2nd Harmonic Input
Intercept Point vs. Forward Bias
Current.
INPUT INTERCEPT POINT (dBm)
Diode Mounted as a
Series Attenuator in a
50 Ohm Microstrip and
Tested at 123 MHz
FORWARD CURRENT (mA)
Figure 2. Reverse Recovery Time vs.
Forward Current for Various Reverse
Voltages.
T
rr
– REVERSE RECOVERY TIME (ns)
1
10
100
10 20 30
V
R
= 2V
V
R
= 5V
V
R
= 10V
100
10
1
0.1
0.01 0 0.2 0.4 0.6 0.8 1.0 1.2
I
F
– FORWARD CURRENT (mA)
V
F
– FORWARD VOLTAGE (mA)
Figure 1. Forward Current vs.
Forward Voltage.
125°C25°C–50°C
CW POWER IN (dBm)
Figure 6. Large Signal Transfer Curve
of the HSMP-482x Limiter.
CW POWER OUT (dBm)
0
30
25
20
15
10
5
0
4010
520 25 30 3515
Measured with external
bias return
1.0 GHz
1.5 GHz
Typical Applications for Multiple Diode Products
RF COMMON
RF 1
BIAS 1
RF 2
BIAS 2
Figure 7. Simple SPDT Switch, Using Only Positive
Current.
Figure 8. High Isolation SPDT Switch, Dual Bias.
RF COMMON
BIAS BIAS
RF 2
RF 1
4
Typical Applications for Multiple Diode Products, continued
BIAS
Figure 9. Switch Using Both Positive and Negative
Bias Current.
Figure 10. Very High Isolation SPDT Switch,
Dual Bias.
Figure 11. High Isolation SPST Switch (Repeat Cells
as Required.
Figure 12. Power Limiter Using HSMP-3822 Diode
Pair. See Application Note 1050 for details.
RF COMMON
RF 1 RF 2
BIAS
RF COMMON
RF 2
RF 1
BIAS
5
Typical Applications for
HSMP-482x Low
Inductance Series
Microstrip Series Connection
for HSMP-482x Series
In order to take full advantage of
the low inductance of the
HSMP-482x series when using
them in series applications, both
lead 1 and lead 2 should be
connected together, as shown in
Figure 14.
12
3
HSMP-482x
Figure 13. Internal Connections.
Figure 14. Circuit Layout.
Microstrip Shunt Connections
for HSMP-482x Series
In Figure 15, the center conductor
of the microstrip line is inter-
rupted and leads 1 and 2 of the
HSMP-482x diode are placed
across the resulting gap. This
forces the 0.5 nH lead inductance
of leads 1 and 2 to appear as part
of a low pass filter, reducing the
shunt parasitic inductance and
increasing the maximum available
attenuation. The 0.3 nH of shunt
inductance external to the diode
is created by the via holes, and is
a good estimate for 0.032" thick
material.
50 OHM MICROSTRIP LINES
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
Figure 15. Circuit Layout,
HSMP-482x Limiter.
0.3 nH
0.3 nH
0.8 pF
1.5 nH 1.5 nH
Figure 16. Equivalent Circuit.
Co-Planar Waveguide Shunt
Connection for HSMP-482x
Series
Co-Planar waveguide, with
ground on the top side of the
printed circuit board, is shown in
Figure 17. Since it eliminates the
need for via holes to ground, it
offers lower shunt parasitic
inductance and higher maximum
attenuation when compared to a
microstrip circuit. See AN1050 for
details.
Co-Planar Waveguide
Groundplane
Center Conductor
Groundplane
Figure 17. Circuit Layout.
0.8 pF
0.75 nH
Figure 18. Equivalent Circuit.
6
Assembly Information
SOT-323 PCB Footprint
A recommended PCB pad layout
for the miniature SOT-323 (SC-70)
package is shown in Figure 19
(dimensions are in inches). This
layout provides ample allowance
for package placement by auto-
mated assembly equipment
without adding parasitics that
could impair the performance.
0.026
0.035
0.07
0.016
Figure 19. PCB Pad Layout
(dimensions in inches).
SOT-23 PCB Footprint
0.037
0.95
0.037
0.95
0.079
2.0
0.031
0.8
DIMENSIONS IN inches
mm
0.035
0.9
Figure 20. PCB Pad Layout.
TIME (seconds)
TMAX
TEMPERATURE (°C)
0
0
50
100
150
200
250
60
Preheat
Zone Cool Down
Zone
Reflow
Zone
120 180 240 300
Figure 21. Surface Mount Assembly Profile.
SMT Assembly
Reliable assembly of surface
mount components is a complex
process that involves many
material, process, and equipment
factors, including: method of
heating (e.g., IR or vapor phase
reflow, wave soldering, etc.)
circuit board material, conductor
thickness and pattern, type of
solder alloy, and the thermal
conductivity and thermal mass of
components. Components with a
low mass, such as the SOT-323/-23
package, will reach solder reflow
temperatures faster than those
with a greater mass.
Agilents diodes have been
qualified to the time-temperature
profile shown in Figure 21. This
profile is representative of an IR
reflow type of surface mount
assembly process.
After ramping up from room
temperature, the circuit board
with components attached to it
(held in place with solder paste)
passes through one or more
preheat zones. The preheat zones
increase the temperature of the
board and components to prevent
thermal shock and begin evaporat-
ing solvents from the solder paste.
The reflow zone briefly elevates
the temperature sufficiently to
produce a reflow of the solder.
The rates of change of tempera-
ture for the ramp-up and cool-
down zones are chosen to be low
enough to not cause deformation
of the board or damage to compo-
nents due to thermal shock. The
maximum temperature in the
reflow zone (TMAX) should not
exceed 235°C.
These parameters are typical for a
surface mount assembly process
for Agilent diodes. As a general
guideline, the circuit board and
components should be exposed
only to the minimum tempera-
tures and times necessary to
achieve a uniform reflow of
solder.
7
Package Characteristics
Lead Material ................................... Copper (SOT-323); Alloy 42 (SOT-23)
Lead Finish ............................................................................ Tin-Lead 85-15%
Maximum Soldering Temperature .............................. 260°C for 5 seconds
Minimum Lead Strength .......................................................... 2 pounds pull
Typical Package Inductance .................................................................. 2 nH
Typical Package Capacitance .............................. 0.08 pF (opposite leads)
Ordering Information
Specify part number followed by option. For example:
HSMP - 382x - XXX
Bulk or Tape and Reel Option
Part Number; x = Lead Code
Surface Mount PIN
Option Descriptions
-BLK = Bulk, 100 pcs. per antistatic bag
-TR1 = Tape and Reel, 3000 devices per 7" reel
-TR2 = Tape and Reel, 10,000 devices per 13" reel
Tape and Reeling conforms to Electronic Industries RS-481, Taping of
Surface Mounted Components for Automated Placement.
For lead-free option, the part number will have the character "G" at the
end, eg. -TR2G for a 10K pc lead-free reel.
Package Dimensions
Outline SOT-323 (SC-70) Outline 23 (SOT-23)
2.20 (0.087)
2.00 (0.079)
1.35 (0.053)
1.15 (0.045)
1.30 (0.051)
REF.
0.650 BSC (0.025)
2.20 (0.087)
1.80 (0.071)
0.10 (0.004)
0.00 (0.00)
0.25 (0.010)
0.15 (0.006)
1.00 (0.039)
0.80 (0.031)
0.20 (0.008)
0.10 (0.004)
0.30 (0.012)
0.10 (0.004)
0.30 REF.
10°
0.425 (0.017)
TYP.
DIMENSIONS ARE IN MILLIMETERS
(
INCHES
)
PACKAGE
MARKING
CODE (XX)
X X X
DATE CODE (X)
3
12
SIDE VIEW
TOP VIEW
END VIEW
DIMENSIONS ARE IN MILLIMETERS
(
INCHES
)
1.02 (0.040)
0.89 (0.035)
0.60 (0.024)
0.45 (0.018)
1.40 (0.055)
1.20 (0.047)
2.65 (0.104)
2.10 (0.083)
3.06 (0.120)
2.80 (0.110)
2.04 (0.080)
1.78 (0.070)
1.02 (0.041)
0.85 (0.033)
0.152 (0.006)
0.066 (0.003)
0.10 (0.004)
0.013 (0.0005)
0.69 (0.027)
0.45 (0.018)
0.54 (0.021)
0.37 (0.015)
X X X
PACKAGE
MARKING
CODE (XX)
DATE CODE (X)
8
Tape Dimensions and Product Orientation
For Outline SOT-23
Note: "AB" represents package marking code.
"C" represents date code.
END VIE
W
8 mm
4 mm
TOP VIEW
ABC ABC ABC ABC
Device Orientation
For Outlines SOT-23/323
USER
FEED
DIRECTION
COVER TAPE
CARRIER
TAPE
REEL
9° MAX
A0
P
P0
D
P2
E
F
W
D1
Ko 8° MAX
B0
13.5° MAX
t1
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P
D1
3.15 ± 0.10
2.77 ± 0.10
1.22 ± 0.10
4.00 ± 0.10
1.00 + 0.05
0.124 ± 0.004
0.109 ± 0.004
0.048 ± 0.004
0.157 ± 0.004
0.039 ± 0.002
CAVITY
DIAMETER
PITCH
POSITION
D
P0
E
1.50 + 0.10
4.00 ± 0.10
1.75 ± 0.10
0.059 + 0.004
0.157 ± 0.004
0.069 ± 0.004
PERFORATION
WIDTH
THICKNESS
W
t1
8.00 + 0.30 – 0.10
0.229 ± 0.013
0.315 + 0.012 – 0.004
0.009 ± 0.0005
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
BETWEEN
CENTERLINE
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Data subject to change.
Copyright © 2004 Agilent Technologies, Inc.
Obsoletes 5988-3145EN
March 24, 2004
5989-0483EN
P
P
0
P
2
F
W
C
D
1
D
E
A
0
An
t
1
(CARRIER TAPE THICKNESS) T
t
(COVER TAPE THICKNESS)
An
B
0
K
0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
2.40 ± 0.10
2.40 ± 0.10
1.20 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.094 ± 0.004
0.094 ± 0.004
0.047 ± 0.004
0.157 ± 0.004
0.039 + 0.010
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.55 ± 0.05
4.00 ± 0.10
1.75 ± 0.10
0.061 ± 0.002
0.157 ± 0.004
0.069 ± 0.004
PERFORATION
WIDTH
THICKNESS
W
t
1
8.00 ± 0.30
0.254 ± 0.02
0.315 ± 0.012
0.0100 ± 0.0008
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
FOR SOT-323 (SC70-3 LEAD) An 8°C MAX
FOR SOT-363 (SC70-6 LEAD) 10°C MAX
ANGLE
WIDTH
TAPE THICKNESS
C
T
t
5.4 ± 0.10
0.062 ± 0.001
0.205 ± 0.004
0.0025 ± 0.00004
COVER TAPE
Tape Dimensions and Product Orientation
For Outline SOT-323