M29F800DT55N6E - Numonyx - Product.Network

August 2006 Rev 5 1/53

M29F800DT

M29F800DB

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)

5V Supply Flash Memory

Feature summary

■Supply voltage

–V

CC = 5V ±10% for Program, Erase and

Read

■Access time: 55, 70, 90ns

■Programming time

– 10µs per Byte/Word typical

■19 Memory Blocks

– 1 Boot Block (Top or Bottom location)

– 2 Parameter and 16 Main Blocks

■Program/Erase controller

– Embedded Byte/Word Program algorithms

■Erase Susp end and Resume modes

– Read and Program anot he r Block during

Erase Suspend

■Unlock Bypass Program command

– Faster Production/batch Programming

■Temporary Block Unprot ection mode

■Common Flash Interface

– 64 bit Security Code

■Low power consumption

– Standby and Automatic Standby

■100,000 Program/Erase cycles per Block

■Electronic Signature

– Manufacturer Code: 0020h

– Top Device Code M29F800DT: 22ECh

– Bottom Device Code M29F800DB: 2258 h

TSOP48 (N)

12 x 20mm

SO44 (M)

www.st.com

Contents M29F800DT

2/53

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.0.1 Address Inputs (A0-A18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.0.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.0.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.0.4 Data Input/Output or Address Input (DQ15A-1) . . . . . . . . . . . . . . . . . . . 12

2.0.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.0.6 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.0.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.0.8 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.0.9 Ready/Busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.0.10 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.0.11 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.0.12 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0.6 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.0.7 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.0.8 Block Protection and Blocks Unprotection . . . . . . . . . . . . . . . . . . . . . . . 15

4 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.0.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.0.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.0.3 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.0.4 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.0.5 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.0.6 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.0.7 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.0.8 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

M29F800DT Contents

3/53

4.0.9 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.0.10 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.0.11 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.0.12 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 19

5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.0.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.0.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.0.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.0.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.0.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Appendix A Block address tab le. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.2 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

List of tables M29F800DT

4/53

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 3. Bus operations, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 4. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 5. Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 6. Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 9. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 12. Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13. Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14. Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 15. Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, package mechanical data. . . 36

Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 37

Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 19. Top Boot Block addresses, M29F800D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 20. Bottom Boot Block addresses, M29F800DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 21. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 22. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 23. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 25. Primary Algorithm-specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 26. Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 27. Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 28. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

M29F800DT List of figures

5/53

List of figures

Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Block addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Block addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Data Polling flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7. Data Toggle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 9. AC measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 10. Read Mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 11. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 12. Write AC waveforms, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 13. Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, package outline. . . . . . . . . . . 36

Figure 15. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 37

Figure 16. Programmer Equipment Block Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 17. Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 18. In-System Equipment Block Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 19. In-System Equipment Chip Unprotect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Summary description M29F800DT

6/53

1 Summary description

The M29F800D is a 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read,

erased and r eprogrammed. These operations can be performed using a single low voltage

(5V) supply. On po we r-up the me mory defau lts to its Read mod e where it ca n be read in the

same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to

preserve valid data while old data is erased. Each block can be protected independently to

prevent accident al Program or Erase commands from modifying the memory. Program and

Erase commands are written to the Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the pro cess of programming or erasing the memory by

taking care of all of the special operations that are required to update the memory contents.

The end of a program or erase operation can be detected and any error conditions

identified. The command set required to control the memory is consistent with JEDEC

standards.

The b locks in the me mory are asymmetrically arran ged, see Figure 4: Bloc k addresses (x8),

and Figure 5: Block addresses (x16). The first or last 64 Kbytes have been divided into four

additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start

the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage

and the remaining 32K is a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals contr ol the bus ope ration of the

memory. They allow simple connection to most microprocessors, often without additional

logic.

The memory is offere d in SO44 and TSOP48 (12 x 20mm) packages. The memory is

supplied with all the bits erased (set to ’1’).

M29F800DT Summary description

7/53

Figure 1. Logic diagram

Table 1. Signal names

A0-A18 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or address Input

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

BYTE Byte/Word Organization Select

VCC Supply voltage

VSS Ground

NC Not Connected Internally

AI06148B

A0-A18

DQ0-DQ14

VCC

M29F800DT

M29F800DB

VSS

DQ15A–1

BYTE

Summary description M29F800DT

8/53

Figure 2. SO connections

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A–1

DQ5DQ2

DQ3 VCC

DQ11 DQ4

DQ14

AI06150

M29F800DT

M29F800DB

2322

17DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10 21 DQ12

A17 A8

A18

M29F800DT Summary description

9/53

Figure 3. TSOP connections

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI06149

M29F800DT

M29F800DB

24 25

DQ8

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

Summary description M29F800DT

10/53

Figure 4. Block addresses (x8)

1. Also see Appendix A, Table 19, and Table 20 for a full listing of the Block addresses.

16 KByte

FFFFFh

FC000h

64 KByte

1FFFFh

10000h

64 KByte

0FFFFh

00000h

M29F800DT

Top Boot Block Addresses (x8)

32 KByte

F7FFFh

F0000h

64 KByte

E0000h

EFFFFh

Total of 15

64 KByte Blocks

16 KByte

FFFFFh

F0000h 64 KByte

64 KByte

03FFFh

00000h

M29F800DB

Bottom Boot Block Addresses (x8)

32 KByte

EFFFFh

1FFFFh 64 KByte

E0000h

10000h

Total of 15

64 KByte Block

0FFFFh

08000h

8 KByte

FBFFFh

FA000h

F9FFFh

F8000h

8 KByte

07FFFh

06000h

05FFFh

04000h

M29F800DT Summary description

11/53

Figure 5. Block addresses (x16)

1. Also see Appendix A, Table 19, and Table 20 for a full listing of the Block addresses.

8 KWord

7FFFFh

7E000h

32 KWord

0FFFFh

08000h

32 KWord

07FFFh

00000h

M29F800DT

Top Boot Block Addresses (x16)

16 KWord

7BFFFh

78000h

32 KWord

70000h

77FFFh

Total of 15

32 KWord Blocks

8 KWord

7FFFFh

78000h 32 KWord

32 KWord

01FFFh

00000h

M29F800DB

Bottom Boot Block Addresses (x16)

16 KWord

77FFFh

0FFFFh 32 KWord

70000h

08000h

Total of 15

32 KWord Block

07FFFh

04000h

4 KWord

7DFFFh

7D000h

7CFFFh

7C000h

4 KWord

03FFFh

03000h

02FFFh

02000h

Signal descriptions M29F800DT

12/53

2 Signal descriptions

See Figure 1: Logic diagram, and Table 1: Signal nam es for a brief overview of the signals

connected to this device.

2.0.1 Address Inputs (A0-A18)

The Address Inputs select the cells in the me mory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the Command

Interface of the internal state machine.

2.0.2 Data Inputs/Outputs (DQ0-DQ7)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operat ion. During Bus Write operations t hey r epresent the command s sent to the Command

Interface of the internal state machine.

2.0.3 Data Inputs/Outputs (DQ8-DQ14)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operat ion when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and ar e

high impedance. During Bus Write operations the Command Register doe s not use these

bits. When reading the Status Register these bits should be ignored.

2.0.4 Data Input/Output or Address Input (DQ15A-1)

When BYTE is High, VIH, this pin beha ves as a Data Input/Output pin (as DQ8-DQ14).

When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Lo w will select the

LSB of the Word on the other addresses, DQ15A–1 High will s elect the MSB. Throughout

the text consider references to the Data Inpu t/ Ou tp ut to inclu de this pin whe n BYTE is High

and references to the Address Inputs to include this pin when BYTE is Low except when

stated explicitly otherwise.

2.0.5 Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to

be performed. When Chip Enable is High, VIH, all other pins are ignored.

2.0.6 Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

2.0.7 Write Enable (W)

The Write Enab le , W, controls the Bus Write operation of the memory’s Command Interface.

M29F800DT Signal descriptions

13/53

2.0.8 Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the

memory or to temporarily unprotect all Blocks that have been protected.

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at

least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be

ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last.

See Section 2.0.9: Ready/Busy output (RB), Table 15: Reset/Block Temporary Unprotect

AC characteristics, and Figure 13: Reset/Block Temporary Unprotect AC waveforms for

more details.

Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program

and Erase operations on all blocks will be possible. The transition from VIH to VID must be

slower than t PHPHH.

2.0.9 Ready/Busy output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the device is

perf orming a Progra m or Erase oper ation. During Prog ram or Er ase oper ations Ready/Busy

is Low, VOL. Ready/Busy i s high-impedance during Read mode, Auto Select mode and

Erase Suspend mode.

After a Hardw are Reset, Bus Read and Bus Write oper ations cannot begi n until Ready/Busy

becomes high-impedance. See Table 15: Reset/Block Temporary Unprotect AC

characteristics, and Figure 13: Reset/Block Temporary Unprotect AC wavef orms.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

2.0.10 Byte/Word Organization Select (BYTE)

The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus

modes of the memory. When Byte/W ord Organization Select is Low, VIL, the memory is in 8-

bit mode, when it is High, VIH, the memory is in 16-bit mode.

2.0.11 VCC Supply Voltage

The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout

vo lt age, VLKO. This prevents Bus Write operations from accidentally damaging the data

during pow er up, power down and power surges. If the Program/Erase Contr oller is

progr amming or erasin g during this time then th e operation abo rts and the memory contents

being altered will be invalid.

A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS

Ground pin to decouple the current surges from the power supply. The PCB track widths

must be sufficient to carry the currents required during program and erase operations, ICC3.

2.0.12 VSS Ground

The VSS Ground is the reference for all voltage measurements.

Bus operations M29F800DT

14/53

3 Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus

Write, Output Disable, Standb y a nd Automatic Standb y. See Table 2: Bus operations, BYTE

= VIL, and Table 3: Bus operations, BYTE = VIH for a summary. Typically glitches of less

than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus

operations.

3.0.1 Bus Read

Bus Read operations read from the me mory cells, or specific registers in the Command

Interface. A valid Bus Read operation involves setting the desired addr ess on the Address

Inputs , applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write

Enab le High, VIH. The Data Inputs/Outputs will output the v alue , see Figure 10: Read Mode

AC waveforms, and Table 12: Read AC characteristics for details of when the output

becomes valid.

3.0.2 Bus Write

Bus Write operations write to the Command I nterf ace. A v alid Bus Write operat ion begins b y

setting the desire d address on the Address Inputs. The Address Inputs are latched b y the

Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs

last. The Data Inputs/Outputs are latched by the Comm and Interface on the rising edge of

Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,

durin g the who le Bu s Write operation. See Figure 11: Write AC waveforms, Write Enable

controlled, Figure 12: Write AC waveforms, Chip Enable controlled, Tab le 13: Write AC

characteristics, Write Enable controlled, and Table 14: Write AC characteristics, Chip

Enable controlled, for details of the tim ing requirements.

3.0.3 Output Disable

The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

3.0.4 Standby

When Chip Enable is High, VIH, the memory enters Standby mode and the Data

Inputs/Output s pins are placed in the h igh-impedance state . To reduce the Supply Cu rrent to

the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the

Standby current level see Table 11: DC characteristics.

During program or erase operations the memory will continue to use the Program/Erase

Supply Current, ICC3, for Program or Erase operations until the operation completes.

3.0.5 Automatic Standby

If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or

more the memory enters A utomatic Standb y where the inte rnal Supply Current is reduced to

the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

M29F800DT Bus operations

15/53

3.0.6 Special bus operations

Additional bus operations can be performed to rea d the Electronic Signature and also to apply and

remov e Bloc k Protectio n. These bus op erations are int ended for use b y prog r amming equip ment and are

not usually used in applications. They require VID to be applied to some pins.

3.0.7 Electronic Signature

The memory has two codes , the manufacture r code an d t he device code , t hat can be re ad t o id entif y t he

memory. These codes can be read b y ap plying the signals list ed in Tab le 2: Bus oper ations, BYTE = VIL ,

and Table 3: Bus operations, BYTE = VIH.

3.0.8 Block Protection and Blocks Unprotection

Each block can be separately protected against accidental Program or Erase. Protected blocks can be

unprotected to allow data to be changed.

There are tw o met hods available fo r prote cting and unpr otectin g the blocks , one for use on progr am ming

equipment and the other f or in-system use. Bloc k Protect and Chip Unprotect operations are described in

Appendix C.

Table 2. Bus operations, BYTE = VIL(1)

Operation E G W Address Inputs

DQ15A–1, A0-A18

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL VIH Cell address Hi-Z Data Output

Bus Write VIL VIH VIL Command address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH Hi-Z 20h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,

Others VIL or VIH Hi-Z ECh (M29F800 DT)

58h (M29F800DB)

1. X = VIL or VIH.

Table 3. Bus operations, BYTE = VIH(1)

Operation E G W Address Inputs

A0-A18 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell address Data Output

Bus Write VIL VIH VIL Command address Data Input

Output Disable X VIH VIH XHi-Z

Standby VIH XXX Hi-Z

Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,

Others VIL or VIH

22ECh (M29F8 00DT)

2258h (M29F800DB)

1. X = VIL or VIH.

Command Interface M29F800DT

16/53

4 Command Interface

All Bus Write operations to the memory are interpreted by the Command Interface.

Commands consist of one or more sequential Bus Write operations. Failure to observe a

v alid sequence of Bus Write operations will result in the memory returning to Read mode.

The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whet her the memory is in 16-

bit or 8-bit mode . See either Table 4, or Table 5, depending on t he configur ation that is being

used, for a summary of the co mmands.

4.0.1 Read/Reset command

The Read/Reset command returns the memory to its Read mode where it behaves like a

ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register.

Either one or three Bus Write operations can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, between Bus Write cycles before the start of a

program or erase operation, to return the device to read mode. Once the program or erase

operation has started the Read/Reset command is no longer accepted. The Read/Reset

command will not abort an Erase operation when issued while in Erase Suspend.

4.0.2 Auto Select command

The A uto Sele ct command is used t o read the Ma nuf act urer Code , the Device Code and the

Block Protection Status. Three consecutive Bus Write operations are required to issue the

Auto Select command. Once the Auto Select command is issued the memory remains in

A uto Select mode until a Rea d/Reset command is issued. Read CFI Query and Read/Reset

commands are accepted in Auto Select mode, all other commands are ignored.

F rom the A uto Select mode the Manuf acture r Code can be read using a Bus Read ope ration

with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The

Manufacturer Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read o peration with A0 = VIH and A1 = VIL. The

other address bits may be set to either VIL or VIH.

The Block Protection Status of each block can be read using a Bus Read operation with A0

= VIL, A1 = VIH, and A12-A18 specifying the address of the block. The other address bits

ma y be set to either VIL or VIH. If the addressed b lock is p rotected then 01h is output on

Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

M29F800DT Command Interface

17/53

4.0.3 Program command

The Prog ram command can be used to prog ram a v alue to one address in the memory arra y

at a time. The command requir es f our Bus Write operat ions, the final write oper ation latches

the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data

remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to

issue any command to abort or pause the operation. Typi cal program times are given in

Tab le 6: Program, Er ase times and Pr ogram, Er ase Endurance cycles. Bus Read oper ations

during the program operation will output the Status Register on the Data Inputs/Outputs.

See Section 5: Status Register, for more details.

After the progr am operation has completed the memory will return to the Read mode , unless

an error has occurred. When an error occurs the memory will continue to outpu t the Status

Read mode.

Note that the Prog r am command ca nnot cha nge a bit set at ’0’ bac k to ’1’. One of the Er ase

Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

4.0.4 Unlock Bypass command

The Unloc k Bypass command is used in conjunction with the Unlock Bypass Program

command to program the memory. When the access time t o the device is l ong (as with

some EPROM programmers) considerable time saving can be made by using these

commands. Thr ee Bus Write oper at ions ar e requir ed to issue t he Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock

Bypass Program command and th e Unlo ck Bypass Reset comm a nd . The mem o ry can be

read as if in Read mode.

4.0.5 Unlock Bypass Program command

The Unlock Bypass Program command can be used to program one address in memory at

a time. The command req uires two Bus Write operations, the final write operation latches

the address and data in the internal state machine and starts the Program/Erase Controller.

The Program operation using the Unlock Bypass Program comma nd behaves identically to

the Program operation using the Program command. A protected block cannot be

programmed; the operation cannot be aborted and the Status Register is read. Errors must

be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode.

See the Program command for details on the behavior.

4.0.6 Unlock Bypass Reset command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from

Unloc k Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass

Reset command. Read/Reset command does not exit from Unlock Bypass Mode.

Command Interface M29F800DT

18/53

4.0.7 Chip Erase command

The Chip Erase comman d can be used to erase the entir e chip. Six Bus Write oper ations

are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any bl o cks are protec te d th en the se are igno re d an d all the ot he r blocks are erased. If all

of the blocks are protected the Chip Erase operation appears to start but will terminate

within about 100µs , leaving the data unchanged. No error cond ition is giv en when pro tected

blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue

any command to abort the oper ation. Typical chip erase times are given in Table 6. All Bus

Read operations during the Chip Erase oper ation will output the Status Register on the Data

Inputs/Outputs. See Section 5: Status Register, for more details.

After the Chip Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs the memory will continue to output the

Status Register. A Read/Reset command must be issued to reset the error cond ition and

return to Read Mode.

The Chip Erase Comm and set s all of th e bits in unpr ot ected blocks of the m emory to ’1’. All

prev ious data is lost.

4.0.8 Block Erase command

The Block Erase command can be used t o erase a list of one or more blocks. Six Bus Write

operat ions are required to select the first b loc k in the list. Each additional bl ock in the list can

be selected by repeating the sixth Bus Write operation using the address of the additional

bl ock. The Block Erase operation starts the Prog ram/Erase Controller about 50 µs after the

last Bus Write operation. Once the Program/Erase Controller starts it is not possible to

select any more blocks. Each additional block must therefore be selected within 50µs of the

last b loc k. The 50µs timer rest arts when an additio nal bloc k is select ed. The Status Regist er

can be read after the sixth Bus Write operation. See the St atus Register for details on how

to identify if the Program/Erase Controller has started the Block Erase operation.

If an y selected b l oc ks are prote cted then t hese are ignored and all the other selected b locks

are erased. If all of the selected blocks are protected the Block Erase operation ap pears to

start but will terminate within about 100µs, lea ving the data unchanged. No error condition is

given when protected b loc ks are ignored.

During the Block Erase oper ation the memory will ignore all commands except the Erase

Suspend command. Typical b l oc k erase ti mes are giv en in Table 6. All Bus Read operations

during the Block Erase operation will output the Status Register on the Data Inputs/Outputs.

See Section 5: Status Register, for more details.

After the Block Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs the memory will continue to output the

Status Register. A Read/Reset command must be issued to reset the error cond ition and

return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All

previous data in the selected blocks is lost.

M29F800DT Command Interface

19/53

4.0.9 Erase Suspend command

The Erase Suspend command may be used to tempor arily suspend a Block Erase oper ation

and return the memory to Read mode. The comm and requires one Bus Write operation.

The Program/Er ase Controller will suspend within the Er ase Suspend Latency Time (refer to

Table 6 for value) of the Erase Suspend command being issued. Once the Program/Erase

Controller has stopped the memory will be set to Read mode and the Erase will be

suspended. If the Er ase Suspend command is issued during the period when the memory is

waiting for an addition al bloc k (bef or e the Progr am/Erase Co ntroller starts) then the Erase is

suspended immediately and will start immediately when the Erase Resume command is

issued. It is not possible to select any further blocks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being

erased; both Read and Program operations behave as normal on these blocks. If any

attempt is made to prog ram in a p rotected b loc k or in the suspended b loc k then th e Progr am

command is ignored and the data remains unchanged. The Status Register is not read and

no error condition is giv e n. Reading from blocks that are being erased will output the Status

It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands

during an Erase Suspend. The Read/Reset command must b e issued to return the de vice to

Read Array mode before the Resume command will be accepted.

4.0.10 Erase Resume command

The Erase Resume command must be used to r estart the Program/Erase Controller from

Erase Suspend. An erase can be suspended and resumed more than once.

4.0.11 Read CFI Query command

The Read CFI Query Command is used to read data from the Co mmon Flash Interface

(CFI) Memory Area. This command is valid when the device is ready to read the array data

or when the device is in autoselected mode.

One Bus Write cycle is required to issue the Read CFI Query Command. Once the

command is issued subsequent Bus Read operations read from the Common Flash

Interface Memory Area. The Read/Reset command must be issued to return the device to

Read Array mode. See Appendix B, Table 21, Table 22, Table 23, Table 24, Table 25, and

Appendix B: Common Flash Int erface (CFI), for details on the information contained in the

Common Flash Inte rface (CFI) memory area.

4.0.12 Block Protect and Chip Unprotect commands

Each block can be separately protected against accidental Program or Erase. The whole

chip can be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are described in Appendix C.

Command Interface M29F800DT

20/53

Table 4. Commands, 16-bit mode, BYTE = VIH(1)

Command

Length

Bus Write operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1XF0

3555AA2AA55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass Program 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 55 98

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in

hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-

DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

M29F800DT Command Interface

21/53

Table 5. Commands, 8-bit mode, BYTE = VIL(1)

Command

Length

Bus Write operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1XF0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Unlock Bypass 3 AAA AA 555 55 A AA 20

Unlock Bypass

Program 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 AA 98

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in

hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-

DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

Table 6. Program, Erase times and Program, Erase Endurance cycles

Parameter Min Typ(1)(2) Max(2) Unit

Chip Erase 12 60(3) s

Block Erase (64 Kbytes) 0.8 6(4) s

Erase Suspend Latency time 30 µs

Program (Byte or Word) 10 200(3) µs

Chip Program (Byte by Byte) 12 60(3) s

Chip Program (Wor d by Word) 6 30(3) s

Program/Erase cycles (per Block) 100,000 cycles

Data Retention 20 years

1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.

4. Maximum value measured at worst case conditions for both temperature and VCC.

Status Register M29F800DT

22/53

5 Status Register

Bus Read oper ations from any a ddress alwa ys read the Stat us Register during Program a nd

Erase operations. It is also read during Erase Suspend when an address within a block

being erased is accessed.

The bits in the Status Register are summarized in Table 7: Status Register Bits.

5.0.1 Data Polling Bit (DQ7)

The Data Polling Bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Data

Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being

programmed to DQ7. After successful completion of the Prog ram operation the memory

returns to Read mode and Bus Read operations from the address just programmed output

DQ7, not its complement.

During Erase operations the Data P olling Bit outputs ’0’, the complement of the erased state

of DQ7. After successful completion of the Erase operation the memory returns to Read

Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation

within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the

Program/Er ase Controller has suspended the Erase operation.

Figure 6: Data P olling flowchart, giv es an e xample of ho w to use the Data P olling Bit. A Valid

Address is the address bein g programmed or an address within th e block being erased.

5.0.2 Toggle Bit (DQ6)

The Toggle Bit can be used to identify whether the Prog ram/Erase Controller has

successfully completed its operation or if it has responded to an Er ase Suspend. The Toggle

Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations at any address . After successful completion of the

operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a b lock

being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has

suspended the Erase operation.

If any attempt is made to erase a protected bloc k, the operation is aborted, no error is

signalled and DQ6 toggles f or approximately 100µs. If any attempt is made to program a

protected block or a suspended block, the operatio n is aborted, no error is signalled and

DQ6 toggles for approximately 1µs.

Figure 7: Data Toggle flowchart, gives an example of how to use the Data Toggle Bit.

M29F800DT Status Register

23/53

5.0.3 Error Bit (DQ5)

The Error Bit can be used to identify errors detected by t he Program/Erase Controller. The

Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the

correct data to the memory. If the Error Bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit is output on DQ5 when the Status Register

is read.

Note that the Prog ram command cannot change a bit set to ’0’ back to ’1’ and attempting to

do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.

One of the Erase commands must be used to set all the bits in a block or in the whole

memory from ’0’ to ’1’

5.0.4 Erase Timer Bit (DQ3)

The Erase Timer Bit can be u sed to iden tify the st art of Program/Erase Controller operation

during a Bloc k Erase command. Once the Program/Erase Controller starts erasing the

Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit

is set to ’0’ and additional blocks to be erased may be written to the Command Interface.

The Erase Timer Bit is output on DQ3 when the Status Register is read.

5.0.5 Alternative Toggle Bit (DQ2)

The Alternative Toggle Bit can be used to monitor the Program/Erase controller during

Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is

read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,

etc., with successiv e Bus Read operations from ad dresses within the b locks being er ased. A

protected block is treated the same as a block not being erased. Once the operation

completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with

successive Bus Read ope r at ion s f rom addre sses within the blocks being erased. Bus Read

operations to addresses within bloc ks not being erased will output the memory cell data as if

in Read mode.

After an Er ase oper ation that causes t he Error Bit to b e set the Alternative To ggle Bit can b e

used to identify which block or blocks have caused the error. The Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses

within blocks that have not erased correctly. The Alternative Toggle Bit does not change if

the addressed block has erased correctly.

Status Register M29F800DT

24/53

Figure 6. Data Polling flowchart

Table 7. Status Register Bits(1)

1. Unspecified data bits should be ignored.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any address DQ7 Toggle 0 – – 0

Program during

Erase Suspend Any address DQ7 Toggle 0 – – 0

Program Error Any address DQ7 Toggle 1 – – 0

Chip Erase Any address 0 Toggle 0 1 Toggle 0

Block Erase

before timeout Erasing Block 0 Toggle 0 0 Togg le 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error Good Block address 0 Toggle 1 1 No Toggle 0

Faulty Block address 0 Toggle 1 1 Toggle 0

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI03598

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

M29F800DT Status Register

25/53

Figure 7. Data Toggle flowchart

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI01370C

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

Maximum rating M29F800DT

26/53

6 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ra tings" table may

cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions

for extended periods may affect device reliability. These are stress ratings only and

operation of the device at these or any other conditions above those indicated in the

Operating sections of this specification is not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality documen ts.

Table 8. Absolute maximum ratings

Symbol Parameter Min Max Unit

TBIAS Temperature under bias –50 125 °C

TSTG Storage temperature –65 150 °C

VIO Input or Output voltage(1)(2)

1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.

–0.6 VCC +0.6 V

VCC Supply voltage –0.6 6 V

VID Identification voltage –0.6 13.5 V

M29F800DT DC and AC parameters

27/53

7 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The par ameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

Table 9: Operating and AC measurement conditions. Designers should check that the

operat ing conditions in their circuit match the operating conditions when relying on the

quoted parameters.

Figure 8. AC measurement I/O wavef orm

Table 9. Operating and AC measurement conditions

Parameter

M29F800D

Unit

55 70/ 90

Min Max Min Max

VCC Supply voltage 4.5 5.5 4.5 5.5 V

Ambient Operating Temperature (range 1) 0 70 0 70 °C

Ambient Operating Temperature (range 6) –40 85 –40 85 °C

Load capacitance (CL) 30 100 pF

Input Rise and Fall times 10 10 ns

Input Pulse voltages 0 to 3 0.45 to 2.4 V

Input and Output Timing Ref. voltages 1.5 0.8 and 2.0 V

AI05276

High Speed (55ns)

1.5V

2.4V

Standard (70, 90ns)

0.45V

2.0V

0.8V

DC and AC parameters M29F800DT

28/53

Figure 9. AC measurement Load Circuit

Table 10. Devi ce capacitance(1)

1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input capacitance VIN = 0V 6 pF

COUT Output capacitance VOUT = 0V 12 pF

AI05277

1.3V

OUT

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

VCC

0.1µF

M29F800DT DC and AC parameters

29/53

Figure 10. Read Mode AC wavef orms

Table 11. DC characterist ics

Symbol Parameter Test condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz 20 mA

ICC2 Supply Current (Standby) TTL E = VIH 2mA

ICC3 Supply Current (Standby) CMOS E = VCC ±0.2V, RP = VCC ±0.2V 150 µA

ICC4(1) Supply Current (Program/Erase) Program/Erase Controller activ e 20 mA

VIL Input Low voltage –0.5 0.8 V

VIH Input High voltage 2 VCC + 0.5 V

VOL Output Low vo ltage IOL = 5.8mA 0.45 V

VOH Output High voltage TTL CMOS IOH = –2.5mA 2.4 V

VID Identification voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO Program/Erase Lockout Supply voltage 3.2 4.2 V

1. Sampled only, not 100% tested.

AI06154

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

DC and AC parameters M29F800DT

30/53

Table 12. Read AC characterist ics

Symbol Alt Parameter Test condition M29F800D Unit

55 70/ 90

tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL Min 55 70 ns

tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL Max 55 70 ns

tELQX(1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 55 70 ns

tGLQX(1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 30 ns

tEHQZ(1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 18 20 ns

tGHQZ(1) tDF Output Enable High to Output Hi-Z E = VIL Max 18 20 ns

tEHQX tGHQX

tAXQX tOH Chip Enable, Output Enable or Address

Transition to Output Transition Min 0 0 ns

tELBL

tELBH

tELFL

tELFH Chip Enable to BYTE Low or High Max 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns

1. Sampled only, not 100% tested.

M29F800DT DC and AC parameters

31/53

Figure 11. Write AC waveforms, Write Enable controlled

AI06155

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

DC and AC parameters M29F800DT

32/53

Figure 12. Write AC waveforms, Chip Enable controlled

Table 13. Write AC characteristics, Write Enable controlled

Symbol Alt Parameter M29F800D Unit

55 70/ 90

tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns

tELWL tCS Chip Enable Low to Write Enab le Low Min 0 0 ns

tWLWH tWP Write Enab l e Low to Write Enable Hig h Min 45 45 ns

tDVWH tDS Input Valid to Write Enable High Min 45 45 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 45 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 n s

tWHGL tOEH Write Enable High to Output Enable Low Mi n 0 0 ns

tWHRL(1) tBUSY Progr a m/Erase Valid to RB Low Max 30 30 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

1. Sampled only, not 100% tested.

AI06156

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

M29F800DT DC and AC parameters

33/53

Figure 13. Reset/Block Temporary Unprotect AC waveforms

Table 14. Write AC ch aracteristics, Chip Enable controlled

Symbol Alt Parameter M29F800D Unit

55 70/ 90

tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 45 45 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 2 0 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tEHRL(1)

1. Sampled only, not 100% tested.

tBUSY Program/Erase Valid to RB Low Max 30 30 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

AI06870

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

DC and AC parameters M29F800DT

34/53

Table 15. Reset/Block Temporary Unprotect AC characteristics

Symbol Alt Parameter M29F800D Unit

55 70/ 90

tPHWL(1) tPHEL

tPHGL(1)

1. Sampled only, not 100% tested.

tRH RP High to Write Enable Low, Chip

Enable Low, Output Enable Low Min 50 50 ns

tRHWL(1)

tRHEL(1)

tRHGL(1) tRB RB High to Write Enable Low, Chip

Enable Low, Output Enable Low Min 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 ns

tPLYH(1) tREADY RP Low to Read Mode Max 10 10 µs

tPHPHH(1) tVIDR RP Rise Time to VID Min 500 500 ns

M29F800DT Package mechanical

35/53

8 Package mechanical

In order to meet environmental requirements, ST offe rs these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect . The categor y of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Package mechanical M29F800DT

36/53

Figure 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, package

outline

1. Drawing is not to scale.

Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils bod y width, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.80 0.1102

A1 0.10 0.0039

A2 2.30 2.20 2.40 0.0906 0.0866 0.0945

b 0.40 0.35 0.50 0.0157 0.0138 0.0197

C 0.15 0.10 0.20 0.0059 0.0039 0.0079

CP 0.08 0.0030

D 28.20 28.00 28.40 1.1102 1.1024 1.1181

E 13.30 13.20 13.50 0.5236 0.5197 0.5315

EH 16.00 15.75 16.25 0.6299 0.6201 0.6398

e 1.27 – – 0.0500 – –

L 0.80 0.0315

α8° 8°

N44 44

SO-d

LA1 α

eCP

M29F800DT Package mechanical

37/53

Figure 15. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline

1. Drawing is not to scale.

Table 17. TSOP48 – 48 lead Plastic Thin Small Ou tline, 12 x 20mm, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.080 0.0031

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

α3° 0 5° 3° 0 5°

TSOP-G

DIE

LA1 α

Part numbering M29F800DT

38/53

9 Part numbering

Table 18. Ordering information scheme

Example: M29 F 800DB 55 N 6 T

Device Type

M29

Operating Voltage

F = VCC = 5V ± 10%

Device Function

800D = 8 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

55 = 55 ns

70 = 70 ns

90 = 90 ns

Package

M = SO44

N = TSOP48: 12 x 20 mm

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

E = ECOPACK® package , standard package

F = ECOPACK® package, tape & reel 24mm packing

M29F800DT Part numbering

39/53

Devices are shipped from the factory with the memory content bi ts erased to ’1’.

F or a list of a vailable opti ons (Spe ed, Pack age, etc.) or for further information on any aspect

of this device, please contact the ST Sales Office nearest to you.

Block address table M29F800DT

40/53

Appendix A Block address table

Table 19. Top Boot Block addresses, M29F800D

# Size (Kbytes) Address range (x8) Address range (x16)

18 16 FC000h-FFFFFh 7E000h-7FFFFh

17 8 FA000h-FBFFFh 7D000h-7DFFFh

16 8 F8000h-F9FFFh 7C000h-7CFFFh

15 32 F0000h-F7FFFh 78000h-7BFFFh

14 64 E0000h-EFFFFh 70000h-77FFFh

13 64 D0000h-DFFFFh 68000h-6FFFFh

12 64 C0000h-CFFFFh 60000h-67FFFh

11 64 B0000h-BFFFFh 58000h-5FFFFh

10 64 A0000h-AFFFFh 50000h-57FFFh

9 64 90000h-9FFFFh 48000h-4FFFFh

8 64 80000h-8FFFFh 40000h-47FFFh

7 64 70000h-7FFFFh 38000h-3FFFFh

6 64 60000h-6FFFFh 30000h-37FFFh

5 64 50000h-5FFFFh 28000h-2FFFFh

4 64 40000h-4FFFFh 20000h-27FFFh

3 64 30000h-3FFFFh 18000h-1FFFFh

2 64 20000h-2FFFFh 10000h-17FFFh

1 64 10000h-1FFFFh 08000h-0FFFFh

0 64 00000h-0FFFFh 00000h-07FFFh

M29F800DT Block address table

41/53

Table 20. Bottom Boot Block addresses, M29F800DB

# Size (Kbytes) Address range (x8) Address range (x16)

18 64 F0000h-FFFFFh 78000h-7FFFFh

17 64 E0000h-EFFFFh 70000h-77FFFh

16 64 D0000h-DFFFFh 68000h-6FFFFh

15 64 C0000h-CFFFFh 60000h-67FFFh

14 64 B0000h-BFFFFh 58000h-5FFFFh

13 64 A0000h-AFFFFh 50000h-57FFFh

12 64 90000h-9FFFFh 48000h-4FFFFh

11 64 80000h-8FFFFh 40000h-47FFFh

10 64 70000h-7FFFFh 38000h-3FFFFh

9 64 60000h-6FFFFh 30000h-37FFFh

8 64 50000h-5FFFFh 28000h-2FFFFh

7 64 40000h-4FFFFh 20000h-27FFFh

6 64 30000h-3FFFFh 18000h-1FFFFh

5 64 20000h-2FFFFh 10000h-17FFFh

4 64 10000h-1FFFFh 08000h-0FFFFh

3 32 08000h-0FFFFh 04000h-07FFFh

2 8 06000h-07FFFh 03000h-03FFFh

1 8 04000h-05FFFh 02000h-02FFFh

0 16 00000h-03FFFh 00000h-01FFFh

Common Flash Interface (CFI) M29F800DT

42/53

Appendix B Common Flash Interface (CFI)

The Common F lash Interf ace is a JEDEC appro ve d, standardiz ed data structure tha t can be

read from the Flash memory device. It allows a system software to query the device to

determine various electrical and timing parameters, density information and functions

supported by the memory. The system can interface easily with the device, enabling the

software to upgrade itself when necessary.

When the CFI Query Command is issued the device enters CFI Query mode and the data

structure is read from the memory. Table 21, Table 22, Table 23, Table 24, Table 25, and

Table 26 show the addresses used to retrieve the data.

The CFI data structure also cont ains a security area wher e a 64 bit uniq ue security numbe r

is written (see Table 26: Security Code Area). This area can be accessed only in Read

mode by the final user. It is impossible to change the security number after it has been

written by ST. Issue a Read command to return to Read mode.

Table 21. Query structure overview(1)

1. Query data are always presented on the lowest order data outputs.

Address Sub-section name Description

x16 x8

10h 20h CFI Query Identification String Command set ID and algorithm data offset

1Bh 36h System Interface Information Device timing & voltage information

27h 4Eh Device Geometry Definition Flash device layout

40h 80h Primary Algorithm-specific

Extended Query table Additional information specific to the

Primary Algorithm (optional)

61h C2h Securi ty Code Area 64 bit unique device number

M29F800DT Common Flash Interfa ce (CFI)

43/53

Table 22. CFI Query Identification String(1)

1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Address Data Description Value

x16 x8

10h 20h 0051h "Q"

11h 22h 0052h Query Unique ASCII String "QRY" "R"

12h 24h 0059h "Y"

13h 26h 0002h Primary Algorithm Command Set and Control Interf ace ID

code 16 bit ID code defining a specific algorithm AMD

Compatible

14h 28h 0000h

15h 2Ah 0040h Address for Primary Algorithm extended Query table (see

Table 24)P = 40h

16h 2Ch 0000h

17h 2Eh 0000h Alternate Vendor Command Set and Control Interface ID

Code second vendor - specified algorithm suppo rted NA

18h 30h 0000h

19h 32h 0000h Address for Alternate Algorithm extended Query table NA

1Ah 34h 0000h

Table 23. CFI Query System Interface Information

Address Data Description Value

x16 x8

1Bh 36h 0045h VCC Logic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV 4.5V

1Ch 38h 0055h VCC Logic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV 5.5V

1Dh 3Ah 0000h VPP [Programming] Supply Minimum Program/Erase voltage NA

1Eh 3Ch 0000h VPP [Programming] Supply Maximum Program/Erase voltage NA

1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs

20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs NA

21h 42h 000Ah Typical timeout per individual block er ase = 2n ms 1s

22h 44h 0000h Typical timeout for full chip erase = 2n ms see note(1)

1. Not supported in the CFI

23h 46h 0004h Maximum timeout for byte/word progra m = 2n times typical 256µs

24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA

25h 4Ah 0003h Maximum timeout per individual block er ase = 2n times typical 8s

26h 4Ch 0000h Maximum timeout f or chip erase = 2n times typical see note(1)

Common Flash Interface (CFI) M29F800DT

44/53

Table 24. Device Geometry Definition

Address Data Description Value

x16 x8

27h 4Eh 0014h Device Size = 2n in number of bytes 1 MByte

28h

29h 50h

52h 0002h

0000h Flash Device Interface Code description x8, x16

Async.

2Ah

2Bh 54h

56h 0000h

0000h Maximum number of bytes in multi-byte progr a m or page = 2n NA

2Ch 58h 0004h Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing

contiguous Erase Blocks of the same size. 4

2Dh

2Eh 5Ah

5Ch 0000h

0000h Region 1 Information

Number of identical size erase block = 0000 h+1 1

2Fh

30h 5Eh

60h 0040h

0000h Region 1 Information

Block size in Region 1 = 0040h * 256 byte 16 Kbyte

31h

32h 62h

64h 0001h

0000h Region 2 Information

Number of identical size erase block = 0001 h+1 2

33h

34h 66h

68h 0020h

0000h Region 2 Information

Block size in Region 2 = 0020h * 256 byte 8 Kbyte

35h

36h 6Ah

6Ch 0000h

0000h Region 3 Information

Number of identical size erase block = 0000 h+1 1

37h

38h 6Eh

70h 0080h

0000h Region 3 Information

Block size in Region 3 = 0080h * 256 byte 32 Kbyte

39h

3Ah 72h

74h 000Eh

0000h Region 4 Information

Number of identical-size erase block = 000Eh+1 15

3Bh

3Ch 76h

78h 0000h

0001h Region 4 Information

Block size in Region 4 = 0100h * 256 byte 64 Kbyte

M29F800DT Common Flash Interfa ce (CFI)

45/53

Table 25. Primary Algorithm-specific Extended Query table

Address Data Description Value

x16 x8

40h 80h 0050h

Primary Algorithm Extended Query table unique ASCII string “PRI”

"P"

41h 82h 0052h "R"

42h 84h 0049h "I"

43h 86h 0031h Major version number, ASCII "1"

44h 88h 0030h Minor version number, ASCII "0"

45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required

Silicon Revision Number (bits 7 to 2) Yes

46h 8Ch 0002h Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write 2

47h 8Eh 0001h Block Protection

00 = not supported, x = number of sectors in per group 1

48h 90h 0001h Temporar y Block Unprotect

00 = not supported, 01 = supported Yes

49h 92h 0004h Block Protect /Unprotect

04 = M29W400B 4

4Ah 94h 0000h Simultaneous Operations, 00 = not supported No

4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No

4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page

word No

Table 26. Security Code Area

Address Data Description

x16 x8

61h C3h, C2h XXXX

64 bit: unique device number

62h C5h, C4h XXXX

63h C7h, C6h XXXX

64h C9h, C8h XXXX

Block protection M29F800DT

46/53

Appendix C Block protection

Bloc k protect ion can be used to preven t an y oper at ion from modif ying the data stored in th e

Flash. Each Block can be protected individually. Once protected, Program and Erase

operations on the block fail to change the data.

There are three techniques that can be used to control Block Protection, these are the

Programmer technique, the In-System technique and Temporary Unprotection. Tempor ary

Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is

descr ibe d in th e S ign al De scriptions section.

Unlike the Command Interface of the Program/Erase Controller, the techniques for

protecting and unprotecting blocks change between different Flash memory suppliers. For

example, the techniques for AMD parts will not work on STMicroelectronics parts. Care

should be taken when changing drivers for one part to work on another.

9.1 Programmer technique

The Programmer technique uses high (VID) voltag e levels on some of the bus pins. These

cannot be achieved using a standard microprocessor b us, therefore the technique is

recommended only for use in Programming Equipment.

To protect a block follow the flowchart in Figure 16: Programmer Equipment Block Protect

flowchart. To unprote ct the whole chip it is necessary to protect all of th e bl oc ks first, then all

bl ocks can be unprotected at the same time. To unprotect the chip follow Figure 17:

Programmer Equipment Chip Unprotect flowchart. Table 27: Programmer technique bus

operations, BYTE = VIH or VIL, gives a summary of each oper ation.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a

pause is specified, it is followed as closely as possible. Do not abort the procedure before

reaching the end. Chip Unprotect can take several seconds and a user message should be

provided to show that the operation is progressing.

9.2 In-System technique

The In-System technique requires a high voltage level on the Reset/Blocks Temporary

Unprotect pin, RP. This can be achieved without violating the maximum ratings of the

components on the micro processor b us , ther ef or e this technique is suit ab le for use after the

Flash has been fitted to the system.

To protect a block follow the flowchart in Figure 18: In-System Equipment Block Protect

flowchart. To unprote ct the whole chip it is necessary to protect all of th e bl oc ks first, then all

the blocks can be unprotected at the same time. To unprotect the chip follow Figure 19: In-

System Equipment Chip Unprotect flowchart.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a

pause is specified, it is followed as closely as possibl e. Do not allow the microproces so r to

service interrupts that will upset the timing and do not abort the procedure before reaching

the end. Chip Unprote ct can take several seconds and a user message should be provided

to show that the operation is progressing.

M29F800DT Block protection

47/53

Table 27. Program mer technique bus operations, BYTE = VIH or VIL

Operation E G W Address Inputs

A0-A18 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Block Protect VIL VID VIL Pulse A9 = VID, A12-A18 Block address

Others = X X

Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH

Others = X X

Block Protection

verify VIL VIL VIH

A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,

A12-A18 Block address

Others = X

Pass = XX01h

Retr y = XX00h

Block Unprotection

verify VIL VIL VIH

A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,

A12-A18 Block address

Others = X

Retry = XX01h

Pass = XX00h

Block protection M29F800DT

48/53

Figure 16. Programmer Equipment Block Protect flowchart

ADDRESS = BLOCK ADDRESS

AI03469

G, A9 = VID,

E = VIL

n = 0

Wait 4µs

Wait 100µs

W = VIL

W = VIH

E, G = VIH,

A0, A6 = VIL,

A1 = VIH

A9 = VIH

E, G = VIH

++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

W = VIH

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

Verify Protect Set-upEnd

A9 = VIH

E, G = VIH

M29F800DT Block protection

49/53

Figure 17. Programmer Equipment Chip Unprotect flowchart

PROTECT ALL BLOCKS

AI03470

A6, A12, A15 = VIH(1)

E, G, A9 = VID

DATA

W = VIH

E, G = VIH

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1, A6 = VIH

Wait 10ms

00h

INCREMENT

CURRENT BLOCK

n = 0

CURRENT BLOCK = 0

Wait 4µs

W = VIL

++n

= 1000

START

YES

YESNO

NO LAST

BLOCK

YES

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

FAIL PASS

Verify Unprotect Set-upEnd

A9 = VIH

E, G = VIH A9 = VIH

E, G = VIH

Block protection M29F800DT

50/53

Figure 18. In-System Equipment Blo ck Protect flowchart

AI03471

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

n = 0

Wait 100µs

WRITE 40h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VIH ++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

RP = VIH

Wait 4µs

Verify Protect Set-upEnd

READ DATA

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

M29F800DT Block protection

51/53

Figure 19. In-System Equipment Chip Unprotect flowchart

AI03472

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

n = 0

CURRENT BLOCK = 0

Wait 10ms

WRITE 40h

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VIH

++n

= 1000

START

FAIL PASS

YES

DATA

00h

YESNO

RP = VIH

Wait 4µs

READ DATA

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PROTECT ALL BLOCKS

INCREMENT

CURRENT BLOCK

LAST

BLOCK

YES

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

Verify Unprotect Set-upEnd

Revision history M29F800DT

52/53

Revision history

Table 28. Document revision history

Date Revision Revision details

13-Dec-2001 -01 Fi rst Issue

21-Jan-2002 -02 VIH(max) value corrected

01-Mar-2002 -03

Description of Ready/Busy signal clarified (and Figure 13: Reset/Block

Temporary Unprotect AC waveforms modified)

Clarified allowable commands during block erase

Clarified the mode the device returns to in the CFI Read Query command

section

17-Feb-2003 4.0

Revision numbering modified: a mi nor revision will be indicated by

incrementing the digit after the dot, and a major re vision, by incrementing

the digit before the dot (revision version 03 equals 3.0).

Erase Suspend Latency Time (typical) and Data Retention parameters

added to Table 6: Program, Erase times and Program, Erase Endurance

cycles, and notes added to the table. Figure 1: Logic diagram, and

Figure 7: Data Toggle flowchart corrected.

Lead-free package options E and F added to Table 18: Ordering

information scheme.

Document promoted to full datasheet.

08-Jul-2003 4.1

TSOP48 package information updated (se e Fig ure 15: TSOP48 – 48

lead Plastic Thin Small Outline, 12 x 20mm, package outline and

Table 17: TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm,

package mechanical data). Cross-references updated in Appendix B:

Common Flash Interface (CFI) on page 42. Temperature range 3 added.

24-Aug-2006 5

Changed document to new template; indicated that Ready/Busy Ou tput

now a vailab le for both SO44 and TSOP48 packages (see Table 1.: Signal

names); removed temperature range 3 from Table 9 and Table 18;

ecopack compliant

M29F800DT

53/53

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers a re so lel y res ponsibl e fo r th e choic e, se lecti on an d use o f th e ST pr oduc ts and s ervi ces d escr ibed he rein , and ST as sumes no

liability whatsoever relati ng to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document ref er s to an y t hi rd pa rt y p roduc t s or serv ic es it sh al l n ot be dee med a li ce nse gr an t by ST for t he use of su ch t hi rd party products

or services, or any intel lectual pro perty conta ined therei n or considere d as a warranty covering the use in any mann er whatsoev er of such

third party products or servi ces or any intellect u al property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTAB ILIT Y, FITNESS F OR A PARTI CULAR PURPOS E (AND THEIR EQUIVALE NTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warrant y granted by ST for the S T product or se rvice descr ibed herein a nd shall no t create or e xtend in any manner whatsoe ver, any

liability of ST.

ST and the ST lo go are trademarks or registered trademarks of ST in various countries.

Information in this document su persedes and replaces all informatio n previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroele ctr on ic s gr ou p of compan ie s

Australia - Belgium - Brazil - Canada - China - Czech Republic - F inland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America