Data Sheet
©2008 Silicon Storage Technology, Inc.
S71297-04-000 12/08
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
16 Mbit (x16) Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
FEATURES:
Organized as 1M x16
Single Voltage Read and Write Operations
1.65-1.95V
Superior Reliability
Endurance: 100,000 Cycles (Typical)
Greater than 100 years Data Retention
Low Power Consumption (typical values at 5 MHz)
Active Current: 5 mA (typical)
Standby Current: 5 µA (typical)
Auto Low Power Mode: 5 µA (typical)
Hardware Block-Protection/WP# Input Pin
Top Block-Protection (top 32 KWord)
for SST39WF1602
Bottom Block-Protection (bottom 32 KWord)
for SST39WF1601
Sector-Erase Capability
Uniform 2 KWord sectors
Block-Erase Capability
Uniform 32 KWord blocks
Chip-Erase Capability
Erase-Suspend/Erase-Resume Capabilities
Hardware Reset Pin (RST#)
Security-ID Feature
SST: 128 bits; User: 128 bits
Fast Read Access Time:
70 ns, 90 ns
Latched Address and Data
Fast Erase and Word-Program:
Sector-Erase Time: 36 ms (typical)
Block-Erase Time: 36 ms (typical)
Chip-Erase Time: 140 ms (typical)
Word-Program Time: 28 µs (typical)
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bits
Data# Polling
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pin Assignments and
Command Sets
Packages Available
48-ball TFBGA (6mm x 8mm)
48-ball WFBGA (5mm x 6mm)
48-ball WFBGA (4mm x 6mm)
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39WF1601/1602 devices are 1M x16 CMOS
Multi-Purpose Flash Plus (MPF+) manufactured with
SST’s proprietary, high-performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39WF1601/
1602 write (Program or Erase) with a 1.65-1.95V power
supply. These devices conform to JEDEC standard pin
assignments for x16 memories.
Featuring high performance Word-Program, the
SST39WF1601/1602 devices provide a typical Word-Pro-
gram time of 28 µsec. These devices use Toggle Bit or
Data# Polling to indicate the completion of Program opera-
tion. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
typical endurance of 100,000 cycles. Data retention is rated
at greater than 100 years.
The SST39WF1601/1602 devices are suited for applica-
tions that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than
alternative flash technologies. The total energy consumed
is a function of the applied voltage, current, and time of
application. Since for any given voltage range, the Super-
Flash technology uses less current to program and has a
shorter erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
technologies. These devices also improve flexibility while
lowering the cost for program, data, and configuration stor-
age applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
SST39WF160x2.7V 16Mb (x16) MPF+ memories
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2
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
To meet high density, surface mount requirements, the
SST39WF1601/1602 are offered in both 48-ball TFBGA
and 48-ball WFBGA packages. See Figures 2 and 3 for
pin assignments.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39WF1601/1602 also have the Auto Low Power
mode which puts the device in a near standby mode after
data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 9 mA to
typically 5 µA. The Auto Low Power mode reduces the typi-
cal IDD active read current to the range of 2 mA/MHz of
Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
Read
The Read operation of the SST39WF1601/1602 is con-
trolled by CE# and OE#, both have to be low for the sys-
tem to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 4).
Word-Program Operation
The SST39WF1601/1602 are programmed on a word-by-
word basis. Before programming, the sector where the
word exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within 40
µs. See Figures 5 and 6 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 20 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during the internal Program opera-
tion are ignored. During the command sequence, WP#
should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39WF1601/1602 offer both Sector-
Erase and Block-Erase modes. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The Block-
Erase operation is initiated by executing a six-byte com-
mand sequence with Block-Erase command (50H) and
block address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 10 and 11 for
timing waveforms and Figure 24 for the flowchart. Any
commands issued during the Sector- or Block-Erase oper-
ation are ignored. When WP# is low, any attempt to Sector-
(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
3
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Chip-Erase Operation
The SST39WF1601/1602 provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 10 for tim-
ing diagram, and Figure 24 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39WF1601/1602 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39WF1601/1602 are in the internal Pro-
gram operation, any attempt to read DQ7 will produce the
complement of the true data. Once the Program operation
is completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 21 for a flowchart.
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4
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or CE#)
pulse of Write operation. See Figure 8 for Toggle Bit timing
diagram and Figure 21 for a flowchart.
Note: DQ7 and DQ2 require a valid address when reading
status information.
Data Protection
The SST39WF1601/1602 provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST39WF1602 support top hardware block protec-
tion, which protects the top 32 KWord block of the device.
The SST39WF1601 support bottom hardware block pro-
tection, which protects the bottom 32 KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 32 KWord when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place (see Figure 16).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39WF1601/1602 provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
6 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to read mode within TRC. The contents of DQ15-DQ8
can be VIL or VIH, but no other value, during any SDP com-
mand sequence.
TABLE 1: Write Operation Status
Status DQ7DQ6DQ2
Normal
Operation
Standard
Program
DQ7# Toggle No Toggle
Standard
Erase
0 Toggle Toggle
Erase-
Suspend
Mode
Read from
Erase-Suspended
Sector/Block
1 1 Toggle
Read from
Non- Erase-Suspended
Sector/Block
Data Data Data
Program DQ7# Toggle N/A
T1.0 1297
TABLE 2: Boot Block Address Ranges
Product Address Range
Bottom Boot Block
SST39WF1601 000000H-007FFFH
Top Boot Block
SST39WF1602 0F8000H-0FFFFFH
T2.0 1297
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
5
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
Common Flash Memory Interface (CFI)
The SST39WF1601/1602 contain the CFI information to
describe the characteristics of the device. The
SST39WF1601/1602 support the original SST CFI Query
mode implementation for compatibility with existing SST
devices as well as the general CFI Query mode. Both will
be explained in subsequent paragraphs.
In order to enter the SST CFI Query mode, the system
must write the three-byte sequence, same as the product
ID entry command with 98H (CFI Query command) to
address 5555H in the last byte sequence. Once the device
enters CFI Query mode, the system can read CFI data at
the addresses given in Tables 7 through 9. The system
must write the CFI Exit command to return to Read mode
from the CFI Query mode.
In order to enter the general CFI Query mode, the system
must write a one-byte sequence with entry command with
98H to address 55H. Once the device enters the CFI
Query mode, the system can read CFI data at the
addresses given in Tables 7 through 9. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as
the SST39WF1601, SST39WF1602 and manufacturer as
SST. This mode may be accessed software operations.
Users may use the Software Product Identification opera-
tion to identify the part (i.e., using the device ID) when
using multiple manufacturers in the same socket. For
details, see Table 6 for software operation, Figure 12 for
the Software ID Entry and Read timing diagram and Fig-
ure 22 for the Software ID Entry command sequence
flowchart.
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figure 14 for timing waveform, and Figures 22 and
23 for flowcharts.
Security ID
The SST39WF1601/1602 devices offer a 256-bit Security
ID space. The Secure ID space is divided into two 128-bit
segments - one factory programmed segment and one
user programmed segment. The first segment is pro-
grammed and locked at SST with a random 128-bit num-
ber. The user segment is left un-programmed for the
customer to program as desired.
To program the user segment of the Security ID, the user
must use the Security ID Word-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-
byte command sequence with Enter Sec ID command
(88H) at address 5555H in the last byte sequence. To exit
this mode, the Exit Sec ID command should be executed.
Refer to Table 6 for more details.TABLE 3: Product Identification
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST39WF1601 0001H BF274B
SST39WF1602 0001H BF274A
T3.0 1297
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6
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 1: Functional Block Diagram
FIGURE 2: Pin assignments for 48-ball TFBGA
Y-Decoder
I/O Buffers and Data Latches
1297 B1.0
Address Buffer & Latches
X-Decoder
DQ15 - DQ0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
WP#
RESET#
A13
A9
WE#
NC
A7
A3
A12
A8
RST#
WP#
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
A19
NC
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
1297 48-tfbga B3K P1.1
TOP VIEW (balls facing down)
6
5
4
3
2
1
A B C D E F G H
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
7
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 3: Pin assignments for 48-ball WFBGA
A2
A1
A0
CE#
V
SS
A4
A3
A5
DQ8
OE#
DQ0
A6
A7
A18
DQ10
DQ9
DQ1
A17
WP#
A19
DQ2
NC
DQ3
NC
V
DD
WE#
DQ12
RST#
NC
NC
DQ13
A9
A10
A8
DQ4
DQ5
DQ14
A11
A13
A12
DQ11
DQ6
DQ15
A14
A15
A16
DQ7
V
SS
TOP VIEW (balls facing down)
A B C D E F G H J K L
6
5
4
3
2
1
1297 48-wfbga MBQ P02.0
SST39WF160x
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8
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
TABLE 4: Pin Description
Symbol Pin Name Functions
AMS1-A0Address Inputs To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.
RST# Reset To reset and return the device to Read mode.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 1.65-1.95V
VSS Ground
NC No Connection Unconnected pins.
T4.0 1297
1. AMS = Most significant address
AMS = A19 for SST39WF1601/1602
TABLE 5: Operation Modes Selection
Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1
1. X can be VIL or VIH, but no other value.
Sector or block address,
XXH for Chip-Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
XXV
IH High Z/ DOUT X
Product Identification
Software Mode VIL VIL VIH See Table 6
T5.0 1297
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
9
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
TABLE 6: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2
Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3Data
Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX430H
Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX450H
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Erase-Suspend XXXXH B0H
Erase-Resume XXXXH 30H
Query Sec ID55555H AAH 2AAAH 55H 5555H 88H
User Security ID
Word-Program
5555H AAH 2AAAH 55H 5555H A5H WA6Data
User Security ID
Program Lock-Out
5555H AAH 2AAAH 55H 5555H 85H XXH60000H
Software ID Entry7,8 5555H AAH 2AAAH 55H 5555H 90H
SST CFI Query Entry 5555H AAH 2AAAH 55H 5555H 98H
General CFI Query Mode 55H 98H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
5555H AAH 2AAAH 55H 5555H F0H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
XXH F0H
T6.0 1297
1. Address format A14-A0 (Hex).
Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST39WF1601/1602.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A19 for SST39WF1601/1602
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000008H to 00000FH).
User ID Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 00000FH.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39WF1601 Device ID = BF274BH, is read with A0 = 1,
SST39WF1602 Device ID = BF274AH, is read with A0 = 1.
AMS = Most significant address
AMS = A19 for SST39WF1601/1602
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and
000008H to 00000FH.
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10
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
TABLE 7: CFI Query Identification String1
Address Data Data
10H 0051H Query Unique ASCII string “QRY”
11H 0052H
12H 0059H
13H 0002H Primary OEM command set
14H 0000H
15H 0000H Address for Primary Extended Table
16H 0000H
17H 0000H Alternate OEM command set (00H = none exists)
18H 0000H
19H 0000H Address for Alternate OEM extended Table (00H = none exits)
1AH 0000H
T7.0 1297
1. Refer to CFI publication 100 for more details.
TABLE 8: System Interface Information
Address Data Data
1BH 0016H VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH 0020H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH 0000H VPP min. (00H = no VPP pin)
1EH 0000H VPP max. (00H = no VPP pin)
1FH 0005H Typical time out for Word-Program 2N µs (25 = 32 µs)
20H 0000H Typical time out for min. size buffer program 2N µs (00H = not supported)
21H 0005H Typical time out for individual Sector/Block-Erase 2N ms (25 = 30 ms)
22H 0007H Typical time out for Chip-Erase 2N ms (27 = 128 ms)
23H 0001H Maximum time out for Word-Program 2N times typical (21 x 25 = 64 µs)
24H 0000H Maximum time out for buffer program 2N times typical
25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms)
26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms)
T8.0 1297
TABLE 9: Device Geometry Information
Address Data Data
27H 0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 0001H y = 511 + 1 = 512 sectors (01FF = 511)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H 001FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 0000H y = 31 + 1 = 32 blocks (001F = 31)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.0 1297
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
11
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range Ambient Temp VDD
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
1.65-1.95V
1.65-1.95V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 18 and 19
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12
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
TABLE 10: DC Operating Characteristics VDD = 1.65-1.95V1
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD Power Supply Current Address input=VILT/VIHT, at f=5 MHz,
VDD=VDD Max
Read 10 mA CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase 25 mA CE#=WE#=VIL, OE#=VIH
ISB Standby VDD Current240 µA CE#=VIHC, VDD=VDD Max
IALP Auto Low Power 40 µA CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILIW Input Leakage Current
on WP# pin and RST#
10 µA WP#=GND to VDD or RST#=GND to VDD
ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.2VDD VV
DD=VDD Min
VIH Input High Voltage 0.8VDD VV
DD=VDD Max
VOL Output Low Voltage 0.1 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.1 V IOH=-100 µA, VDD=VDD Min
T10.0 1297
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 1.8V. Not 100% tested.
2. For all SST39WF160x commercial and industrial devices, ISB typical is under 5 µA.
TABLE 11: Recommended System Power-up Timings
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Power-up to Read Operation 100 µs
TPU-WRITE1Power-up to Program/Erase Operation 100 µs
T11.0 1297
TABLE 12: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
CI/O1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
I/O Pin Capacitance VI/O = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
T12.0 1297
TABLE 13: Reliability Characteristics
Symbol Parameter Minimum Specification Units Test Method
NEND1,2
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
T13.0 1297
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
13
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
AC CHARACTERISTICS
TABLE 14: Read Cycle Timing Parameters VDD = 1.65-1.95V
Symbol Parameter
SST39WF1601/1602-70 SST39WF1601/1602-90
UnitsMin Max Min Max
TRC Read Cycle Time 70 90 ns
TCE Chip Enable Access Time 70 90 ns
TAA Address Access Time 70 90 ns
TOE Output Enable Access Time 35 50 ns
TCLZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
CE# Low to Active Output 0 0 ns
TOLZ1OE# Low to Active Output 0 0 ns
TCHZ1CE# High to High-Z Output 40 40 ns
TOHZ1OE# High to High-Z Output 40 40 ns
TOH1Output Hold from Address Change 0 0 ns
TRP1RST# Pulse Width 500 500 ns
TRHR1RST# High before Read 50 50 ns
TRY1,2
2. This parameter applies to Sector-Erase, Block-Erase and Program operations.
This parameter does not apply to Chip-Erase operations.
RST# Pin Low to Read Mode 203
3. This parameter is 100 µs if reset after an Erase operation.
203µs
T14.0 1297
TABLE 15: Program/Erase Cycle Timing Parameters
Symbol Parameter Min Max Units
TBP Word-Program Time 40 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 50 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 50 ns
TWP WE# Pulse Width 50 ns
TWPH1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
WE# Pulse Width High 30 ns
TCPH1CE# Pulse Width High 30 ns
TDS Data Setup Time 50 ns
TDH1Data Hold Time 0 ns
TIDA1Software ID Access and Exit Time 150 ns
TSE Sector-Erase 50 ms
TBE Block-Erase 50 ms
TSCE Chip-Erase 200 ms
T15.0 1297
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14
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 4: Read Cycle Timing Diagram
FIGURE 5: WE# Controlled Program Cycle Timing Diagram
1297 F03.1
ADDRESS A19-0
DQ15-0
WE#
OE#
CE#
TCE
TRC TAA
TOE
TOLZ
VIH
HIGH-Z
TCLZ TOH TCHZ
HIGH-Z
DATA VALIDDATA VALID
TOHZ
1297 F04.1
ADDRESS A19-0
DQ15-0
TDH
TWPH
TDS
TWP
TAH
TAS
TCH
TCS
CE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
WE#
TBP
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
15
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 6: CE# Controlled Program Cycle Timing Diagram
FIGURE 7: Data# Polling Timing Diagram
1297 F05.1
ADDRESS A19-0
DQ15-0
TDH
TCPH
TDS
TCP
TAH
TAS
TCH
TCS
WE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
CE#
TBP
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
1297 F06.1
ADDRESS A19-0
DQ7DATA DATA# DATA# DATA
WE#
OE#
CE#
TOEH
TOE
TCE
TOES
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16
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 8: Toggle Bits Timing Diagram
FIGURE 9: WE# Controlled Chip-Erase Timing Diagram
1297 F07.1
ADDRESS A19-0
DQ6 and DQ2
WE#
OE#
CE#
TOE
TOEH
TCE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
1297 F08.1
ADDRESS A19-0
DQ15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX10XX55XXAA XX80 XXAA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
TSCE
TWP
Note: This device also supports CE# controlled Chip-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15.)
WP# must be held in proper logic state (VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
17
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 10: WE# Controlled Block-Erase Timing Diagram
FIGURE 11: WE# Controlled Sector-Erase Timing Diagram
1297 F09.1
ADDRESS A19-0
DQ15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX50XX55XXAA XX80 XXAA
BAX
OE#
CE#
SIX-BYTE CODE FOR BLOCK-ERASE
TBE
TWP
Note: This device also supports CE# controlled Block-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15.)
BAX = Block Address
WP# must be held in proper logic state (VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
1297 F10.1
ADDRESS A19-0
DQ15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX30XX55XXAA XX80 XXAA
SAX
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
TWP
Note: This device also supports CE# controlled Sector-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15.)
SAX = Sector Address
WP# must be held in proper logic state (VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
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18
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 12: Software ID Entry and Read
FIGURE 13: CFI Query Entry and Read
1297 F11.1
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0 SW1 SW2
5555 2AAA 5555 0000 0001
OE#
CE#
Three-Byte Sequence for Software ID Entry
TWP
TWPH TAA
00BF
Device ID
XX55XXAA XX90
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
Device ID - See Table 3
X can be VIL or VIH, but no other value.
1297 F12.1
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0 SW1 SW2
5555 2AAA 5555
OE#
CE#
Three-Byte Sequence for CFI Query Entry
TWP
TWPH TAA
XX55XXAA XX98
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
19
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 14: Software ID Exit/CFI Exit
FIGURE 15: Sec ID Entry
1297 F13.1
ADDRESS A14-0
DQ15-0
TIDA
TWP
TWHP
WE#
SW0 SW1 SW2
5555 2AAA 5555
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
OE#
CE#
XXAA XX55 XXF0
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
1297 F20.1
ADDRESS A19-0
TIDA
DQ15-0
WE#
SW0 SW1 SW2
5555 2AAA 5555
OE#
CE#
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
TWP
TWPH TAA
XX55XXAA XX88
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
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20
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 16: RST# Timing Diagram (When no internal operation is in progress)
FIGURE 17: RST# Timing Diagram (During Program or Erase operation)
1297 F22.0
RST#
CE#/OE#
TRP
TRHR
1297 F23.1
RST#
CE#/OE#
TRP
TRY
End-of-Write Detection
(Toggle-Bit)
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
21
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 18: AC Input/Output Reference Waveforms
FIGURE 19: A Test Load Example
1297 F14.1
REFERENCE POINTS OUTPUTINPUT VIT
VIHT
VILT
VOT
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Te s t
VOT - VOUTPUT Tes t
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
1297 F15.1
TO TESTER
TO DUT
CL
VDD
25K
25K
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22
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 20: Word-Program Algorithm
1297 F16.0
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
X can be VIL or VIH, but no other value
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
23
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 21: Wait Options
1297 F17.0
Wait TBP,
TSCE, TSE
or TBE
Program/Erase
Initiated
Internal Timer Toggle Bit
Ye s
Ye s
No
No
Program/Erase
Completed
Does DQ6
match?
Read same
word
Data# Polling
Program/Erase
Completed
Program/Erase
Completed
Read word
Is DQ7 =
true data?
Read DQ7
Program/Erase
Initiated
Program/Erase
Initiated
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24
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 22: Software ID/CFI Entry Command Flowcharts
1297 F21.0
Load data: XXAAH
Address: 5555H
Software Product ID Entry
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX90H
Address: 5555H
Wait TIDA
Read Software ID
Load data: XXAAH
Address: 5555H
CFI Query Entry
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX98H
Address: 5555H
Wait TIDA
Read CFI data
Load data: XXAAH
Address: 5555H
Sec ID Query Entry
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX88H
Address: 5555H
Wait TIDA
Read Sec ID
X can be VIL or VIH, but no other value
Load data: XX98H
Address: 55H
General
CFI Query Entry
Command Sequence
Wait TIDA
Read CFI data
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
25
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 23: Software ID/CFI Exit Command Flowcharts
1297 F18.0
Load data: XXAAH
Address: 5555H
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XXF0H
Address: 5555H
Load data: XXF0H
Address: XXH
Return to normal
operation
Wait TIDA
Wait TIDA
Return to normal
operation
X can be VIL or VIH, but no other value
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26
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 24: Erase Command Sequence
1297 F19.0
Load data: XXAAH
Address: 5555H
Chip-Erase
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XXAAH
Address: 5555H
Wait TSCE
Chip erased
to FFFFH
Load data: XXAAH
Address: 5555H
Sector-Erase
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX30H
Address: SAX
Load data: XXAAH
Address: 5555H
Wait TSE
Sector erased
to FFFFH
Load data: XXAAH
Address: 5555H
Block-Erase
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX50H
Address: BAX
Load data: XXAAH
Address: 5555H
Wait TBE
Block erased
to FFFFH
X can be V
IL
or V
IH,
but no other value
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
27
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
PRODUCT ORDERING INFORMATION
Valid Combinations for SST39WF1601
SST39WF1601-70-4C-B3KE SST39WF1601-70-4C-MBQE SST39WF1601-70-4C-Y1QE
SST39WF1601-70-4I-B3KE SST39WF1601-70-4I-MBQE SST39WF1601-70-4I-Y1QE
SST39WF1601-90-4C-B3KE SST39WF1601-90-4C-MBQE SST39WF1601-90-4C-Y1QE
SST39WF1601-90-4I-B3KE SST39WF1601-90-4I-MBQE SST39WF1601-90-4I-Y1QE
Valid Combinations for SST39WF1602
SST39WF1602-70-4C-B3KE SST39WF1602-70-4C-MBQE SST39WF1602-70-4C-Y1QE
SST39WF1602-70-4I-B3KE SST39WF1602-70-4I-MBQE SST39WF1602-70-4I-Y1QE
SST39WF1602-90-4C-B3KE SST39WF1602-90-4C-MBQE SST39WF1602-90-4C-Y1QE
SST39WF1602-90-4I-B3KE SST39WF1602-90-4I-MBQE SST39WF1602-90-4I-Y1QE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls
Q = 48 balls (66 possible positions)
Package Type
B3 = TFBGA (6mm x 8mm)
MB = WFBGA (5mm x 6mm)
Y1 = WFBGA (4mm x 6mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
160 = 16 Mbit
Voltage
W = 1.65-1.95V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
SST 39 WF 1602 - 70 - 4C - B3K E
XX XXXXXX- XXX -XX-XXX X
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28
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
PACKAGING DIAGRAMS
FIGURE 25: 48-ball Thin-Profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
FIGURE 26: 48-ball Very-Very-Thin-Profile, Fine-pitch Ball Grid Array (WFBGA) 5mm x 6mm
SST Package Code MBQ
A1 CORNER
H G F E D C B A
A B C D E F G H
BOTTOM VIEWTOP VIEW
SIDE VIEW
6
5
4
3
2
1
6
5
4
3
2
1
SEATING PLANE
0.35 ± 0.05
1.10 ± 0.10
0.12
6.00 ± 0.20
0.45 ± 0.05
(48X)
A1 CORNER
8.00 ± 0.20
0.80
4.00
0.80
5.60
48-tfbga-B3K-6x8-450mic-4
Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
1mm
L K J H G F E D C B A
ABCDEFGHJKL
6
5
4
3
2
1
6
5
4
3
2
1
0.50
0.50
BOTTOM VIEW
5.00 ± 0.08
0.32 ± 0.05
(48X)
6.00 ± 0.08
2.50
5.00
A1 CORNER
TOP VIEW
48-wfbga-MBQ-5x6-32mic-0
1mm
DETAIL SIDE VIEW
SEATING PLANE
0.20 ± 0.06
0.73 max.
0.636 nom.
0.08
A1 INDICATOR
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm (± 0.05 mm)
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Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
29
©2008 Silicon Storage Technology, Inc. S71297-04-000 12/08
FIGURE 27: 48-ball Very-Very-Thin-Profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm
SST Package Code Y1Q
TABLE 16: Revision History
Number Description Date
00 Initial release Oct 2005
01 Added MBQ package information including product numbers.
Migrated document to Preliminary Specifications
Updated Table 10 on page 12
Jul 2006
02 Added 70 ns to Features: Fast Read Access Time
Added 70 ns columns to Table 14
Edited Product Ordering Information and Valid Combination to include 70 ns and
remove leaded parts.
Aug 2007
03 Added YIQE package Jul 2008
04 Changed 000010H to 000017H to 000008H to 00000FH three places in footnotes
of Table 6 on page 9.
Dec 2008
L K J H G F E D C B A
ABCDEFGHJKL
6
5
4
3
2
1
6
5
4
3
2
1
0.50
0.50
BOTTOM VIEW
0.32
±0.05
(48X)
A1 INDICATOR4
2.50
5.00
A1 CORNER
TOP VIEW
48-wfbga-Y1Q-4x6-320mic-5-2.0
Note: 1. Complies with JEDEC Publication 95, MO-207, variant CZB-4, dimensions except nominal ball width
is larger.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. No ball is present in position A1; a gold-colored indicator is present.
5. Ball width at interface to package body surface is 0.29 mm.
1mm
DETAIL SIDE VIEW
SEATING PLANE
0.23 ±0.06
0.61 ±0.10
0.08
4.00
±0.08
6.00
±0.08
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
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