LTC4309
1
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The LTC
®
4309 hot swappable 2-wire bus buffer allows
I/O card insertion into a live backplane without corrup-
tion of the data and clock busses. The LTC4309 provides
bidirectional buffering, keeping the backplane and card
capacitances isolated. Low offset and high VOL tolerance
allows cascading of multiple devices on the clock and data
busses. If SDAOUT or SCLOUT are low for 30ms, FAULT
will pull low indicating a stuck bus low condition. If DISCEN
is tied high, the LTC4309 will automatically break the bus
connection and generate up to 16 clock pulses and a stop
bit in an attempt to free the bus. A connection will resume
if the stuck bus is cleared. If DISCEN is connected to GND,
the busses will remain connected with no clock or stop
bit generation. ACC input enables rise-time accelerators
for high capacitively loaded busses.
During insertion, the SDA and SCL lines are precharged to
1V to minimize bus disturbances. When driven high, the
ENABLE input allows the LTC4309 to connect after a stop
bit or bus idle. Driving ENABLE low breaks the connection
between SDAIN and SDAOUT, SCLIN and SCLOUT. READY
is an open drain output which indicates that the backplane
and card sides are connected.
Level Shifting Low Offset Hot
Swappable 2-Wire Bus Buffer
with Stuck Bus Recovery
n Live Board Insertion
n Servers
n Capacitance Buffer/Bus Extender
n RAID Systems
n ATCA
n Bidirectional Buffer Increases Fanout
n 60mV Buffer Offset Independent of Load
n Optional Disconnect when Bus is Stuck Low
n Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
n Level Shift 2.5V, 3.3V and 5V Busses
n Compatible with Non-Compliant VOL I2C Devices
n ±6kV Human Body Model ESD Ruggedness
n Isolates Input SDA and SCL Lines from Output
n Compatible with I2C™, I2C Fast-Mode and SMBus
n READY Open Drain Output
n FAULT Open Drain Output
n 1V Precharge on All SDA and SCL Lines
n Optional Rise Time Accelerators
n High Impedance SDA, SCL Pins for VCC = 0
n Available in Small 12-Pin DFN (4mm x 3mm) and
16-Lead SSOP Packages
Rising Edge from Asserted Low
4309 TA01
ENABLEEN
SCLIN
SDAIN
SCL1
SDA1
FAULT
ACC
VCC
GND
SCLOUT
SDAOUT
SCL2
SDA2
LTC4309
READY
3.3V
5V
3.3V
3.3V
10k
10k 10k
2.7k 2.7k
10k
ENABLE
VCC2
VCC2
SCLIN
CARD
CONNECTOR
BACKPLANE
CONNECTOR
SDAIN
FAULT
ACC
VCC
GND
SCLOUT
SDAOUT
LTC4309
READY
5V 5V
10k
100k 10k 10k
0.01μF
0.01μF
10k
FAULT FAULT
DISCENDISCEN
100ns/DIV
0
0
200mV/DIV
200
400
600
800
1000
100 200 300 400
4309 G01
500 600
SDAOUT
SDAIN
LOW
OFFSET
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
6356140, 6650174, 7032051.
LTC4309
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VCC, VCC2 to GND ............................................–0.3 to 6V
SDAIN, SCLIN, SDAOUT, SCLOUT, READY,
ENABLE, FAULT, ACC, DISCEN .......................–0.3 to 6V
Maximum Sink Current (SDA, SCL, FAULT, READY)
ISINK ......................................................................50mA
(Note 1, 6)
Operating Temperature
LTC4309C ................................................ 0°C to 70°C
LTC4309I.............................................. –40°C to 85°C
Storage Temperature Range (DE)........... –65°C to 125°C
Storage Temperature Range (GN) .......... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
GN Package ...................................................... 300°C
12
11
10
9
8
7
1
2
3
4
5
6
VCC
VCC2
SDAOUT
SDAIN
FAULT
READY
ENABLE
DISCEN
SCLOUT
SCLIN
ACC
GND
TOP VIEW
13
DE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) PCB CONNECTION TO GND IS OPTIONAL
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
ENABLE
NC
DISCEN
SCLOUT
SCLIN
ACC
NC
GND
VCC
NC
VCC2
SDAOU
T
SDAIN
FAULT
NC
READY
TJMAX = 150°C, θJA = 110°C/W
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4309CDE#PBF LTC4309CDE#TRPBF 4309 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC4309IDE#PBF LTC4309IDE#TRPBF 4309 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC4309CGN#PBF LTC4309CGN#TRPBF 4309 16-Lead Plastic SSOP 0°C to 70°C
LTC4309IGN#PBF LTC4309IGN#TRPBF 4309I 16-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ABSOLUTE MAXIMUM RATINGS
LTC4309
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The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Positive Supply Voltage l2.3 5.5 V
VCC2 Input Side Accelerator Supply Voltage l1.8 5.5 V
ICC VCC Input Supply Current Enabled VCC = VCC2 = 5.5V, VSDAIN = VSCLIN = 0V (Note 2) l711 mA
ISD VCC Input Supply Current Disabled VCC = VCC2 = 5.5V, SDA = SCL = 5.5V, ENABLE = OV l900 1400 μA
ICC2 VCC2 Input Supply Current Enabled VCC = VCC2 = 5.5V, VSDAIN = VSCLIN = 0V (Note 2) l190 250 μA
ISD2 VCC2 Input Supply Current Disabled VCC = VCC2 = 5.5V, SDA = SCL = 5.5V, ENABLE = OV l140 180 μA
Propagation Delay and Rise Time Accelerators
tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL, (Note 3, 4), (Figure 1) 85 ns
tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL, (Note 3, 4), (Figure 1) 10 ns
tRISE SDA/SCL Rise Time CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC = 5V VCC2 = 5V,
(Note 3, 5), (Figure 1)
30 300 ns
tFALL SDA/SCL Fall Time CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC = 5V (Note 3, 5),
(Figure 1)
30 300 ns
IPULLUPAC Transient Boosted Pull-up Current Positive Transition > 0.8V/μS on SDA, SCL, VCC = 3.3V (Note 7) 5 8 mA
Start-Up Circuitry
VPRE Precharge Voltage SDA, SCL Open l0.8 1.0 1.2 V
tIDLE Bus Idle Time l55 95 175 μs
VTHR_EN ENABLE Threshold Voltage ENABLE Rising Edge l0.8 1.4 2 V
VTHR_EN(HYST) ENABLE Threshold Voltage Hysteresis (Note 3) 100 mV
VTHR_CTRL ACC, DISCEN Threshold Voltage 0.5 0.7 1 V
ICTRL ENABLE, ACC, DISCEN Input Currents ENABLE, ACC, DISCEN from 0 to VCC l0.1 ±5 μA
tPLH_EN ENABLE Delay Off-On (Figure 1) 95 μs
tPHL_EN ENABLE Delay On-Off (Note 3), (Figure 1) 10 ns
tPLH_READY READY Delay On-Off (Note 3), (Figure 1) 10 ns
tPHL_READY READY Delay Off-On (Note 3), (Figure 1) 10 ns
VOL_READY READY Output Low Voltage IREADY = 3mA, VCC = 2.3V l0.4 V
IOFF_READY READY Off Leakage Current VCC = READY = 5.5V l0.1 ±5 μA
Timing Characteristics
fI2C, MAX I2C Maximum Operating Frequency (Note 3) 400 600 kHz
tBUF Bus Free Time Between Stop and Start
Condition
(Note 3) 1.3 μs
tHD, STA Hold Time After (Repeated)
Start Condition
(Note 3) 100 ns
tSU, STA Repeated Start Condition Set-Up Time (Note 3) 0 ns
tSU, STO Stop Condition Set-Up Time (Note 3) 0 ns
tHD, DATI Data Hold Time Input (Note 3) 0 ns
tSU, DAT Data Set-Up Time (Note 3) 100 ns
Input-Output Connection
VOS Input-Output Offset Voltage 2.7k to VCC2 on SDA, SCL, Driven SDA, SCL = 0.2V l20 60 100 mV
VTHR SDA, SCL Logic Input Threshold Voltage VCC ≥ 2.9V
VCC < 2.9V
1.4
1.1
1.65
1.35
1.9
1.6
V
V
ELECTRICAL CHARACTERISTICS
LTC4309
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TIMING DIAGRAMS
ENABLE and READY Timing
tPLH_EN
ENABLE
CONNECT
READY
tPLH_READY tPHL_READY
tPHL_EN
4309 TD01
SDA/SCL Propagation Delays, Rise and Fall Times
tPLH
SDAIN/SCLIN
SDAOUT/SCLOUT
tPHL tRISE tFALL
tRISE tFALL
4309 TD02
Figure 1. Timing Diagrams
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VTHR(HYST) SDA, SCL Logic Input Threshold Voltage
Hysteresis
(Note 3) 50 mV
CIN Digital Input Capacitance SDAIN,
SDAOUT, SCLIN, SCLOUT
(Note 3) 10 pF
ILEAK Input Leakage Current SDA, SCL, ACC, DISCEN Pins l±5 μA
VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA, Driven SDA/SCL = 0.2V, VCC =
VCC2 = 2.7V
l0 0.4 V
2.7k to VCC on SDA, SCL, Driven SDA/SCL = 0.1V,
VCC = VCC2 = 3.3V
l120 170 205 mV
VILMAX Buffer Input Logic Low Voltage l1.2 V
Bus Stuck Low Timeout
tTIMEOUT Bus Stuck Low Timer SDAOUT, SCLOUT = OV l25 30 35 ms
VOL_FAULT FAULT Output Low Voltage IFAULT = 3mA l0.4 V
IOFF_FAULT FAULT Off Leakage Current l0.1 ±5 μA
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Test performed with connection circuity active.
Note 3: Determined by design, not subject to test.
Note 4: For larger equivalent bus capacitance, the skew increases, and
setup and hold times must be adjusted accordingly. Please see the
Operation Section of the datasheet.
Note 5: Measure points are 0.3 • VCC and 0.7 • VCC.
Note 6: All currents into pins are positive, all voltages are referenced to
GND, unless otherwise specifi ed.
Note 7: IPULLUPAC varies with temperature and VCC voltage as shown in the
Typical Performance Characteristics section.
ELECTRICAL CHARACTERISTICS
LTC4309
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ICC Enabled Current vs
Temperature
ICC Disabled Current vs
Temperature
ICC2 Enabled Current vs
Temperature
ICC2 Disabled Current vs
Temperature
Offset Voltage vs Pull-Up
Resistance
Input-Output High to Low
Propagation Delay vs Temperature
T
A = 25°C, VCC = 3.3V, VCC2 = 3.3V unless
otherwise noted.
TEMPERATURE (oC)
–50
ICC ENABLED CURRENT (mA)
6.5
7
7.5
25 75
4309 G02
6
5.5
5–25 0 50
8
100
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
TEMPERATURE (°C)
–50
0
IPULLUPAC (mA)
4
8
12
–25 025 50
4309 G03
75
16
20
100
VCC = 5.5V
VCC = 3.3V
TEMPERATURE (oC)
–50
100
120
SUPPLY CURRENT (MA)
140
160
180
–25 025 50
4309 G04
75
200
220
100
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
Input-Output High to Low Propagation
Delay vs Output Capacitance
OUTPUT CAPACITANCE (pF)
0
PROPAGATION DELAY (ns)
90
70
100
110
120
130
140
150
160
80
200 400 600 800
4309 G08
1000
CIN = 50pF
RPULLUPIN = 2.7k7
RPULLUPOUT = 2.7k7
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
TEMPERATURE (oC)
–50
90
SUPPLY CURRENT (MA)
100
110
120
130
140
160
–25 02550
4309 G05
75 100
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
PULL-UP RESISTANCE (kΩ)
0
50
OFFSET VOLTAGE (mV)
58
70
62
66
54
46
4309 G09
2810
VOL = 0.1V
CIN = COUT = 50pF
RPULLUPIN = 2.7kΩ
TEMPERATURE (°C)
–50
PROPAGATION DELAY (ns)
140
120
110
100
90
80
70
60
50 75
4309 G06
–25 0 25 100
CIN = COUT = 50pF
RPULLUPIN = RPULLUPOUT = 2.7kΩ
VCC = 5.5V
VCC = 3.3V
130
VCC = 2.3V
Boost Pull-Up Current vs
Temperature
TEMPERATURE (°C)
–50
BOOST PULL-UP CURRENT (mA)
30
25
20
15
10
5
0
50 75
4309 G07
–25 0 25 100
CIN = 50pF
COUT = 1nF
RPULLUPIN = RPULLUPOUT = 2.7kΩ
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
TYPICAL PERFORMANCE CHARACTERISTICS
LTC4309
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ENABLE (Pin 1/Pin1): Connection Enable Input. This 1.4V
digital threshold input pin enables or disables the LTC4309.
For normal operation pull or connect ENABLE high. Driving
ENABLE below the 0.8V threshold isolates SDAIN from
SDAOUT, SCLIN from SCLOUT, asserts READY low, and
prohibits automatic clock and stop bit generation during a
fault condition. A rising edge on ENABLE after a fault has
occurred forces a connection between SDAIN, SDAOUT
and SCLIN, SCLOUT. Connect to VCC if unused.
DISCEN (Pin 2/Pin 3 ): Bus Stuck Low Disconnect Enable
Input. This pin, when high, allows the stuck low bus
timeout circuitry to disconnect the bus in a fault condition.
When connected to GND, this pin disables the circuitry
that disconnects the bus under a fault condition; however,
the FAULT pin will still go low.
SCLOUT (Pin 3/Pin 4): Serial Clock Output. Connect this
pin to a SCL bus segment where bus stuck low recovery is
desired. If the output rise time accelerators are enabled, a
pull-up resistor should be connected between this pin and
a bus supply greater than or equal to VCC. Bus supplies
can be lower than VCC if the output rise time accelerators
are disabled. See Application Information section for
detailed bus pull-up supply options.
SCLIN (Pin 4/Pin 5): Serial Clock Input. Connect this pin
to a SCL bus segment where isolation from bus stuck
low issues is desired. If the input rise time accelerator is
enabled, a pull-up resistor should be connected between
this pin and a bus supply greater than or equal to VCC2.
Bus supplies can be lower than VCC2 if the input rise time
accelerators are disabled. See Application Information
section for detailed bus pull-up supply options.
ACC (Pin 5/Pin 6): Rise Time Accelerator Control Input.
This nominal 0.7V threshold input pin enables and disables
all rise time accelerators on the SDA and SCL pins. Connect
ACC to GND to enable all four rise time accelerators or
connect ACC to VCC to disable all four rise time accelerators.
Connect ACC to VCC2 to GND to enable the accelerators
on SDAOUT and SCLOUT only.
GND (Pin 6/Pin 8): Device Ground. Connect this pin to a
ground plane for best results.
READY (Pin 7/Pin 9): Connection Ready Status Output.
This open-drain N-channel MOSFET pin pulls low when
ENABLE is low, when the start-up and connection sequence
described in the Operation section has not been completed,
or when the LTC4309 disconnects the input and output
pins due to a bus stuck low condition. READY goes high
when ENABLE is high and connection is made between the
input and output pins. Connect a pull-up resistor, typically
10k, from this pin to the bus pull-up supply. This pin can
be left open if unused.
FAULT (Pin 8/Pin 11): Bus Stuck Low Timeout Output. This
open drain N-channel MOSFET output pulls low after 30ms
when there is a bus stuck low condition on the output pins
of the LTC4309. In normal operation FAULT is high. Connect
a pull-up resistor, typically 10k, from this pin to the bus
pull-up supply. This pin can be left open if unused.
SDAIN (Pin 9/Pin 12): Serial Clock Input. Connect this
pin to a SDA bus segment where isolation from bus stuck
low issues is desired. If the input accelerator is enabled, a
pull-up resistor should be connected between this pin and
a bus supply greater than or equal to VCC2. Bus supplies
can be lower than VCC2 if the input rise time accelerators
are disabled. See Application Information section for
detailed bus pull-up supply options.
SDAOUT (Pin 10/Pin 13): Serial Clock Output. Connect this
pin to a SCL bus segment where bus stuck low recovery is
desired. If the output rise time accelerators are enabled, a
pull-up resistor should be connected between this pin and
a bus supply greater than or equal to VCC. Bus supplies
can be lower than VCC if the output rise time accelerators
are disabled. See Application Information section for
detailed bus pull-up supply options.
VCC2 (Pin 11/Pin 14): Supply Voltage Input for SDAIN and
SCLIN Rise Time Accelerator Circuitry. VCC2 supplies the
rise time accelerator circuitry on the input side. Bypass
this pin to GND with a capacitor of at least 0.01μF and
place close to VCC2 for best results. If VCC2 is connected
to GND, the input side rise time accelerator circuitry is
disabled, regardless of ACC.
(DE12/GN16)
PIN FUNCTIONS
LTC4309
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4309 BD
+
–
+
–
+
–
+
–
+
–
95μs
DELAY
LOGIC
30ms
TIMER
100k
100k
100k
100k
PC CONNECT
CONNECT
GND
READY
FAULT
SCLOUT
SDAOUT
VCC
ENABLE
DISCEN
ACC
SCLIN
SDAIN
VCC2
CONNECT
UVLO
1.4V/1.3V
1.65V/1.6V
1.35V/1.3V
1.65V/1.6V
1.35V/1.3V
1.65V/1.6V
1.35V/1.3V
1.65V/1.6V
1.35V/1.3V
PC
CONNECT
CONNECT
CONNECT
PC
CONNECT
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
IBOOSTSCL
IBOOSTSDA
PRECHARGE
8mA
VCC
IBOOSTSDA
8mA
VCC
IBOOSTSCL
8mA
VCC2
IBOOSTSDA
8mA
VCC2
IBOOSTSCL
VCC (Pin 12/Pin 16): Supply Voltage Input. Bypass this
pin to GND with a capacitor of at least 0.01μF and place
close to VCC for best results.
EXPOSED PAD (Pin 13 DE12 Package Only): Exposed Pad
may be left open or connected to device ground.
(DE12/GN16)
PIN FUNCTIONS
BLOCK DIAGRAM
LTC4309
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Start-Up
When the LTC4309 fi rst receives power on its VCC pin,
either during power up or live insertion, it starts in an under
voltage lockout (UVLO) state, ignoring any activity on the
SDA or SCL pins until VCC rises above 2V. This ensures
the LTC4309 does not try to function until enough supply
voltage is present.
During this time, the 1V precharge circuitry is actively
forcing 1V through 100k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
and SCL busses may be anywhere between 0V and VCC.
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
moment of contact, therefore minimizing the amount of
disturbance caused by the I/O card.
Once the LTC4309 exits from UVLO, it monitors both the
input and output pins for either a stop bit or a bus idle
condition to indicate the completion of data transactions.
When both sides are idle or one side has a stop bit while
the other is idle, the connection circuitry is activated,
joining the SDA and SCL busses on the input side with
those on the output side.
Rise Time Accelerators
Once connection has been established if ACC is connected
to ground and VCC2 is powered from a supply voltage greater
than or equal to 1.8V, the rise time accelerator circuits on
all four SDA and SCL pins are enabled. During positive bus
transitions of at least 0.8V/μs, the rise time accelerators
provide strong, slew-limited pull-up currents to force the
bus voltage to rise at a rate of 100V/μs. Enabling the rise
time accelerators allows users to choose larger bus pull-
up resistors, reducing power consumption and improving
logic low noise margins, or design with bus capacitances
beyond those specifi ed in the I2C specifi cations.
To ensure the rise time accelerators are properly activated
when the rise time accelerators are enabled, users should
choose bus pull-up resistors that guarantee the bus will
rise on its own at a rate of at least 0.8V/μs. See the Ap-
plication Information section for determining the correct
pull-up resistor size.
All four rise time accelerators can be disabled by connect-
ing ACC to VCC. To activate the rise time accelerators on
only SDAOUT and SCLOUT, connect both ACC and VCC2
to ground. The rise time accelerators are also internally
disabled until the sequence of events described in the
start-up section have been completed, as well as during
automatic clocking and stop bit generation for a bus stuck
low recovery event.
Connection Circuitry
Once the connection circuitry is activated, the functionality
of the input and output bus of the respective SDA or SCL
pins are identical. A low forced on either output or input
pin at any time results in both pin voltages forced low.
The LTC4309 is tolerant of I2C bus DC logic low voltages
up to the VIL specifi cation of 0.3 • VCC.
When the LTC4309 senses a rising edge on the bus, with
a slew rate greater than 0.8V/μs, the internal pull-down
device for the respective bus is deactivated at bus volt-
ages as low as 0.48V. This methodology maximizes the
effectiveness of the rise time accelerator circuitry and
maintains compatibility with other devices in the LTC4300
bus buffer family. Care must be taken to ensure devices
participating in clock stretching or arbitration are capable
of forcing logic low voltages below 0.48V at the LTC4309’s
SDA and SCL pins.
A high occurs when all devices on the input and output
pins release high. These important features ensures the
I2C specifi cation protocols such as clock stretching, clock
synchronization, arbitration, and acknowledge function
seamlessly in all cases as specifi ed, regardless of how the
devices in the system are connected to the LTC4309.
Another key feature provided by the connection circuitry
is input and output bus capacitance isolation through
bidirectional buffering. Because of this isolation, the
waveforms on the input busses look slightly different than
the corresponding output bus waveforms, as described
below.
Input to Output Offset Voltage
When a logic low voltage is driven on any of the LTC4309’s
data or clock pins, the LTC4309 regulates the voltage on
the other side of the device to a slightly higher voltage,
OPERATION
LTC4309
9
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typically 60mV. This offset is nearly independent of pull-up
current. (See Typical Performance curves.)
Propagation Delays
During a rising edge, the rise time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between the
two sides. This effect is displayed in Figure 2 for VCC and
VCC2 = 5.5V and a 10k pull-up resistor on each side (50pF
on one side and 150pF on the other). Since the output side
has less capacitance than the input, it rises faster and the
effective propagation delay is negative.
There is a fi nite propagation delay through the connec-
tion circuitry for falling waveforms. Figure 3 shows the
falling edge waveforms for the same pull-up resistors and
equivalent capacitance conditions as used in Figure 2. An
external N-channel MOSFET device pulls down the voltage
on the side with 150pF capacitance; LTC4309 pulls down
the voltage on the opposite side, with a delay of 85ns. This
delay is always positive and is a function of supply voltage,
temperature and the pull-up resistors and equivalent bus
capacitances on both sides of the bus.
The Typical Performance Characteristics section shows
Propagation Delay as a function of temperature and voltage
for 2.7k pull-up resistors and 50pF equivalent capacitance
on both sides of the part. Also, the Propagation Delay as
a function of Output Capacitance curve shows that larger
output capacitances translate to longer delays. Users must
quantify the difference in propagation times for a rising
edge versus a falling edge in their systems and adjust
setup and hold times accordingly.
Bus Stuck Low Timeout
When SDAOUT or SCLOUT is low, an internal timer is
started. The timer is only reset by the respective pin
going high. If the bus stuck low does not go high within
30ms (typical), the FAULT pin pulls low indicating a bus
stuck low condition. If DISCEN is connected to VCC, the
connection circuitry is disabled, breaking the connection
between the respective input and output pins. In addition,
after at least 40μs, up to 16 clock pulses at 8.5kHz (typi-
cal) is generated on the SCLOUT pin by the LTC4309 in an
attempt to free the stuck low bus. Once the clock pulses
have completed, a stop bit is generated on the SCLOUT
and SDAOUT pins to reset all devices on the bus.
If the stuck low SDAOUT or SCLOUT recovers to a logic
high, the FAULT flag clears, and the LTC4309 waits for
either a stop bit or a bus idle condition to activate the
connection circuitry to reconnect the input and output
busses.
If DISCEN is connected to GND, the FAULT pin will pull
low, but the connection circuitry will not be disabled,
leaving the input and output busses connected. Also, no
clock or stop bit is generated.
When powering up into a bus stuck low condition, the
connection circuitry connecting the SDA and SCL busses
on the I/O card with those on the backplane is not activated.
30ms after UVLO, the FAULT pin pulls low indicating a bus
stuck low condition and automatic clocking and stop bit
generation takes place as described above.
READY Digital Output
This pin provides a digital fl ag which is low when either
ENABLE is low, the start-up sequence described earlier
in this section has not been completed, or the LTC4309
Figure 2. Input-Output Rising Edge Waveforms Figure 3. Input-Output Falling Edge Waveforms
OUTPUT SIDE
50pF
1V/DIV
INPUT SIDE
150pF
1V/DIV
200ns/DIV 4307 F01
INPUT SIDE
150pF
1V/DIV
OUTPUT SIDE
50pF
1V/DIV
200ns/DIV 4307 F02
OPERATION
LTC4309
10
4309fa
has disconnected the input and output busses due to a
bus stuck low condition. READY goes high when ENABLE
is high and start-up is complete. The pin is driven by an
open drain pull-down device capable of sinking 3mA
while holding 0.4V on the pin. Connect a resistor to the
bus pull-up supply to provide the pull-up.
FAULT Digital Output
This pin provides a digital flag which is low when SDA
or SCL is low for 30ms (typical). The pin is driven by an
open drain pull-down capable of sinking 3mA while hold-
ing 0.4V on the pin. Connect a resistor from FAULT to the
bus pull-up supply to provide the pull-up.
Live Insertion and Capacitance Buffering Application
Figures 4 and 5 illustrate applications of the LTC4309 that
take advantage of the LTC4309’s Hot Swap
TM
, capacitance
buffering and precharge features. If the I/O cards were
plugged directly into the backplane without the LTC4309
buffer, all of the backplane and card capacitances would
add directly together, making rise time and fall time re-
quirements difficult to meet. Placing an LTC4309 on the
edge of each card, however, isolates the card capacitance
from the backplane. For a given I/O card, the LTC4309
drives the capacitance of everything on the card and the
backplane must drive only the capacitance of the LTC4309,
which is less than 10pF.
Figure 4 shows the LTC4309 used in the typical staggered
connector application, where VCC and GND are the longest
“early power” pins. The “early power” pins ensure the
LTC4309 is initially powered and forcing a 1V precharge
voltage on the medium length SDA and SCL pins before
they contact to the backplane busses. Coupled with
ENABLE as the shortest pin, passively pulled to ground
by a resistor, the staggered approach provides additional
time for transients associated with live insertion to settle
before the LTC4309 can be enabled.
Figure 5 shows the LTC4309 in an application where all
of the pins have the same length. In this application, a
resistor is used to hold the ENABLE pin low during live
insertion, until the backplane control circuitry can enable
the device.
Repeater/Bus Extender Applications
Users who wish to connect two 2-wire systems separated
by a distance can do so by connecting two LTC4309s back-
to-back, as shown in Figure 6. The I2C specification allows
for 400pF maximum bus capacitance, severely limiting
the length of the bus. The SMBus specification places no
restriction on bus capacitance, but the limited impedances
of devices connected to the bus require systems to remain
small if rise time and fall time specifications are to be met.
In this situation, the differential ground voltage between
the two systems may limit the allowed distance, because
a valid logic low voltage with respect to the ground at one
end of the system may violate the allowed VOL specification
with respect to the ground at the other end. In addition,
the connection circuitry offset voltages of the back-to-
back LTC4309s add together, directly contributing to the
same problem.
Figure 7 further illustrates a repeater application. In
AdvancedTCA applications, the bus pull-up resistance can
be quite small. Since there is no effect on the offset due
OPERATION
APPLICATIONS INFORMATION
Hot Swap is a trademark of Linear Technology Corporation.
ENABLE
When the ENABLE pin is driven below 0.8V with respect
to the LTC4309’s ground, the input pin is disconnected
from the output pin and the READY pin is internally pulled
low. When the pin is driven above 2V, the part waits for
data transactions on both the input and output pins to be
complete (as described in the Start-Up section) before
connecting the two sides. At this time the internal pull-
down on READY releases.
A rising edge on ENABLE after a fault has occurred forces a
connection between SDAIN, SDAOUT and SCLIN, SCLOUT,
even if the bus stuck low conditions has not been cleared.
At this time, the 30ms timer is reset, but not disabled.
LTC4309
11
4309fa
If the rise time accelerators are enabled, the bus pull-up
supply can be greater than or equal to VCC for the output
busses and accordingly, the input pull-up supply can
be greater than or equal to VCC2 for the input busses.
This ensures the LTC4309’s rise time accelerators do
not source current through the pull-up resistors into the
pull-up supply. If the rise time accelerator circuitries are
disabled, the bus pull-up supply can be as low as 2V for
VCC ≥ 2.9V and for VCC < 2.9V, the bus pull-up supply can
be as low as 1.7V. The bound on the lower supply limit
exists to ensure the bus signal range exceeds the logic
input threshold voltage, VTHR.
Resistor Pull-Up Value Selection
To guarantee the rise time accelerators are activated during
a rising edge, the bus must rise on its own with a positive
slew rate of at least 0.8V/μs. To achieve this, choose a
maximum resistor value RPULLUP using the formula:
RPULLUP
(V
BUS(MIN) – 0.8V)•1250 ns
V
CBUS
Where RPULLUP is the pull-up resistor value in kilo ohms,
VBUS(MIN) is the minimum bus pull-up supply voltage and
CBUS is the equivalent bus capacitance in pico-Farads
(pF).
To estimate the value of CBUS, use a general rule of 20pF
of capacitance per device on the bus (10pF for the device
and 10pF for interconnect).
In addition, RPULLUP must be strong enough to overcome
the precharge voltage and provide logic highs on SDAOUT
and SCLOUT for the start-up and connection circuitry to
connect the backplane to the card. Regardless of the bus
capacitance, always choose
RPULLUP VBUS(MAX) –V
THR
100μA
to the pull-up impedance, multiple LTC4309 buffers can
be used in a single system. This allows the user to divide
the line and device capacitances into more sections with
buffering and meet rise and fall times.
The LTC4309 disconnects when both bus I/O’s are above
0.48V and rising. In systems with large ground bounce,
if many devices are cascaded, the 0.48V threshold can be
exceeded, and the transients associated with the ground
bounce can appear to be a rising edge. Under this condition,
the LTC4309 with inputs above 0.48V may disconnect.
Level Shifting Applications
Systems requiring different supply voltages for the
backplane side and the card side can use the LTC4309
for bidirectional level shifting, as shown in Figure 6. The
LTC4309 can level shift between bus pull-up supplies as
low as 1.7V, with the accelerators disabled, to as high as
5.5V. Level shifting allows newer designs that require low
voltage supplies, such as EEPROMs and microcontrollers,
the capability to interface with legacy backplanes which
may be operating at higher supply voltages.
Systems with Supply Voltage Droop
In large 2-wire systems, the supply voltages seen by devices
at various points in the system can differ by a few hundred
millivolts or more. For proper operation, make sure that
the VCC2(LTC4309) is ≥ 1.8V, and VCC(LTC4309) ≥ 2.3V.
Additional Pull-Up Supply Options
In typical applications, a pull-up resistor connected from
the LTC4309’s bus output pins to VCC and bus input pins
to VCC2 or VCC, if VCC2 is grounded, is suffi cient. However,
for unique applications, additional fl exibility is available for
bus pull-up supplies other than VCC or VCC2. One example
is shown in Figure 8. The expanded bus pull-up range is
dependent on the user confi guration of the rise time ac-
celerators and the supply voltage, VCC.
APPLICATIONS INFORMATION
LTC4309
12
4309fa
VCC2
SDAIN
SCLIN
FAULT
READY
ENABLE
SDA
SCL
FAULT
READY
ENA1
DISCEN
SDAOUT
SCLOUT
ACC
C1
0.01μFR5
10k
R1
10k
VCC
VCC2
BACKPLANE
CONNECTOR
BACKPLANE
CARD
CONNECTORS
ENAN
R2
10k
R3
10k
R4
10k
R10
10k
R6
10k
I/O PERIPHERAL CARD 1
LTC4309
VCC
GND
LTC4309
VCC
GND
CARD 1_SDA
CARD 1_SCL
VCC2
SDAIN
SCLIN
FAULT
READY
ENABLE
DISCEN
SDAOUT
SCLOUT
ACC
R7
10k
C4
0.01μF
C3
0.01μF
C2
0.01μF
R8
10k
R9
10k
I/O PERIPHERAL CARD N
CARD N_SDA
CARD N_SCL
4309 F01
Figure 4. The LTC4309 in an Application with a Staggered Connector.
APPLICATIONS INFORMATION
LTC4309
13
4309fa
Figure 6. The LTC4309 in a Level Shifting Repeater/Bus Extender Application.
SDAIN
SCLIN
DISCEN
ENABLE
READY
FAULT
SDAOUT
SCLOUT
C1
0.01μF
C2
0.01μF
LTC4309
VCC VCC2
GND
3.3V
SDA1
2.5V
SCL1
R3
10k
R2
10k
R4
10k
R1
10k
SDAIN
SCLIN
DISCEN
ENABLE
READY
FAULT
SDAOUT
SCLOUT
C4
0.01μF
C3
0.01μF
LTC4309
VCC
VCC2
GND
5V
SDA2
SCL2
R8
10k
R9
10k
R7
10k
R10
10k
R5
2.7k
R6
2.7k
4309 F04
ACC ACC
VCC2
SDAIN
SCLIN
FAULT
READY
ENABLE
SDA
SCL
FAULT
READY
ENA1
DISCEN
SDAOUT
SCLOUT
ACC
C1
0.01μFR5
10k
R1
10k
VCC
VCC2
BACKPLANE
CONNECTOR
BACKPLANE
CARD
CONNECTORS
ENAN
R2
10k
R3
10k
R4
10k
R10
10k
R6
10k
I/O PERIPHERAL CARD 1
LTC4309
VCC
GND
LTC4309
VCC
GND
CARD 1_SDA
CARD 1_SCL
VCC2
SDAIN
SCLIN
FAULT
READY
ENABLE
DISCEN
SDAOUT
SCLOUT
ACC
R7
10k
C4
0.01μF
C3
0.01μF
C2
0.01μF
R8
10k
R9
10k
I/O PERIPHERAL CARD N
CARD N_SDA
CARD N_SCL
4309 F01
Figure 5. The LTC4309 in an Application Where All the Pins Have the Same Length.
APPLICATIONS INFORMATION
LTC4309
14
4309fa
Figure 8. The LTC4309 in a level shifting application where the bus supplies are different from VCC.
4309 F06
SDAIN
SCLIN
DISCEN
ENABLE
READY
FAULT
SDAOUT
SCLOUT
C2
0.01μF
LTC4309
VCC
VCC2
GND
5V
2.5V
SDA2
SCL2
SDA1
SCL1
R4
10k
R5
10k
R3
10k
R6
10k
R1
2.7k
R2
2.7k
ACC
3.3V
Figure 7. The LTC4309 in a Repeater Application. The LTC4309’s Low Offset Allows Cascading of Multiple Devices.
4309 F05
SDAIN
SCLIN
DISCEN
ENABLE
READY
FAULT
SDAOUT
SCLOUT
C1
0.01MF
C2
0.01MF
LTC4309
VCC VCC2
GND
VCC
SDA1
SCL1
R3
10k
R2
2.7k
R4
10k
SDAIN
SCLIN
DISCEN
ENABLE
READY
FAULT
SDAOUT
SCLOUT
C5
0.01MF
LTC4309
VCC VCC2
GND
R11
10k
R12
10k
R1
2.7k
SDAIN
SCLIN
DISCEN
ENABLE
READY
FAULT
SDAOUT
SCLOUT
C4
0.01MF
C3
0.01MF
C6
0.01MF
LTC4309
VCC
VCC2
GND
SDA2
SCL2
R8
10k
R9
2.7k
R7
10k
R10
2.7k
R13
2.7k
R14
2.7k
R5
2.7k
R6
2.7k
VCC
ACCACCACC
APPLICATIONS INFORMATION
LTC4309
15
4309fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 p .004
(0.38 p 0.10) s 45o
0o – 8o TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 p.0015
.045 p.005
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
4.00 p0.10
(2 SIDES)
3.00 p0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 p 0.05
(2 SIDES)
0.75 p0.05
R = 0.115
TYP
R = 0.05
TYP
0.25 p 0.05
3.30 p0.05
(2 SIDES)
16
127
0.50
BSC
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0905 REV C
0.25 p 0.05
3.30 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.70 p0.05
(2 SIDES)
2.20 p0.05
0.50
BSC
0.70 p0.05
3.60 p0.05
PACKAGE OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD
FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
DE/UE Package
12-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1695)
PACKAGE DESCRIPTION
LTC4309
16
4309fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0108 REV A • PRINTED IN USA
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Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled
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LTC4307-1 High Defi nition Multimedia Interface (HDMI) Level Shifting
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4309 F07
SDAIN
SCLIN
DISCEN
ENABLE
READY
FAULT
SDAOUT
SCLOUT
C2
0.01MF
C1
0.01MF
LTC4309
VCC
VCC2
GND
5V3.3V
SDA2
SCL2
SDA1
SCL1
R4
10k
R5
10k
R3
10k
R6
10k
R1
10k
R2
10k
ACC
5V to 3.3V Level Translator
ThinSOT is a trademark of Linear Technology Corporation
