2K x 8 Automotive Dual-port Static RAM
CG5982AF
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06067 Rev. *C Revised September 6, 2005
Features
• True dual-ported memory cells that allow simultaneous
reads of the same memory location
• Automotive temp erature operation: –40°C to +115°C
• 2K x 8 organization
• High-speed access: 55 ns
• Low operating power: ICC = 120 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CG5982AF easily expands data bus wid th to 16
or more bits using slave
• BUSY output flag
•INT
flag for port-to-port communication
Functional Description
The CG5982AF are high-speed CMOS 2K x 8 dual-port static
RAMs. Two ports are provided to permit independent access
to any location in memory. The CG5982AF can be utilized a s
either a standalone 8-bit dual-port static RAM or as a MASTER
dual-port RAM in conjunction with the CG5982AF SLAVE
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output en able (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. On the PLCC
version, INT is an interrupt flag indicating that data has been
placed in a unique l ocation (7FF for the left port and 7FE for
the right port).
An automatic power-down feature is controlled independently
on each port by the chip enable (CE) pins.
The CG5982AF is available in a 52-pin PLCC package.
Notes:
1. CG5982AF (Master): BUSY is open-drain output and requires pull-up resistor.
2. Open drain output s; pull-up resistor required.
Arbitration Logic
and
Interrupt Logic
Logic Block Diagram
Control
I/O Control
I/O
Memory
Array
Address
Decoder
INTL
CEL
OEL
R/WL
CER
OER
R/WR
A0L
A10L Address
Decoder A10R
A0R
I/O7R
I/O0R
BUSYR
INTR
I/O7L
I/O0L
BUSYL
•
•
•
•
•
••
•
•
•
•
•
•
•
•
•
•
•
R/WL
CEL
OEL
R/WR
CER
OER
[1]
[2]
[1]
[2]
CG5982AF 2K x 8 Automotive Dual-port Static RAM
CG5982AF
Document #: 38-06067 Rev. *C Page 2 of 12
Pin Configurations
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .............................. ...–65°C to +150°C
Ambient Temperature with
Power Applied........... ... ... .............. ... ... ........–55°C to +125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24)............ ... .............. ... ...........–0.5V to +7.0V
DC Voltage Appli ed to Outputs
in High-Z State............. ... ... .............. ... ...........–0.5V to +7.0V
DC Input Voltage ...... .............. ... ... .............. ... .–3.5V to +7.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current............... ... ... ............................ ... > 200 mA
Selection Guide
CG5982AF Unit
Maximum Access T i me 55 ns
Maximum Operating Current 120 mA
Maximum Standby Current 45 mA
1
VCC
Top View
PLCC
OER
A0R
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2 52 51 50 49 48 47
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NC
I/O7R
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4L
5L
6L
7L
0R
1R
2R
3R
4R
5R
6R
NC
GND
OE
BUSY
INT
A
R/W
CE
R/W
BUSY
INT
0L
L
L
L
L
L
CER
R
R
R
CG5982AF
A
10L
A10R
Operating Range
Range Ambient
Temperature VCC
Automotive[3] –40°C to +115°C 5V ± 10%
Electrical Characteristics Over the Operating Range[4]
Parameter Description Test Conditions
CG5982AF
UnitMin. Max.
VOH Output HIGH Voltage VCC = Min., I OH = –4.0 mA 2.4 V
VOL Output LOW V oltage IOL = 4.0 mA 0.4 V
IOL = 16.0 mA[5] 0.5
VIH Input HIGH Voltage 2.2 V
VIL Input LOW Voltage 0.8 V
IIX Input Load Current GND < VI < VCC –5 +5 µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –5 +5 µA
IOS Output Short–Circuit Current[6] VCC = Max., VOUT = GND –350 mA
Note:
3. TA is the “instant on” case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. BUSY and INT pins only.
6. Duration of the short circuit should not exceed 30 seconds.
CG5982AF
Document #: 38-06067 Rev. *C Page 3 of 12
ICC VCC Operating Supply Current CE = VIL, Outputs Open,
f = fMAX[7] Auto 120 mA
ISB1 Standby Current Both Ports,
TTL Inputs CEL and CER > VIH,
f = fMAX[7] Auto 45 mA
ISB2 Standby Current One Port,
TTL Inputs CEL or CER > VIH, Active Port
Outputs Open, f = fMAX[7] Auto 90 mA
ISB3 Standby Current Both Ports,
CMOS Inputs Both Ports CEL and CER >
VCC – 0.2V, VIN > VCC – 0.2V
or VIN < 0.2V, f = 0
Auto 15 mA
ISB4 Standby Current One Port,
CMOS Inputs One Port CEL or CER > VCC
– 0.2V, VIN > VCC – 0.2V or
VIN < 0.2V, Active Port
Outputs Open, f = fMAX[7]
Auto 85 mA
Capacitance[8]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 15 pF
COUT Output Capacitance 10 pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[4, 9]
Parameter Description
CG5982AF
UnitMin. Max.
Read Cycle
tRC Read Cycle Time 55 ns
tAA Address to Data Valid[10] 55 ns
tOHA Data Hold from Address Change 0ns
tACE CE LOW to Data Valid[10] 55 ns
tDOE OE LOW to Data Valid[10] 25 ns
tLZOE OE LOW to Low-Z[8, 11] 3ns
Notes:
7. At f = fMAX, address and data inp uts are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V.
8. This parame ter is guaranteed but not tested.
9. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of the specified
IOL/IOH, and 30-pF load capacitance.
10.AC test conditions use VOH = 1.6V and VOL = 1.4V.
11.At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
Electrical Characteristics Over the Operating Range[4] (continued)
Parameter Description Test Conditions
CG5982AF
UnitMin. Max.
BUSY Output Load
3.0V
5V
OUTPUT
R1 893Ω
R2
347Ω
30 pF
Including
Jig and
Scope
GND 90% 90%
10%
<5ns <5
ns
5V
OUTPUT
R1 893Ω
R2
347Ω
5 pF
(a) (b)
OUTPUT 1.4V
Equivalent to: THÉVENIN EQUIVALENT
5V
281Ω
30 pF
BUSY
OR
INT
(CY7C132/CY7C136 Only)
10%
All input pulses
250Ω
Including
Jig and
Scope
CG5982AF
Document #: 38-06067 Rev. *C Page 4 of 12
tHZOE OE HIGH to High-Z[8, 11, 12] 25 ns
tHZCE CE HIGH to High-Z[8, 11, 12] 25 ns
tPU CE LOW to Power-Up[8] 0ns
tPD CE HIGH to Power-Down[8] 35 ns
Write Cycle[13]
tWC Write Cycle Time 55 ns
tSCE CE LOW to W rite End 40 ns
tAW Address Set-up to Write End 40 ns
tHA Address Hold from Write End 2ns
tSA Address Set-up to Write Start 0ns
tPWE R/W Pulse Width 30 ns
tSD Data Set-up to Write End 20 ns
tHD Data Hold from Write End 0ns
tHZWE R/W LOW to High-Z [8] 25 ns
tLZWE R/W HIGH to Low-Z [8] 0ns
Busy/Interru pt Timing
tBLA BUSY LOW from Address Match 30 ns
tBHA BUSY HIGH from Address Mismatch[14] 30 ns
tBLC BUSY LOW from CE LOW 30 ns
tBHC BUSY HIGH from CE HIGH[14] 30 ns
tPS Port Set-up for Priority 5ns
tWB R/W LOW after BUSY LOW 0ns
tWH R/W HIGH after BUSY HIGH 35 ns
tBDD BUSY HIGH to Valid Data 45 ns
tDDD Write Data Valid to Read Data Valid Note 15 ns
tWDD Write Pulse to Data Delay Note 15 ns
Interrupt Timing[15]
tWINS R/W to INTERRUPT Set Time 45 ns
tEINS CE to INTERRUPT Set Time 45 ns
tINS Address to INTERRUPT Set Time 45 ns
tOINR OE to INTERRUPT Rese t Time[14] 45 ns
tEINR CE to INTERRUPT Reset Time[14] 45 ns
tINR Address to INTERRUPT Reset Time[14] 45 ns
Notes:
12.tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5 pF, as in (b) of AC Test Loads. T r ansition is measured ± 500 mV fro m steady-state voltage.
13.The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal tha t terminates the write.
14.These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
15.A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Switching Characteristics Over the Operating Range[4, 9] (continued)
Parameter Description
CG5982AF
UnitMin. Max.
CG5982AF
Document #: 38-06067 Rev. *C Page 5 of 12
Switching Waveforms
Read Cycle No. 1 (Either Port-Address Access)[16, 17]
Read Cycle No. 2 (Either Port-CE/OE)[16, 18]
Read Cycle No. 3 (Read with BUSY Master)
Notes:
16.R/W is HIGH for read cycle.
17.Device is continuously selected, CE = VIL and OE = VIL.
18.Address valid prior to or coincident with CE t ransition LOW.
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
tACE
tLZOE tDOE tHZOE
tHZCE
DATA VALID
DATA OUT
CE
OE
tLZCE
tPU
ICC
ISB
tPD
tBHA
tBDD
VALID
tDDD
tWDD
ADDRESS MATCH
ADDRESS MATCH
R/WR
ADDRESSR
DINR
ADDRESSL
BUSYL
DOUTL
tPS
tBLA
tRC
tPWE
VALID
CG5982AF
Document #: 38-06067 Rev. *C Page 6 of 12
Write Cycle No.1 (OE Three-States Data I/Os—Either Port)[13, 19]
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[13, 20]
Notes:
19.If OE is LOW during a R/W control led write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/ O pins to enter high impedance
and for data to be placed on the bus for the required t SD.
20.If the CE LOW transition occurs simultaneou sly with or aft er the R/W LOW transition, the outputs remain in a high-impedance state.
Switching Waveforms (continued)
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA tPWE
tHD
tSD
tHA
tHZOE
CE
R/W
ADDRESS
OE
DOUT
DATAIN
tAW
tWC
tSCE
tSA tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
CE
R/W
ADDRESS
DOUT
DATAIN
tLZWE
DATAVALID
CG5982AF
Document #: 38-06067 Rev. *C Page 7 of 12
Busy Timing Diagram No. 1 (CE Arbitration)
Busy Timing Diagram No. 2 (Address Arbitration)
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
BUSYL
CER
CEL
ADDRESSL,R
BUSYR
CEL
CER
ADDRESSL,R
CEL Valid First:
CER Valid First:
Left Address Valid First:
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRCor tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSYL
tRCor tWC
tBLA tBHA
ADDRESSR
Right Address Valid First:
CG5982AF
Document #: 38-06067 Rev. *C Page 8 of 12
Busy Timing Diagram No. 3 (Write with BUSY, Slave)
Interrupt Timing Diagrams[16]
Left Side Sets INTR:
Right Side Clears INTR:
Right Side Sets INTL:
Switching Waveforms (continued)
tPWE
tWB tWH
BUSY
R/W
CE
WRITE 7FF
tINS
ADDRESSL
R/WL
tWC
tEINS
CELtHA
tSA tWINS
INTR
READ 7FF
tRC
tEINR
tHA tINR
tOINR
ADDRESSR
CER
R/WR
INTR
OER
WRITE 7FE
tINS
ADDRESSR
R/WR
tWC
tEINS
CERtHA
tSA tWINS
INTL
CG5982AF
Document #: 38-06067 Rev. *C Page 9 of 12
Left Side Clears INTL:
Interrupt Timing Diagrams[16] (continued)
READ 7FE
tEINR
tHA tINR
tOINR
ADDRESSL
CEL
R/WL
INTL
OEL
tRC
CG5982AF
Document #: 38-06067 Rev. *C Page 10 of 12
Typical DC and AC Characteristics
1.4
1.0
0.4
4.0 4.5 5.0 5.5 6.0 –55 25 125
1.2
1.0
120
100
80
60
40
20
01.02.03.04.0
OUTPUT SOURCE CURRENT (mA)
Supply Voltage (V)
Normalized Supply Current
vs. Supply Voltage Normalized Supply Current
vs. Ambient Temperature
Ambient Temperature (°C) Output Voltage (V)
Output Source Current
vs. Output Voltage
0.0
0.8 0.8
0.6
0.6
NORMALIZED ICC, ISB
VCC = 5.0V
VIN = 5.0V TA = 25°C
0
ICC
1.6
1.4
1.2
1.0
0.8
–55 125
NORMALIZED tAA
Normalized Access Time
vs. Ambient Temperature
1.4
1.3
1.2
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED tAA
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
Output Sink Current
vs. Output Voltage
0.6
0.8
1.25
1.0
0.75
10 40
NORMALIZED ICC
0.50
Normalized ICC vs. Cycle Time
Cycle Frequency (MHz)
3.0
2.5
2.0
1.5
0.5
0 1.0 2.0 3.0 5.0
NORMALIZED tPC
25.0
30.0
20.0
10.0
5.0
0 200 400 600 800
DELTA tAA (ns)
0
15.0
0.0
Supply Voltage (V)
Typical Power-on Current
vs. Supply Voltage
Capacitance (pF)
Typical Access Time Change
vs. Output Loading
4.0 1000
1.0
20 30
0.2
0.6
1.2
ISB3
NORMALIZED ICC, ISB
0.2
0.4
25
1.1
VCC =4.5V
TA=25°C
Normalized Access Time
vs. Supply Voltage
Supply Voltage (V) Ambient Temperature (°C) Output Voltage (V)
ICC
ISB3
VCC = 5.0V
TA = 25°C VCC = 5.0V
VCC = 5.0V
TA = 25°C
VCC = 5.0V
TA = 25°C
VIN = 5.0V
Ordering Information
Speed ( ns) Ordering Code Package
Name Package Type Operating
Range
55 CG5982AF J69 52-lead Plastic Leaded Chip Carrier Automotive
CG5982AF
Document #: 38-06067 Rev. *C Page 11 of 12
© Cypress Semi con duct or Cor po rati on , 20 05 . The information con t a in ed he re i n is su bject to change wit hout notice. Cypr ess S em icon duct or Corpo ration assu mes no resp onsib ility for th e us e
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furthermore , Cypress does not authorize i ts
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Package Diagrams
All product and company names mentioned in this document are the trademarks of their respective holders.
51-85004-*A
52-lead Plastic Leaded Chip Ca rrier J69
CG5982AF
Document #: 38-06067 Rev. *C Page 12 of 12
Document History Page
Document Title: CG5982AF 2K x 8 Automotive Dual-port Static RAM
Document Number: 38-06067
REV. ECN Issue
Date Orig. of
Change Description of Cha nge
** 11 9657 10/10/02 NIM Customize d data sheet to mee t specia l requirements for CG5982AF;
automotive temperature –40°C to +115°C; base part in CY7C136
*A 1214 88 12/09/02 OOR Fixed Typo- change d 5 mA to 5 µA (p.2)
*B 393195 SEE ECN KGH Included the automotive temperature operation range to the Features
section
Removed the micron CMOS size and the 52-pin PLCC references from the
Features section
Added Automotive to the title description
*C 421244 See ECN ODC Add to external web.
