LTC2325IUKG-14#PBF - ANALOG DEVICES

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

Typical applicaTion

FeaTures DescripTion

Quad, 14-Bit + Sign, 5Msps/Ch

Simultaneous Sampling ADC

The LTC

2325-14 is a low noise, high speed quad 14-bit

+ sign successive approximation register (SAR) ADC with

differential inputs and wide input common mode range.

Operating from a single 3.3V or 5V supply, the LTC2325-14

has an 8VP-P differential input range, making it ideal for

applications which require a wide dynamic range with high

common mode rejection. The LTC2325-14 achieves ±1LSB

INL typical, no missing codes at 14 bits and 81dB SNR.

The LTC2325-14 has an onboard low drift (20ppm/°C max)

2.048V or 4.096V temperature-compensated reference.

The LTC2325-14 also has a high speed SPI-compatible

serial interface that supports CMOS or LVDS. The fast

5Msps per channel throughput with one cycle latency

makes the LTC2325-14 ideally suited for a wide variety

of high speed applications. The LTC2325-14 dissipates

only 45mW per channel and offers nap and sleep modes

to reduce the power consumption to 26μW for further

power savings during inactive periods.

32k Point FFT fSMPL = 5Msps,

fIN = 2.2MHz

applicaTions

n 5Msps/Ch Throughput Rate

n Four Simultaneously Sampling Channels

n Guaranteed 14-Bit, No Missing Codes

n 8VP-P Differential Inputs with Wide Input

Common Mode Range

n 81dB SNR (Typ) at fIN = 2.2MHz

n –88dB THD (Typ) at fIN = 2.2MHz

n Guaranteed Operation to 125°C

n Single 3.3V or 5V Supply

n Low Drift (20ppm/°C Max) 2.048V or 4.096V

Internal Reference

n 1.8V to 2.5V I/O Voltages

n CMOS or LVDS SPI-Compatible Serial I/O

n Power Dissipation 45mW/Ch (Typ)

n Small 52-Lead (7mm × 8mm) QFN Package

n High Speed Data Acquisition Systems

n Communications

n Optical Networking

n Multiphase Motor Control

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

BIPOLAR UNIPOLAR

ARBITRARY

TRUE DIFFERENTIAL INPUTS

NO CONFIGURATION REQUIRED

IN+, IN–

DIFFERENTIAL

0V 0V

VDD VDD

0V 0V

FOUR SIMULTANEOUS

SAMPLING CHANNELS

1µF

10µF

1µF

AIN1+

AIN1–

AIN2+

AIN2–

S/H

AIN3+

AIN3–

AIN4+

AIN4–

REF

GND

REFOUT1

1.8V TO 2.5V

3.3V OR 5V

CMOS/LVDS

SDR/DDR

REFBUFEN

SDO1

SDO2

SDO3

SDO4

CLKOUT

SCK

CNV

SAMPLE

CLOCK

REFOUT2

REFOUT3

REFOUT4

LTC2325-14

232514 TA01a

S/H

14-BIT

+SIGN

SAR ADC

14-BIT

+SIGN

SAR ADC

14-BIT

+SIGN

SAR ADC

14-BIT

+SIGN

SAR ADC

SNR = 81.3dB

THD = –87.2dB

SINAD = 80.5dB

SFDR = 90.3dB

FREQUENCY (MHz)

0.5

1.5

2.5

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

232514 TA01b

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

pin conFiguraTionabsoluTe MaxiMuM raTings

Supply Voltage (VDD) ..................................................6V

Supply Voltage (OVDD) ................................................3V

Analog Input Voltage

AIN+, AIN– (Note 3) ................... –0.3V to (VDD + 0.3V)

REFOUT1,2,3,4........................ .–0.3V to (VDD + 0.3V)

CNV........................................ –0.3V to (OVDD + 0.3V)

Digital Input Voltage

(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)

Digital Output Voltage

(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)

Operating Temperature Range

LTC2325C ................................................ 0°C to 70°C

LTC2325I .............................................–40°C to 85°C

LTC2325H .......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

(Notes 1, 2)

1615 17 18 19

TOP VIEW

GND

UKG PACKAGE

52-LEAD (7mm × 8mm) PLASTIC QFN

20 21 22 23 24 25 26

5152 50 49 48 47 46 45 44 43 42 41

1AIN4–

AIN4+

GND

AIN3–

AIN3+

REFOUT3

GND

REF

REFOUT2

AIN2–

AIN2+

GND

AIN1–

AIN1+

DNC/SDOD–

SDO4/SDOD+

GND

OVDD

DNC/SDOC–

SDO3/SDOC+

CLKOUTEN/CLKOUT–

CLKOUT/CLKOUT+

GND

OVDD

DNC/SDOB–

SDO2/SDOB+

DNC/SDOA–

SDO1/SDOA+

VDD

GND

REFOUT4

VDD

REFBUFEN

DNC/SCK–

SCK/SCK+

VDD

GND

VDD

REFOUT1

SDR/DDR

CNV

CMOS/LVDS

GND

TJMAX = 150°C, θJA = 31°C/W

EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2325CUKG-14#PBF LTC2325CUKG-14#TRPBF LTC2325UKG-14 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2325IUKG-14#PBF LTC2325IUKG-14#TRPBF LTC2325UKG-14 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

LTC2325HUKG-14#PBF LTC2325HUKG-14#TRPBF LTC2325UKG-14 52-Lead (7mm × 8mm) Plastic QFN –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

http://www.linear.com/product/LTC2325-14#orderinfo

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C (Note 4).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN+Absolute Input Range (AIN+ to AIN–) (Note 5) l0 VDD V

VIN–Absolute Input Range (AIN+ to AIN–) (Note 5) l0 VDD V

VIN+ – VIN–Input Differential Voltage Range VIN = VIN+ – VIN–l–REFOUT1,2,3,4 REFOUT1,2,3,4 V

VCM Common Mode Input Range VCM = (VIN+ – VIN–)/2 l0 VDD V

IIN Analog Input DC Leakage Current l–1 1 μA

CIN Analog Input Capacitance 10 pF

CMRR Input Common Mode Rejection Ratio fIN = 2.2MHz 102 dB

VIHCNV CNV High Level Input Voltage l1.5 V

VILCNV CNV Low Level Input Voltage l0.5 V

IINCNV CNV Input Current l–10 10 μA

converTer characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution l14 Bits

No Missing Codes l14 Bits

Transition Noise 0.4 LSBRMS

INL Integral Linearity Error (Note 6) l–3 ±1 3 LSB

DNL Differential Linearity Error l–0.99 ±0.4 0.99 LSB

BZE Bipolar Zero-Scale Error (Note 7) l–2 0 2 LSB

Bipolar Zero-Scale Error Drift 0.01 LSB/°C

FSE Bipolar Full-Scale Error VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded) (Note 7) l–7 7 LSB

Bipolar Full-Scale Error Drift VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded) 15 ppm/°C

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C (Note 4).

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

DynaMic accuracy

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SINAD Signal-to-(Noise + Distortion) Ratio fIN = 2.2MHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference l76 81 dB

fIN = 2.2MHz, VREFOUT1,2,3,4 = 5V, External Reference 81 dB

SNR Signal-to-Noise Ratio fIN = 2.2MHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference l76.5 82 dB

fIN = 2.2MHz, VREFOUT1,2,3,4 = 5V, External Reference 82.5 dB

THD Total Harmonic Distortion fIN = 2.2MHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference l–90 –78 dB

fIN = 2.2MHz, VREFOUT1,2,3,4 = 5V, External Reference –91 dB

SFDR Spurious Free Dynamic Range fIN = 2.2MHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference l78 93 dB

fIN = 2.2MHz, VREFOUT1,2,3,4 = 5V, External Reference 93 dB

–3dB Input Bandwidth 95 MHz

Aperture Delay 500 ps

Aperture Delay Matching 500 ps

Aperture Jitter 1 psRMS

Transient Response Full-Scale Step 30 ns

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA = 25°C and AIN = –1dBFS (Notes 4, 8).

inTernal reFerence characTerisTics

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREFOUT1,2,3,4 Internal Reference Output Voltage 4.75V < VDD < 5.25V

3.13V < VDD < 3.47V

4.078

2.034

4.096

2.048

4.115

2.064

VREF Temperature Coefficient (Note 14) l3 20 ppm/°C

REFOUT1,2,3,4 Output Impedance 0.25 Ω

VREFOUT1,2,3,4 Line Regulation 4.75V < VDD < 5.25V 0.3 mV/V

IREFOUT1,2,3,4 External Reference Current REFBUFEN = 0V

REFOUT1,2,3,4 = 4.096V

REFOUT1,2,3,4 = 2.048V

(Notes 9, 10)

500

300

μA

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

DigiTal inpuTs anD DigiTal ouTpuTs

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CMOS Digital Inputs and Outputs CMOS/LVDS = GND

VIH High Level Input Voltage l0.8 • OVDD V

VIL Low Level Input Voltage l0.2 • OVDD V

IIN Digital Input Current VIN = 0V to OVDD l–10 10 μA

CIN Digital Input Capacitance l5 pF

VOH High Level Output Voltage IO = –500μA lOVDD – 0.2 V

VOL Low Level Output Voltage IO = 500μA l0.2 V

IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 μA

ISOURCE Output Source Current VOUT = 0V l–10 mA

ISINK Output Sink Current VOUT = OVDD l10 mA

LVDS Digital Inputs and Outputs CMOS/LVDS = OVDD

VID LVDS Differential Input Voltage 100Ω Differential Termination

OVDD = 2.5V

l240 600 mV

VIS LVDS Common Mode Input Voltage 100Ω Differential Termination

OVDD = 2.5V

l1 1.45 V

VOD LVDS Differential Output Voltage 100Ω Differential Termination

OVDD = 2.5V

l220 350 600 mV

VOS LVDS Common Mode Output Voltage 100Ω Differential Termination

OVDD = 2.5V

l0.85 1.2 1.4 V

VOD_LP Low Power LVDS Differential Output

Voltage

100Ω Differential Termination

OVDD = 2.5V

l100 200 350 mV

VOS_LP Low Power LVDS Common Mode Output

Voltage

100Ω Differential Termination

OVDD = 2.5V

l0.85 1.2 1.4 V

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSMPL Maximum Sampling Frequency l5 Msps

tCYC Time Between Conversions (Note 11) tCYC = tCNVH + tCONV l0.2 1000 µs

tCONV Conversion Time l170 ns

tCNVH CNV High Time l30 ns

tACQUISITION Sampling Aperture (Note 11) tACQUISITION = tCYC – tCONV 28 ns

tWAKE REFOUT1,2,3,4 Wake-Up Time CREFOUT1,2,3,4 = 10µF 50 ms

CMOS I/O Mode, SDR: CMOS/LVDS = GND, SDR/ DDR = GND

tSCK SCK Period (Note 13) l9.1 ns

tSCKH SCK High Time l4.1 ns

tSCKL SCK Low Time l4.1 ns

tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓CL = 5pF (Note 12) l0 1.5 ns

tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l2 4.5 ns

power requireMenTs

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C (Note 4).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD Supply Voltage 5V Operation

3.3V Operation

4.75

3.13

5.25

3.47

IVDD Supply Current 5Msps Sample Rate (IN+ = IN– = 0V) l31 44.5 mA

CMOS I/O Mode: CMOS/LVDS = GND

OVDD Supply Voltage l1.71 2.63 V

IOVDD Supply Current 5Msps Sample Rate (CL = 5pF) l4.4 15.5 mA

INAP Nap Mode Current Conversion Done (IVDD)l5.3 6.4 mA

ISLEEP Sleep Mode Current Sleep Mode (IVDD+ IOVDD)l20 90 µA

PD_3.3V Power Dissipation VDD = 3.3V, 5Msps Sample Rate

Nap Mode

Sleep Mode

102

181

21.1

288

µW

PD_5V Power Dissipation VDD = 5V, 5Msps Sample Rate

Nap Mode

Sleep Mode

162

261

424

µW

LVDS I/O Mode: CMOS/LVDS = OVDD, OVDD = 2.5V

OVDD Supply Voltage l2.37 2.63 V

IOVDD Supply Current 5Msps Sample Rate (CL = 5pF, RL = 100Ω) l26 32 mA

INAP Nap Mode Current Conversion Done (IVDD)l5.3 6.4 mA

ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD)l20 90 µA

PD_3.3V Power Dissipation VDD = 3.3V, 5Msps Sample Rate

Nap Mode

Sleep Mode

151

218

58.6

288

µW

PD_5V Power Dissipation VDD = 5V, 5Msps Sample Rate

Nap Mode

Sleep Mode

214

303

69.2

424

µW

aDc TiMing characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C (Note 4).

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground, or above VDD or

OVDD, they will be clamped by internal diodes. This product can handle input

currents up to 100mA below ground, or above VDD or OVDD, without latch-up.

Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 = 4.096V, fSMPL = 5MHz.

Note 5: Recommended operating conditions.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB

when the output code flickers between 000 0000 0000 0000 and 111

1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS

untrimmed deviation from ideal first and last code transitions and includes

the effect of offset error.

Note 8: All specifications in dB are referred to a full-scale ±4.096V input

with REF = 4.096V.

Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer

must be turned off by setting REFBUFEN = 0V.

Note 10: fSMPL = 5MHz, IREFOUT1,2,3,4 varies proportionally with sample rate.

Note 11: Guaranteed by design, not subject to test.

Note 12: Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V.

Note 13: tSCK of 9.1ns allows a shift clock frequency up to 105MHz for

rising edge capture.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 15: CNV is driven from a low jitter digital source, typically at OVDD

logic levels.

aDc TiMing characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C (Note 4).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tDCNVSDOZ Bus Relinquish Time After CNV↑(Note 11) l3 ns

tDCNVSDOV SDO Valid Delay from CNV↓(Note 11) l3 ns

tDSCKHCNVH SCK Delay Time to CNV↑(Note 11) l0 ns

CMOS I/O Mode, DDR: CMOS/LVDS = GND, SDR/ DDR = OVDD

tSCK SCK Period l18.2 ns

tSCKH SCK High Time l8.2 ns

tSCKL SCK Low Time l8.2 ns

tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓CL = 5pF (Note 12) l0 1.5 ns

tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l2 4.5 ns

tDCNVSDOZ Bus Relinquish Time After CNV↑(Note 11) l3 ns

tDCNVSDOV SDO Valid Delay from CNV↓(Note 11) l3 ns

tDSCKHCNVH SCK Delay Time to CNV↑(Note 11) l0 ns

LVDS I/O Mode, SDR: CMOS/LVDS = OVDD, SDR/DDR = GND

tSCK SCK Period l9.1 ns

tSCKH SCK High Time l4.1 ns

tSCKL SCK Low Time l4.1 ns

tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓CL = 5pF (Note 12) l0 1.5 ns

tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l2 4 ns

tDSCKHCNVH SCK Delay Time to CNV↑(Note 11) l0 ns

LVDS I/O Mode, DDR: CMOS/LVDS = OVDD, SDR/DDR = OVDD = 2.5V

tSCK SCK Period l18.2 ns

tSCKH SCK High Time l8.2 ns

tSCKL SCK Low Time l8.2 ns

tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓CL = 5pF l0 1.5 ns

tDSCKCLKOUT SCK to CLKOUT Delay l2 4 ns

tDSCKHCNVH SCK Delay Time to CNV↑(Note 11) l0 ns

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

Figure1. Voltage Levels for Timing Specifications

0.8 • OVDD

0.2 • OVDD

50% 50%

232514 F01

0.2 • OVDD

0.8 • OVDD

0.2 • OVDD

0.8 • OVDD

tDELAY

tWIDTH

tDELAY

aDc TiMing characTerisTics

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

Typical perForMance characTerisTics

THD, Harmonics vs Input Common

Mode

SNR, SINAD vs Reference Voltage,

fIN = 2.2MHz

32k Point FFT, IMD, fSMPL = 5Msps,

AIN+ = 1.2MHz, AIN– = 2.2MHz

32k Point FFT, fSMPL = 5Msps,

fIN = 2.2MHz

SNR, SINAD vs Input Frequency

(1kHz to 2.2MHz)

THD, Harmonics vs Input

Frequency (1kHz to 2.2MHz)

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code DC Histogram

TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4

= 4.096V, fSMPL = 5Msps, unless otherwise noted.

OUTPUT CODE

–16384

–8192

8192

16384

–2

–1

INL ERROR (LSB)

232514 G01

OUTPUT CODE

–16384

–8192

8192

16384

–1.0

–0.5

0.5

1.0

DNL ERROR (LSB)

232514 G02

σ = 0.38

CODE

–3

–2

–1

4000

8000

12000

16000

20000

24000

28000

32000

36000

40000

COUNTS

232414 G03

SNR = 81.3dB

THD = –87.2dB

SINAD = 80.5dB

SFDR = 90.3dB

FREQUENCY (MHz)

0.5

1.5

2.5

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

232514 G04

SNR

SINAD

FREQUENCY (MHz)

0.5

1.5

2.5

80.0

80.2

80.4

80.6

80.8

81.0

81.2

81.4

81.6

81.8

82.0

SNR, SINAD LEVEL (dBFS)

232514 G05

THD

HD3

HD2

FREQUENCY (MHz)

0.5

1.5

2.5

–120

–116

–112

–108

–104

–100

–96

–92

–88

–84

–80

THD, HARMONICS LEVEL (dBFS)

232514 G06

THD

HD3

HD2

f = 2.2MHz

INPUT COMMON MODE (V)

1.5

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

–110

–107

–104

–101

–98

–95

–92

–89

–86

–83

–80

THD, HARMONICS LEVEL (dBFS)

232514 G07

SNR

SINAD

f = 2.2MHz

REFOUT

(V)

0.5

1.5

2.5

3.5

4.5

SNR, SINAD LEVEL (dBFS)

232514 G08

THD = 86dB

= 1MHz, 4VP-P

FREQUENCY (MHz)

0.5

1.5

2.5

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

232514 G09

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

Typical perForMance characTerisTics

Step Response

(Fine Settling)

External Reference Supply

Current vs Sample Frequency REF Output vs Temperature

Offset Error vs Temperature

Supply Current

vs Sample Frequency

OVDD Current vs SCK Frequency,

CLOAD = 10pF

CMRR vs Input Frequency Crosstalk vs Input Frequency

Step Response

(Large Signal Settling)

TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4

= 4.096V, fSMPL = 5Msps, unless otherwise noted.

= 4VP-P

FREQUENCY (kHz)

500

1000

1500

2000

2500

104

112

120

CMRR (dB)

232514 G10

FREQUENCY (MHz)

0.5

1.5

2.5

–125

–123

–121

–119

–117

–115

–113

–111

–109

–107

–105

CROSSTALK (dB)

232514 G11

4.096V RANGE

IN+ = 5MHz SQUARE WAVE

IN– = 0V

SETTLING TIME (ns)

–20

–10

–4096

4096

8192

12288

16384

OUTPUT CODE (LSB)

232514 G12

4.096V RANGE

IN+ = 5MHz

SQUARE WAVE

IN– = 0V

SETTLING TIME (ns)

–20

–10

–50

–25

DEVIATION FROM FINAL VALUE (LSB)

232514 G13

REFOUT1,2,3,4

= 4.096V

REFOUT1,2,3,4

= 2.048V

REFBUFEN = 0V

(EXT REF BUF

OVERDRIVING REF BUF)

SAMPLE FREQUENCY (Msps)

100

200

300

400

500

600

700

SUPPLY CURRENT (uA)

232514 G14

= 3.3V

= 5V

TEMPERATURE (°C)

–55

–35

–15

105

125

–3.00

–2.50

–2.00

–1.50

–1.00

–0.50

0.50

1.00

REF OUTPUT ERROR (mV)

232514 G15

TEMPERATURE (°C)

–55

–35

–15

105

125

–1.0

–0.5

0.5

1.0

LSB

232514 G16

= 5V

= 3.3V

SAMPLE FREQUENCY (Msps)

SUPPLY CURRENT (mA)

232514 G17

LVDS

CMOS(2.5V)

LOW POWER LVDS

CMOS(1.8V)

FULL SCALE SINUSOIDAL INPUT

SCK FREQUENCY (MHz)

110

CURRENT CMOS (mA)

CURRENT LVDS (mA)

232514 G18

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

pin FuncTions

PINS THAT ARE THE SAME FOR ALL DIGITAL I/O MODES

AIN4+, AIN4– (Pins 2, 1): Analog Differential Input Pins.

Full-scale range (AIN4+ – AIN4–) is ±REFOUT4 voltage.

These pins can be driven from VDD to GND.

GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground.

These pins and exposed pad (Pin 53) must be tied directly

to a solid ground plane.

AIN3+, AIN3– (Pins 5, 4): Analog Differential Input Pins.

Full-scale range (AIN3+ – AIN3–) is ±REFOUT3 voltage.

These pins can be driven from VDD to GND.

REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

REF (Pin 8): Common 4.096V reference output. Decouple

to GND with a 1μF low ESR ceramic capacitor. May be

overdriven with a single external reference to establish a

common reference for ADC cores 1 through 4.

REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

AIN2+, AIN2– (Pins 11, 10): Analog Differential Input Pins.

Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage.

These pins can be driven from VDD to GND.

AIN1+, AIN1– (Pins 14, 13): Analog Differential Input Pins.

Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage.

These pins can be driven from VDD to GND.

VDD (Pins 15, 21, 44, 52): Power Supply. Bypass VDD to

GND with a 10µF ceramic capacitor and a 0.1µF ceramic

capacitor close to the part. The VDD pins should be shorted

together and driven from the same supply.

REFOUT1 (Pin 22): Reference Buffer 1 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

SDR/DDR (Pin 23): Double Data Rate Input. Controls the

frequency of SCK and CLKOUT. Tie to GND for the falling

edge of SCK to shift each serial data output (Single Data

Rate, SDR). Tie to OVDD to shift serial data output on each

edge of SCK (Double Data Rate, DDR). CLKOUT will be a

delayed version of SCK for both pin states.

CNV (Pin 24): Convert Input. This pin, when high, defines

the acquisition phase. When this pin is driven low, the

conversion phase is initiated and output data is clocked

out. This input must be driven at OVDD levels with a low

jitter pulse. This pin is unaffected by the CMOS/LVDS pin.

CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin

to enable CMOS mode, tie to OVDD to enable LVDS mode.

Float this pin to enable low power LVDS mode.

OVDD (Pins 31, 37): I/O Interface Digital Power. The range

of OVDD is 1.71V to 2.63V. This supply is nominally set

to the same supply as the host interface (CMOS: 1.8V or

2.5V, LVDS: 2.5V). Bypass OVDD to GND (Pins 32 and 38)

with 0.1µF capacitors.

REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie

to VDD when using the internal reference. Tie to ground

to disable the internal REFOUT1–4 buffers for use with

external voltage references. This pin has a 500k internal

pull-up to VDD.

REFOUT4 (Pin 45): Reference Buffer 4 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

Exposed Pad (Pin 53): Ground. Solder this pad to ground.

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

pin FuncTions

CMOS DATA OUTPUT OPTION (CMOS/LVDS = LOW)

SDO1 (Pin 27): CMOS Serial Data Output for ADC Channel

1. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 15-bit conversion

data to be read from SDO1 in SDR mode, 8 SCK edges

in DDR mode.

SDO2 (Pin 29): CMOS Serial Data Output for ADC Channel

2. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 15-bit conversion

data to be read from SDO2 in SDR mode, 8 SCK edges

in DDR mode.

SDO3 (Pin 35): CMOS Serial Data Output for ADC Channel

3. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 15-bit conversion

data to be read from SDO3 in SDR mode, 8 SCK edges

in DDR mode.

SDO4 (Pin 39): CMOS Serial Data Output for ADC Channel

4. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 15-bit conversion

data to be read from SDO4 in SDR mode, 8 SCK edges

in DDR mode.

CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT

provides a skew-matched clock to latch the SDO output

at the receiver (FPGA). The logic level is determined by

OVDD. This pin echoes the input at SCK with a small delay.

CLKOUTEN (Pin 34): CLKOUT can be disabled by tying

Pin 34 to OVDD for a small power savings. If CLKOUT is

used, ground this pin.

SCK (Pin 41): Serial Data Clock Input. The falling edge

of this clock shifts the conversion result MSB first onto

the SDO pins in SDR mode (DDR = LOW). In DDR mode

(SDR/DDR = HIGH) each edge of this clock shifts the

conversion result MSB first onto the SDO pins. The logic

level is determined by OVDD.

DNC (Pins 28, 30, 36, 40, 42): In CMOS mode, do not

connect this pin.

LVDS DATA OUTPUT OPTION (CMOS/LVDS = HIGH OR

FLOAT)

SDOA+, SDOA– (Pins 27, 28): LVDS Serial Data Output

for ADC Channel 1. The conversion result is shifted CH1

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 16 SCK edges are required

for 15-bit conversion data to be read from SDOA in SDR

mode, 8 SCK edges in DDR mode. Terminate with a 100Ω

resistor at the receiver (FPGA).

SDOB+, SDOB– (Pins 29, 30): LVDS Serial Data Output

for ADC Channel 2. The conversion result is shifted CH2

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 16 SCK edges are required

for 15-bit conversion data to be read from SDOB in SDR

mode, 8 SCK edges in DDR mode. Terminate with a 100Ω

resistor at the receiver (FPGA).

CLKOUT+, CLKOUT– (Pins 33, 34): Serial Data Clock Output.

CLKOUT provides a skew-matched clock to latch the SDO

output at the receiver. These pins echo the input at SCK with

a small delay. These pins must be differentially terminated

by an external 100Ω resistor at the receiver(FPGA).

SDOC+, SDOC– (Pins 35, 36): LVDS Serial Data Output

for ADC channel 3. The conversion result is shifted CH3

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 16 SCK edges are required

for 15-bit conversion data to be read from SDOA in SDR

mode, 8 SCK edges in DDR mode. Terminate with a 100Ω

resistor at the receiver (FPGA).

SDOD+, SDOD– (Pins 39, 40): LVDS Serial Data Output

for ADC Channel 4. The conversion result is shifted CH4

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 16 SCK edges are required

for 15-bit conversion data to be read from SDOA in SDR

mode, 8 SCK edges in DDR mode. Terminate with a 100Ω

resistor at the receiver (FPGA).

SCK+, SCK– (Pins 41, 42): Serial Data Clock Input. The

falling edge of this clock shifts the conversion result MSB

first onto the SDO pins in SDR mode (SDR/DDR = LOW).

In DDR mode (SDR/DDR = HIGH) each edge of this clock

shifts the conversion result MSB first onto the SDO pins.

These pins must be differentially terminated by an external

100Ω resistor at the receiver (ADC).

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

FuncTional block DiagraM

CMOS IO Mode

CMOS

I/O

SDO1

DNC

AIN1+

REF

AIN1–

CNV

VDD

(15, 21, 44, 52)

REF ×1

CMOS

RECEIVERS

OUTPUT

CLOCK DRIVER

–

S/H 14-BIT+SIGN

SAR ADC

CMOS

I/O

SDO2

DNC

AIN2+

AIN2–

REF ×1

–

S/H 14-BIT+SIGN

SAR ADC

CMOS

I/O

SDO3

DNC

AIN3+

DNC

SCK

AIN3–

REF ×1

–

S/H 14-BIT+SIGN

SAR ADC

CMOS

I/O

SDO4

DNC

REFOUT4

CMOS/LVDS

AIN4+

AIN4–

REF ×1

–

S/H 14-BIT+SIGN

SAR ADC

SDR/DDR

REFOUT3

×1.7

×3.4 1.2V INT REF REFBUFEN

OVDD (31, 37)

CLKOUTEN

CLKOUT

REFOUT2

REFOUT1

250μA

GND

(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)

232514 BDa

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

LVDS IO Mode

FuncTional block DiagraM

LVDS

I/O

SDOA+

SDOA–

AIN1+

REF

AIN1–

CNV

VDD

(15, 21, 44, 52)

REF ×1

LVDS

RECEIVERS

OUTPUT

CLOCK DRIVER

–

S/H 14-BIT+SIGN

SAR ADC

LVDS

I/O

SDOB+

SDOB–

AIN2+

AIN2–

REF ×1

–

S/H 14-BIT+SIGN

SAR ADC

LVDS

I/O

SDOC+

SDOC–

AIN3+

SCK–

SCK+

AIN3–

REF ×1

–

S/H 14-BIT+SIGN

SAR ADC

LVDS

I/O

SDOD+

SDOD–

REFOUT4

CMOS/LVDS

AIN4+

AIN4–

REF ×1

–

S/H 14-BIT+SIGN

SAR ADC

SDR/DDR

REFOUT3

×1.7

×3.4 1.2V INT REF REFBUFEN

OVDD (31, 37)

CLKOUT–

CLKOUT+

REFOUT2

REFOUT1

250μA

GND

(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)

232514 BDb

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

TiMing DiagraM

SDR Mode, CMOS

DDR Mode, CMOS

CNV

SCK

SDO1

CLKOUT

D14

Hi-Z

ACQUIRE

SAMPLE N

D13

D12

D11

D10

SAMPLE N+1

SDO4

D14

Hi-Z

D13

D12

D11

D10

Hi-Z

CONVERSION AND READOUT

232514 TD01

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4

CNV

SDO1

D14

Hi-Z

ACQUIRE

SAMPLE N

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1

D13

D12

D11

D10

SAMPLE N+1

SDO4

D14

Hi-Z

D13

D12

D11

D10

Hi-Z

CONVERSION AND READOUT

SCK

CLKOUT

Hi-Z

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4

232514 TD02

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

SDR Mode, LVDS

DDR Mode, LVDS

TiMing DiagraM

CNV

SCK

SDOA

CLKOUT

D14

ACQUIRE

SAMPLE N

D13

D12

D11

D10

SAMPLE N+1

SDOD

D14

D13

D12

D11

D10

CONVERSION AND READOUT

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4

232514 TD03

CNV

SDOA

D14

ACQUIRE

SAMPLE N

D13

D12

D11

D10

SAMPLE N+1

SDOD

D14

D13

D12

D11

D10

CONVERSION AND READOUT

SCK

CLKOUT

232514 TD04

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

OVERVIEW

The LTC2325-14 is a low noise, high speed 14-bit succes-

sive approximation register (SAR) ADC with differential

inputs and a wide input common mode range. Operating

from a single 3.3V or 5V supply, the LTC2325-14 has a

4VP-P or 8VP-P differential input range, making it ideal for

applications which require a wide dynamic range. The

LTC2325-14 achieves ±1LSB INL typical, no missing codes

at 14 bits and 81dB SNR.

The LTC2325-14 has an onboard reference buffer and low

drift (20ppm/°C max) 4.096V temperature-compensated

reference. The LTC2325-14 also has a high speed SPI-

compatible serial interface that supports CMOS or LVDS.

The fast 5Msps per channel throughput with one-cycle

latency makes the LTC2325-14 ideally suited for a wide

variety of high speed applications. The LTC2325-14 dis-

sipates only 45mW per channel. Nap and sleep modes

are also provided to reduce the power consumption

of the LTC2325-14 during inactive periods for further

power savings.

CONVERTER OPERATION

The LTC2325-14 operates in two phases. During the ac-

quisition phase, the sample capacitor is connected to the

analog input pins AIN+ and AIN– to sample the differential

analog input voltage, as shown in Figure3. A falling edge on

the CNV pin initiates a conversion. During the conversion

phase, the 15-bit CDAC is sequenced through a successive

approximation algorithm effectively comparing the sampled

input with binary-weighted fractions of the reference volt-

age (e.g., VREFOUT/2, VREFOUT/4 … VREFOUT/32768) using

a differential comparator. At the end of conversion, a CDAC

output approximates the sampled analog input. The ADC

control logic then prepares the 15-bit digital output code

for serial transfer.

TRANSFER FUNCTION

The LTC2325-14 digitizes the full-scale voltage of 2 •

REFOUT1,2,3,4 into 215 levels, resulting in an LSB size of

1mV with REF = 4.096V. The ideal transfer function is shown

in Figure2. The output data is in 2’s complement format.

When driven by fully differential inputs, the transfer func-

tion spans 215 codes. When driven by pseudo-differential

inputs, the transfer function spans 214 codes.

Figure2. LTC2325-14 Transfer Function

Figure3. The Equivalent Circuit for the Differential

Analog Input of the LTC2325-14

Table 1. Code Ranges for the Analog Input Operational Modes

MODE SPAN (VIN+ – VIN–) MIN CODE MAX CODE

Fully Differential –REFOUT to +REFOUT 100 0000 0000 0000 011 1111 1111 1111

Pseudo-Differential Bipolar –REFOUT/2 to +REFOUT/2 110 0000 0000 0000 001 1111 1111 1111

Pseudo-Differential Unipolar 0 to REFOUT 000 0000 0000 0000 011 1111 1111 1111

INPUT VOLTAGE (V)

–REFOUT REFOUT – 1LSB

OUTPUT CODE (TWO’S COMPLEMENT)

232514 F02

011 1111 1111 1111

011 1111 1111 1110

111 1111 1111 1111

100 0000 0000 0000

100 0000 0000 0001

000 0000 0000 0000

000 0000 0000 0001

–1

LSB

1LSB = 2 • REFOUT/32768

0 1

LSB

RON

15Ω

RON

15Ω

BIAS

VOLTAGE

232514 F03

CIN

10pF

VDD

CIN

10pF

VDD

AIN–

AIN+

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

Analog Input

The differential inputs of the LTC2325-14 provide great

flexibility to convert a wide variety of analog signals with

no configuration required. The LTC2325-14 digitizes the

difference voltage between the AIN+ and AIN– pins while

supporting a wide common mode input range. The analog

input signals can have an arbitrary relationship to each

other, provided that they remain between VDD and GND.

The LTC2325-14 can also digitize more limited classes of

analog input signals such as pseudo-differential unipolar/

bipolar and fully differential with no configuration required.

The analog inputs of the LTC2325-14 can be modeled

by the equivalent circuit shown in Figure3. The back-

to-back diodes at the inputs form clamps that provide

ESD protection. In the acquisition phase, 10pF (CIN)

from the sampling capacitor in series with approximately

15Ω(RON) from the on-resistance of the sampling switch

is connected to the input. Any unwanted signal that is

common to both inputs will be reduced by the common

mode rejection of the ADC sampler. The inputs of the

ADC core draw a small current spike while charging the

CIN capacitors during acquisition.

Single-Ended Signals

Single-ended signals can be directly digitized by the

LTC2325-14. These signals should be sensed pseudo-

differentially for improved common mode rejection. By

connecting the reference signal (e.g., ground sense) of

the main analog signal to the other AIN pin, any noise or

disturbance common to the two signals will be rejected

by the high CMRR of the ADC. The LTC2325-14 flexibility

handles both pseudo-differential unipolar and bipolar

signals, with no configuration required. The wide common

mode input range relaxes the accuracy requirements of

any signal conditioning circuits prior to the analog inputs.

Figure4. Pseudo-Differential Bipolar Application Circuit

Figure5. Pseudo-Differential Bipolar Transfer Function

25Ω

220pF

VREF

VREF /2

VREF

10k

ONLY CHANNEL 1 SHOWN FOR CLARITY

–

LTC2325-14LT1819

232514 F04

SDO1

REF

REFOUT1

CLKOUT

AIN1–

AIN1+

SCK

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

1µF

10µF

1µF

232514 F05

–VREF

–8192

8191

–16384

16383

VREF

DOTTED REGIONS AVAILABLE

AIN

(AIN+ – AIN–)

ADC CODE

(2’s COMPLEMENT)

–VREF/2 VREF /20

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

Pseudo-Differential Bipolar Input Range

The pseudo-differential bipolar configuration represents

driving one of the analog inputs at a fixed voltage, typically

VREF/2, and applying a signal to the other AIN pin. In this

case the analog input swings symmetrically around the

fixed input yielding bipolar two’s complement output codes

with an ADC span of half of full-scale. This configuration

is illustrated in Figure4, and the corresponding transfer

function in Figure5. The fixed analog input pin need not

be set at VREF/2, but at some point within the VDD rails

allowing the alternate input to swing symmetrically around

this voltage. If the input signal (AIN+ – AIN–) swings beyond

±REFOUT1,2,3,4/2, valid codes will be generated by the

ADC and must be clamped by the user, if necessary.

Pseudo-Differential Unipolar Input Range

The pseudo-differential unipolar configuration represents

driving one of the analog inputs at ground and applying a

signal to the other AIN pin. In this case, the analog input

swings between ground and VREF yielding unipolar two’s

complement output codes with an ADC span of half of

full-scale. This configuration is illustrated in Figure6, and

the corresponding transfer function in Figure7. If the input

signal (AIN+ – AIN–) swings negative, valid codes will be

generated by the ADC and must be clamped by the user,

if necessary.

Figure6. Pseudo-Differential Unipolar Application Circuit

Figure7. Pseudo-Differential Unipolar Transfer Function

25Ω

220pF

VREF

–

LTC2325-14

LT1818

232514 F06

SDO1

REF

REFOUT1

CLKOUT

AIN1–

AIN1+

SCK

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

1µF

10µF

232514 F07

–VREF

–8192

8191

–16384

16383

VREF

DOTTED REGIONS AVAILABLE

AIN

(AIN+ – AIN–)

ADC CODE

(2’s COMPLEMENT)

–VREF/2 VREF /20

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

Single-Ended-to-Differential Conversion

While single-ended signals can be directly digitized as pre-

viously discussed, single-ended to differential conversion

circuits may also be used when higher dynamic range is

desired. By producing a differential signal at the inputs of

the LTC2325-14, the signal swing presented to the ADC is

maximized, thus increasing the achievable SNR.

The LT

1819 high speed dual operational amplifier is

recommended for performing single-ended-to-differential

conversions, as shown in Figure8. In this case, the first

amplifier is configured as a unity-gain buffer and the

single-ended input signal directly drives the high imped-

ance input of this amplifier.

Fully-Differential Inputs

To achieve the best distortion performance of the

LTC2325-14, we recommend driving a fully-differential

signal through LT1819 amplifiers configured as two

unity-gain buffers, as shown in Figure 9. This circuit

achieves the full data sheet THD specification of –88dB at

input frequencies up to 500kHz. A fully-differential input

signal can span the maximum full-scale of the ADC, up to

±REFOUT1,2,3,4. The common mode input voltage can

span the entire supply range up to VDD, limited by the

input signal swing. The fully-differential configuration is

illustrated in Figure10, with the corresponding transfer

function illustrated in Figure11.

INPUT DRIVE CIRCUITS

A low impedance source can directly drive the high im-

pedance inputs of the LTC2325-14 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC inputs, because the ADC inputs

draw a current spike when during acquisition.

For best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2325-14. The amplifier

provides low output impedance to minimize gain error

and allows for fast settling of the analog signal during

the acquisition phase. It also provides isolation between

the signal source and the ADC inputs, which draw a small

current spike during acquisition.

Figure8. Single-Ended to Differential Driver Figure9. LT1819 Buffering a Fully-Differential Signal Source

VREF

VREF /2

–

200Ω

LT1819

232514 F08

VREF

–

LT1819

232514 F09

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

Input Filtering

The noise and distortion of the buffer amplifier and signal

source must be considered since they add to the ADC noise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with a low bandwidth filter

to minimize noise. The simple 1-pole RC lowpass filter

shown in Figure12 is sufficient for many applications.

The sampling switch on-resistance (RON) and the sample

capacitor (CIN) form a second lowpass filter that limits

the input bandwidth to the ADC core to 110MHz. A buffer

amplifier with a low noise density must be selected to

minimize the degradation of the SNR over this bandwidth.

High quality capacitors and resistors should be used in the

RC filters since these components can add distortion. NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occur during soldering. Metal film surface mount resistors

are much less susceptible to both problems.

25Ω

220pF

VREF

ONLY CHANNEL 1 SHOWN FOR CLARITY

–

LTC2325-14LT1819

232514 F10

SDO1

REF

REFOUT1

CLKOUT

AIN1–

AIN1+

SCK

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

1µF

10µF

Figure10. Fully-Differential Application Circuit

Figure11. Fully-Differential Transfer Function

232514 F11

–VREF

–8192

8191

–16384

16383

VREF

AIN

(AINn+ – AINn–)

ADC CODE

(2’s COMPLEMENT)

–VREF/2 VREF /20

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

ADC REFERENCE

Internal Reference

The LTC2325-14 has an on-chip, low noise, low

drift(20ppm/°C max), temperature compensated band-

gap reference. It is internally buffered and is available

at REF (Pin8). The reference buffer gains the internal

reference voltage to 4.096V for supply voltages VDD = 5V

and to 2.048V for VDD = 3.3V. The REF pin also drives

the four internal reference buffers with a current limited

output(250μA) so it may be easily overdriven with an

external reference in the range of 1.25V to 5V. Bypass

REF to GND with a 1μF (X5R, 0805 size) ceramic capacitor

to compensate the reference buffer and minimize noise.

The 1μF capacitor should be as close as possible to the

LTC2325-14 package to minimize wiring inductance. The

voltage on the REF pin must be externally buffered if used

for external circuitry.

Figure12. Input Signal Chain

Table 2. Reference Configurations and Ranges

REFERENCE CONFIGURATION VDD REFBUFEN REF PIN

REFOUT1,2,3,4

DIFFERENTIAL

INPUT RANGE

Internal Reference with Internal Buffers 5V 5V 4.096V 4.096V ±4.096V

3.3V 3.3V 2.048V 2.048V ±2.048V

Common External Reference with Internal Buffer (REF Pin

Externally Overdriven)

5V 5V 1.25V to 5V 1.25V to 3.3V ±1.25V to ±5V

3.3V 3.3V 1.25V to 5V 1.25V to 3.3V ±1.25V to ±3.3V

External Reference with REF Buffers Disabled 5V 0V 4.096V 1.25V to 5V ±1.25V to ±5V

3.3V 0V 2.048V 1.25V to 3.3V ±1.25V to ±3.3V

50Ω

SINGLE-ENDED

INPUT SIGNAL

232514 F12

BW = 1MHz

3.3nF

SINGLE-ENDED

TO DIFFERENTIAL

DRIVER

IN+

IN–LTC2325

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

External Reference

The internal REFOUT1,2,3,4 buffers can also be over-

driven from 1.25V to 5V with an external reference at

REFOUT1,2,3,4 as shown in Figure 13 (c). To do so,

REFBUFEN must be grounded to disable the REF buffers.

A 55k internal resistance loads the REFOUT1,2,3,4 pins

when the REF buffers are disabled. To maximize the input

signal swing and corresponding SNR, the LTC6655-5 is

(13a) LTC2325-14 Internal Reference Circuit (13b) LTC2325-14 with a Shared External Reference Circuit

(13c) LTC2325-14 with Different External Reference Voltages

Figure13. Reference Connections

recommended when overdriving REFOUT. The LTC6655-5

offers the same small size, accuracy, drift and extended

temperature range as the LTC6655-4.096. By using a 5V

reference, a higher SNR can be achieved. We recommend

bypassing the LTC6655-5 with a 10μF ceramic capacitor

(X5R, 0805 size) close to each of the REFOUT1,2,3,4

pins. If the REF pin voltage is used as a REFOUT refer-

ence when REFBUFEN is connected to GND, it should be

buffered externally.

LTC6655-4.096

5V TO

13.2V

0.1µF

VDD

LTC2325-14

GND

232514 F13b

+5V

REF

REFOUT1

REFOUT2

REFOUT3

REFOUT4

REFBUFEN

10µF

VIN

SHDN

VOUT_F

VOUT_S

5V TO 13.2V

0.1µF

VDD

LTC2325-14

GND

232514 F13c

+5V

REFOUT1

REF

REFOUT2

REFOUT3

REFOUT4

REFBUFEN

10µF

LTC6655-4.096

1µF

VIN

SHDN

VOUT_F

VOUT_S

5V TO 13.2V

0.1µF

10µF

LTC6655-2.048

VIN

SHDN

VOUT_F

VOUT_S

5V TO 13.2V

0.1µF

10µF

LTC6655-2.5

VIN

SHDN

VOUT_F

VOUT_S

5V TO 13.2V

0.1µF

10µF

LTC6655-3

VIN

SHDN

VOUT_F

VOUT_S

VDD

LTC2325-14

GND

232514 F13a

3.3V TO 5V

REF

REFOUT1

REFOUT2

REFOUT3

REFOUT4

REFBUFEN

1µF

10µF

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

Internal Reference Buffer Transient Response

The REFOUT1,2,3,4 pins of the LTC2325-14 draw charge

(QCONV) from the external bypass capacitors during

each conversion cycle. If the internal reference buffer is

overdriven, the external reference must provide all of this

charge with a DC current equivalent to IREF = QCONV/tCYC.

Thus, the DC current draw of IREFOUT1,2,3,4 depends

on the sampling rate and output code. In applications

where a burst of samples is taken after idling for long

periods, as shown in Figure 14 , IREFBUF quickly goes

from approximately ~75µA to a maximum of 500µA for

REFOUT = 5V at 5Msps. This step in DC current draw

triggers a transient response in the external reference that

must be considered since any deviation in the voltage at

REFOUT will affect the accuracy of the output code. Due

to the one-cycle conversion latency, the first conversion

result at the beginning of a burst sampling period will

be invalid. If an external reference is used to overdrive

REFOUT1,2,3,4, the fast settling LTC6655 reference is

recommended.

DYNAMIC PERFORMANCE

Fast Fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2325-14 provides

guaranteed tested limits for both AC distortion and noise

measurements.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is bandlimited

to frequencies from above DC and below half the sampling

frequency. Figure16 shows that the LTC2325-14 achieves

a typical SINAD of 80dB at a 5MHz sampling rate with a

2.2MHz input.

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure16 shows

that the LTC2325-14 achieves a typical SNR of 81dB at a

5MHz sampling rate with a 2.2MHz input.

CNV

232514 F14

IDLE

PERIOD

Figure14. CNV Waveform Showing Burst Sampling

Figure15. Transient Response of the LTC2325-14 Figure16. 32k Point FFT of the LTC2325-14

SNR = 81.3dB

THD = –87.2dB

SINAD = 80.5dB

SFDR = 90.3dB

FREQUENCY (MHz)

0.5

1.5

2.5

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

232514 F16

4.096V RANGE

SETTLING TIME (ns)

–20

–10

–4096

4096

8192

12288

16384

OUTPUT CODE (LSB)

232514 F15

IN+ = 5MHz SQUARE WAVE

IN– = 0V

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

Total Harmonic Distortion (THD)

Total harmonic distortion (THD) is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental itself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (fSMPL/2).

THD is expressed as:

THD=20log V22+V32+V42+…+ VN

where V1 is the RMS amplitude of the fundamental

frequency and V2 through VN are the amplitudes of the

second through Nth harmonics.

POWER CONSIDERATIONS

The LTC2325-14 requires two power supplies: the 3.3V

to 5V power supply (VDD), and the digital input/output

interface power supply (OVDD). The flexible OVDD supply

allows the LTC2325-14 to communicate with any digital

logic operating between 1.8V and 2.5V. When using LVDS

I/O, the OVDD supply must be set to 2.5V.

Power Supply Sequencing

The LTC2325-14 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2325-14

has a power-on-reset (POR) circuit that will reset the

LTC2325-14 at initial power-up or whenever the power

supply voltage drops below 2V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 10ms after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

Figure17. Power Supply Current of the LTC2325-14 Versus Sampling Rate

= 5V

= 3.3V

SAMPLE FREQUENCY (Msps)

SUPPLY CURRENT (mA)

232514 F17

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

TIMING AND CONTROL

CNV Timing

The LTC2325-14 sampling and conversion is controlled

by CNV. A rising edge on CNV will start sampling and the

falling edge starts the conversion and readout process. The

conversion process is timed by the SCK input clock. For

optimum performance, CNV should be driven by a clean

low jitter signal. The Typical Application at the back of the

data sheet illustrates a recommended implementation to

reduce the relatively large jitter from an FPGA CNV pulse

source. Note the low jitter input clock times the falling

edge of the CNV signal. The rising edge jitter of CNV is

much less critical to performance. The typical pulse width

of the CNV signal is 30ns with < 1.5ns rise and fall times

at a 5Msps conversion rate.

SCK Serial Data Clock Input

In SDR mode (SDR/DDR Pin 23 = GND), the falling edge

of this clock shifts the conversion result MSB first onto

the SDO pins. A 100MHz external clock must be applied

at the SCK pin to achieve 5Msps throughput using all four

SDO outputs. In DDR mode (SDR/DDR Pin 23 = OVDD),

each input edge of SCK shifts the conversion result MSB

first onto the SDO pins. A 50MHz external clock must be

applied at the SCK pin to achieve 5Msps throughput using

all five SDO1 through SDO4 outputs.

CLKOUT Serial Data Clock Output

The CLKOUT output provides a skew-matched clock to

latch the SDO output at the receiver. The timing skew

of the CLKOUT and SDO outputs are matched. For high

throughput applications, using CLKOUT instead of SCK to

capture the SDO output eases timing requirements at the

receiver. For low throughput speed applications, CLKOUT

can be disabled by tying Pin 34 to OVDD.

Nap/Sleep Modes

Nap mode is a method to save power without sacrificing

power-up delays for subsequent conversions. Sleep mode

has substantial power savings, but a power-up delay is

incurred to allow the reference and power systems to

become valid. To enter nap mode on the LTC2325-14,

the SCK signal must be held high or low and a series of

two CNV pulses must be applied. This is the case for both

CMOS and LVDS modes. The second rising edge of CNV

initiates the nap state. The nap state will persist until either

a single rising edge of SCK is applied, or further CNV pulses

are applied. The SCK rising edge will put the LTC2325-14

back into the operational (full-power) state. When in nap

mode, two additional pulses will put the LTC2325-14 in

sleep mode. When configured for CMOS I/O operation, a

single rising edge of SCK can return the LTC2325-14 into

operational mode. A 10ms delay is necessary after exiting

sleep mode to allow the reference buffer to recharge the

external filter capacitor. In LVDS mode, exit sleep mode

by supplying a fifth CNV pulse. The fifth pulse will return

the LTC2325-14 to operational mode, and further SCK

pulses will keep the part from re-entering nap and sleep

modes. The fifth SCK pulse also works in CMOS mode

as a method to exit sleep. In the absence of SCK pulses,

repetitive CNV pulses will cycle the LTC2325-14 between

operational, nap and sleep modes indefinitely.

Refer to the timing diagrams in Figure18, Figure19, Figure20

and Figure21 for more detailed timing information about

sleep and nap modes.

Figure18. CMOS and LVDS Mode NAP and WAKE Using SCK

FULL POWER MODE

1 2CNV

SCK HOLD STATIC HIGH OR LOW

NAP MODE

SDO1 – 4

WAKE ON 1ST SCK EDGE

Z Z 232514 F18

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

Figure19. CMOS Mode SLEEP and WAKE Using SCK

Figure20. LVDS and CMOS Mode SLEEP and WAKE Using CNV

Figure21. LTC2325-14 Timing Diagram

FULL POWER MODE

1234

4.096V4.096V

REFOUT

RECOVERY

REFOUT1 – 4

CNV

SCK HOLD STATIC HIGH OR LOW

NAP MODE SLEEP MODE

SDO1 – 4

WAKE ON 1ST SCK EDGE

ZZZZ 232514 F19

tWAKE

1234 5

4.096V4.096V

REFOUT

RECOVERY

CNV

SCK HOLD STATIC HIGH OR LOW

NAP MODE SLEEP MODE FULL POWER MODE

WAKE ON 5TH

CNV EDGE

ZZZZ Z 232514 F20

tWAKE

REFOUT1 – 4

SDO1 – 4

232514 F21

D15

SCKL

SCKH

SCK

CNVH

CYC

CNV

SCK

SDO

CLKOUT

D14

D13

CONV

READOUT

D15

DSCKCLKOUT

DCNVSDOZ

HSDO

DCNVSDOV

HI-Z

DSCKCNVH

DDR MODE TIMING

D15

SCKL

SCKH

SCK

CNVH

CYC

CNV

SCK

SDO

CLKOUT

D14

D13

CONV

READOUT

D15

DSCKCLKOUT

DCNVSDOZ

HSDO

DCNVSDOV

HI-Z

DSCKCNVH

SDR MODE TIMING

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

applicaTions inForMaTion

Figure22. LTC2325-14 Using the LVDS Interface

DIGITAL INTERFACE

The LTC2325-14 features a serial digital interface that

is simple and straightforward to use. The flexible OVDD

supply allows the LTC2325-14 to communicate with any

digital logic operating between 1.8V and 2.5V. In addi-

tion to a standard CMOS SPI interface, the LTC2325-14

provides an optional LVDS SPI interface to support low

noise digital design. The CMOS /LVDS pin is used to select

the digital interface mode. The SCK input clock shifts the

conversion result MSB first on the SDO pins. CLKOUT

provides a skew-matched clock to latch the SDO output

at the receiver. The timing skew of the CLKOUT and SDO

outputs are matched. For high throughput applications,

using CLKOUT instead of SCK to capture the SDO output

eases timing requirements at the receiver. In CMOS mode,

use the SDO1 – SDO4, and CLKOUT pins as outputs. Use

the SCK pin as an input. In LVDS mode, use the SDOA+/

SDOA– through SDOD+/SDOD– and CLKOUT+/CLKOUT–

pins as differential outputs. Each LVDS lane yields one

channel worth of data: SDOA yields CH1 data, SDOB

yields CH2 data, SDOC yields CH3 data and SDOD yields

CH4 data. These pins must be differentially terminated

by an external 100Ω resistor at the receiver (FPGA).

The SCK+/SCK– pins are differential inputs and must be

terminated differentially by an external 100Ω resistor at

the receiver(ADC).

SDR/DDR Modes

The LTC2325-14 has an SDR (single data rate) and DDR

(double data rate) mode for reading conversion data from

the SDO pins. In both modes, CLKOUT is a delayed version

of SCK. In SDR mode, each negative edge of SCK shifts

the conversion data out the SDO pins. In DDR mode,

each edge of the SCK input shifts the conversion data

out. In DDR mode, the required SCK frequency is half of

what is required in SDR mode. Tie SDR/DDR to ground

to configure for SDR mode and to OVDD for DDR mode.

The CLKOUT signal is a delayed version of the SCK input

and is phase aligned with the SDO data. In SDR mode, the

SDO transitions on the falling edge of CLKOUT as illus-

trated in Figure21. We recommend using the rising edge

of CLKOUT to latch the SDO data into the FPGA register

in SDR mode. In DDR mode, the SDO transitions on each

input edge of SCK. We recommend using the CLKOUT ris-

ing and falling edges to latch the SDO data into the FPGA

registers in DDR mode. Since the CLKOUT and SDO data

are phase aligned, we recommend digitally delaying the

SDO data in the FPGA to provide adequate setup and hold

timing margins in DDR mode.

BOARD LAYOUT

To obtain the best performance from the LTC2325-14,

a printed circuit board is recommended. Layout for the

printed circuit board (PCB) should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals adjacent to analog signals or underneath

the ADC.

Supply bypass capacitors should be placed as close as

possible to the supply pins. Low impedance common re-

turns for these bypass capacitors are essential to the low

noise operation of the ADC. A single solid ground plane

is recommended for this purpose. When possible, screen

the analog input traces using ground.

Recommended Layout

For a detailed look at the reference design for this con-

verter, including schematics and PCB layout, please refer

to DC2395A, the evaluation kit for the LTC2325-14.

100Ω

2.5V

OVDD

LTC2325-14 FPGA OR DSP

232514 F22

SCK+

SCK–

SDOD+

SDOD–

SDOC+

SDOC–

SDOB+

SDOB–

SDOA+

SDOA–

CMOS/LVDS

–

100Ω

–

100Ω

–

100Ω

–

100Ω

–

100Ω

CLKOUT+

CLKOUT–

CNV RETIMING

FLIP-FLOP

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

package DescripTion

7.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45°C

CHAMFER

0.40 ±0.10

5251

BOTTOM VIEW—EXPOSED PAD

TOP VIEW

SIDE VIEW

6.50 REF

(2 SIDES)

8.00 ±0.10

(2 SIDES)

5.50 REF

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.10

TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

6.45 ±0.10

5.41 ±0.10

0.00 – 0.05

(UKG52) QFN REV Ø 0306

5.50 REF

(2 SIDES)

5.41 ±0.05

6.45 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

6.10 ±0.05

7.50 ±0.05

6.50 REF

(2 SIDES) 7.10 ±0.05 8.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

UKG Package

52-Lead Plastic QFN (7mm × 8mm)

(Reference LTC DWG # 05-08-1729 Rev Ø)

Please refer to http://www.linear.com/product/LTC2325-14#packaging for the most recent package drawings.

UKG Package

52-Lead Plastic QFN (7mm × 8mm)

(Reference LTC DWG # 05-08-1729 Rev Ø)

LTC2325-14

232514f

For more information www.linear.com/LTC2325-14

 LINEAR TECHNOLOGY CORPORATION 2017

LT 0417 • PRINTED IN USA

www.linear.com/LTC2325-14

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

ADCs

LTC2311-16/LTC2311-14/

LTC2311-12

16-/14-/12-Bit, 5Msps Simultaneous Sampling ADC 3.3V Supply, 1-Channel 40mW, 20ppm/°C Internal Reference,

Flexible Inputs, 16-Lead MSOP Package

LTC2323-16/LTC2323-14/

LTC2323-12

16-14-/12-Bit Dual Simultaneous Sampling ADC 3V/5V Supply, 40mW/Ch, 20ppm/°C Max Internal Reference,

Flexible Inputs, 4mm × 5mm QFN-28 Package

LTC2321-16/LTC2321-14/

LTC2321-12

16-/14-/12-Bit, Dual 2Msps, Simultaneous

Sampling ADCs

3.3V/5V Supply, 33mW/Ch, 20ppm°C Max Internal Reference,

Flexible Inputs, 4mm × 5mm QFN-28 Package

LTC2320-16/LTC2320-14/

LTC2320-12

16-/14-12-Bit Octal, 1.5Msps/Ch Simultaneous

Sampling ADC

3.3V/5V Supply, 20mW/Ch, 20ppm/°C Internal Reference,

Flexible Inputs, 7mm × 8mm QFN-52 Package

LTC2324-16/LTC2324-14/

LTC2324-12

16-/14-12-Bit Quad, 2Msps/Ch Simultaneous

Sampling ADC

3.3V/5V Supply, 40mW/Ch, 20ppm/°C Internal Reference,

Flexible Inputs, 7mm × 8mm QFN-52 Package

DACs

LTC2632 Dual 12-/10-/8-Bit, SPI VOUT DACs with Internal

Reference

2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,

Rail-to-Rail Output, 8-Pin ThinSOT™ Package

LTC2602/LTC2612/

LTC2622

Dual 16-/14-/12-Bit SPI VOUT DACs with External

Reference

300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead

MSOP Package

References

LTC6655 Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm

Peak-to-Peak Noise, MSOP-8 Package

LTC6652 Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm

Peak-to-Peak Noise, MSOP-8 Package

Amplifiers

LT1818/LT1819 400MHz, 2500V/µs, 9mA Single/Dual Operational

Amplifiers

–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply

Current, Unity-Gain Stable

LT1806 325MHz, Single, Rail-to-Rail Input and Output, Low

Distortion, Low Noise Precision Op Amps

–80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,

9mA Supply Current, Unity-Gain Stable

LT6200 165MHz, Rail-to-Rail Input and Output, 0.95nV/√Hz

Low Noise, Op Amp Family

Low Noise, Low Distortion, Unity-Gain Stable

Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop

NC7SVU04P5X (× 5)

50Ω

NC7SVUO4P5X

CONV ENABLE

MASTER_CLOCK

CONV

LTC2325-14

232514 TA02

SDO1 – 4

SCK

GND

CLR

NC7SV74K8X CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

PRE

CLKOUT

CNV

CMOS/LVDS

GND SDR/DDR

VCC

0.1µF

10Ω