GT93C56A 2Kb Microwire Serial EEPROM Advanced 1. Features Industry-standard Microwire Interface Wide-voltage Operation - Speed - Versatile, easy-to-use interface - - - - 1 MHz (1.8V), 2 MHz (2.5V), 3 MHz (5.5V) 1uA (max.) 1.8V 1mA (max.) 1.8V User Configured Memory Organization - - Software instructions for write-enable/disable CMOS technology Operating current - Defaults to write-disabled state at power-up Standby current - VCC = 1.8V to 5.5V - - Automatic erase-before-write Programming status indicator Byte, Word and chip single erasable Chip select enables power savings Noise immunity on inputs, besides Schmitt trigger High-reliability - - 128x16-bit (ORG = VCC or Floating) or 256x8-bit (ORG = 0V) Endurance: 1 million cycles Data retention: 100 years Self timed write cycle: 5 ms (max.) Packages: SOIC/SOP, TSSOP, and UDFN Hardware and software write protection Lead-free, RoHS, Halogen free, Green 2. General Description The GT93C56A is 2kb non-volatile serial EEPROM with the devices, including read, write, and mode-enable memory array of 2,048 bits. The array can be organized as functions. To protect against inadvertent data modification, either 256 bytes of 8 bits or 128 words of 16 bits via the all write and erase instructions are merely accepted while ORG control. Utilizing the CMOS design and process, these the device is in write enable mode. A selected x8 byte or products provide low standby current and low power x16 word can be modified with a single WRITE or ERASE operations. The devices can operate in a wide supply instruction. Additionally, the WRITE ALL or ERASE ALL voltage range from 1.8V to 5.5V, with frequency up to instruction can program or erase the entire array, 3MHz. respectively. Once a device begins its self-timed program When the ORG pin is connected to VCC or floating, x16 is procedure, the data out pin (Dout) can indicate the selected. Conversely, when it is connected to ground, x8 is READY/BUSY status by raising chip select (CS). The chosen. devices can output any number of consecutive bytes/words An instruction Op-code defines the various operations of using a single READ instruction. Copyright (c) 2010 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment, aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products. Giantec Semiconductor, Inc. A0 www.giantec-semi.com 1/17 GT93C56A 3. Functional Block Diagram Giantec Semiconductor, Inc. A0 www.giantec-semi.com 2/17 GT93C56A 4. Pin Configuration 4.1 8-Pin SOIC/SOP and TSSOP (Top View) 4.2 8-Lead UDFN (Top View) CS SK VCC DIN DOUT ORG GND NC Note: Please see section Top Markings for detailed Marking Information. 4.3 Pin Definition Pin No. Pin Name I/O 1 CS I Chip Select 2 SK I Serial Data Clock 3 DIN I Serial Data Input 4 DOUT O Serial Data Output 5 GND - Ground 6 ORG I Organization Select 7 NC - Not Connect 8 VCC - Supply Voltage Giantec Semiconductor, Inc. A0 Definition www.giantec-semi.com 3/17 GT93C56A 5. Device Operation The GT93C56A is controlled by a set of instructions which Figure 5.10-3) (Note: Chip select must remain LOW until are clocked-in serially on the Din pin. Before each VCC reaches its operational value.) low-to-high transition of the clock (SK), the CS pin must 5.3 Write Disable (WDS) have already been raised to HIGH, and the Din value must The be stable at either LOW or HIGH. Each instruction begins programming capabilities. This protects the entire device with a start bit of the logical 1 or HIGH. Following this are against accidental modification of data until a WEN the Op-code, address field, and data, if appropriate. The instruction is executed. (When VCC is applied, this part clock signal may be held stable at any moment to suspend powers up in the write disabled state.) To protect data, a the device at its last state, allowing clock speed flexibility. WDS instruction should be executed upon completion of Upon completion of bus communication, CS would be each programming operation. pulled LOW. The device then would enter Standby mode if 5.4 Write (WRITE) no internal programming is underway. The WRITE instruction writes 8 or 16 bits of data into the 5.1 Read (READ) specified memory location. After the last data bit has been The READ instruction is the only instruction that outputs applied to DIN, and before the next rising edge of SK, CS serial data on the DOUT pin. After the read instruction and must be brought LOW. If the device is write-enabled, then address have been decoded, data is transferred from the the falling edge of CS initiates the self-timed programming selected memory array into a serial shift register. (Please cycle (see WEN). If CS is brought HIGH, after a minimum note that one logical 0 bit precedes the actual 8 or 16-bit wait of 200 ns after the falling edge of CS (tCS) DOUT will output data string.) The output on DOUT changes during indicate the READY/BUSY status of the chip. Logical 0 the low-to-high transitions of SK (see Figure 5.10-2). means programming is still in progress; logical 1 means The GT93C56A is designed to output a continuous stream the selected memory array has been written, and the part is of memory content in response to a single read operation ready for another instruction (see Figure 5.10-4). The instruction. To utilize this function, the system asserts a READY/BUSY status will not be available if the CS input read instruction specifying a start location address. Once goes HIGH after the end of the self-timed programming the 8 or 16 bits of the addressed register have been clocked cycle (Twp). out, the data in consecutively higher address locations is 5.5 Write All Memory (WRAL) output. The address will wrap around continuously with CS The write all (WRALL) instruction programs entire memory HIGH until the chip select (CS) control pin is brought LOW. with the data pattern specified in the instruction. As with the This allows for single instruction data dumps to be executed WRITE instruction, the falling edge of CS must occur to with a minimum of firmware overhead. initiate the self-timed programming cycle. If CS is then 5.2 Write Enable (WEN) brought HIGH after a minimum wait of 200 ns (tCS), the The write enable (WEN) instruction must be executed DOUT pin indicates the READY/BUSY status of the chip before any device programming (WRITE, WRALL, ERASE, (see Figure 5.10-5). and ERAL) can be done. When VCC is applied, this device 5.6 Erase (ERASE) powers up in the write disabled state. The device then After the erase instruction is entered, CS must be brought remains in a write disabled state until a WEN instruction is LOW. The falling edge of CS initiates the self-timed internal executed. Thereafter, the device remains enabled until a programming cycle. Bringing CS HIGH after a minimum of WDS instruction is executed or until VCC is removed. (See tCS, will cause DOUT to indicate the READ/BUSY status of Giantec Semiconductor, Inc. A0 write disable (WDS) instruction disables all www.giantec-semi.com 4/17 GT93C56A the chip: a logical 0 indicates programming is still in brown-out` due to a sudden power loss or power cycling. progress; a logical 1 indicates the erase cycle is complete In order to refrain the state machine entering into a wrong and the part is ready for another instruction (see Figure state during power-up sequence or a power toggle off-on 5.10-7). condition, a power on reset (POR) circuit is embedded. 5.7 Erase All Memory (ERAL) During power-up, the device does not respond to any Full chip erase is provided for ease of programming. instruction until VCC has reached a minimum stable level Erasing the entire chip involves setting all bits in the entire above the reset threshold voltage. Once VCC passes the memory array to a logical 1 (see Figure 5.10-8). POR threshold, the device is reset and enters in Standby 5.8 Power-On Reset (POR) mode. This can also avoid any inadvertent Write operations The device incorporates a Power-On Reset (POR) circuitry during power-up stage. During power-down process, the which protects the internal logic against powering up into a device must enter into standby mode, once VCC drops wrong state. The device will power up into Standby mode below the power on reset threshold voltage. In addition, the after VCC exceeds the POR trigger level and will power device will enter standby mode after current operation down into Reset mode when VCC drops below the POR completes, provided that no internal write operation is in trigger level. This POR feature protects the device being progress. 5.9 INSTRUCTION SET - GT93C56A (2Kb) Instruction [2] Start OP Bit Code 8-bit Organization 16-bit Organization (ORG = GND) (ORG = VCC or Floating) Required Address[1] Data[1] Clock Required Address[1] Data[1] Cycles Clock Cycles WDS (Write Disable) 1 00 0 0xxx xxxx -- 12 00xx xxxx -- 11 WEN (Write Enable) 1 00 1 1xxx xxxx -- 12 11xx xxxx -- 11 ERAL (Erase All Memory) 1 00 1 0xxx xxxx -- 12 10xx xxxx -- 11 WRAL (Write All Memory) 1 00 0 1xxx xxxx (D7-D0) 20 01xx xxxx (D15-D0) 27 WRITE 1 01 x(A7-A0) (D7-D0) 20 x(A6-A0) (D15-D0) 27 READ 1 10 x(A7-A0) -- x(A6-A0) -- 1 11 x(A7-A0) -- x(A6-A0) -- ERASE Notes: x = Don't care bit. [2] Exact number of clock cycles is required for each Op-code instruction. Giantec Semiconductor, Inc. A0 12 [1] 11 www.giantec-semi.com 5/17 GT93C56A 5.10 Diagrams Figure 5.10-1. Synchronous Data Timing Figure 5.10-2. Read Cycle Timing Figure 5.10-3. Write Enable (WEN) Cycle Timing Giantec Semiconductor, Inc. A0 www.giantec-semi.com 6/17 GT93C56A Figure 5.10-4. Write (Write) Cycle Timing Notes: [1] After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. [2] To determine address bits An-A0 and data bits Dm-D0, see Instruction Set for the specific device. Figure 5.10-5. Write All (WRALL) Cycle Timing Notes: [1] After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. [2] To determine data bits Dm-D0, see Instruction Set for the appropriate device. Figure 5.10-6. Write Disable (WDS) Timing Giantec Semiconductor, Inc. A0 www.giantec-semi.com 7/17 GT93C56A Figure 5.10-7. Erase (Erase) Cycle Timing Notes: [1] After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. [2] To determine data bits An - A0, see Instruction Set for the appropriate device. Figure 5.10-8. Erase All (ERAL) Cycle Timing Notes: [1] After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. [2] To determine data bits An - A0, see Instruction Set for the appropriate device. Giantec Semiconductor, Inc. A0 www.giantec-semi.com 8/17 GT93C56A 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Symbol Parameter Value Unit VS Supply Voltage -0.5 to + 6.5 V VP Voltage on Any Pin -0.5 to VCC + 0.5 V TBIAS Temperature Under Bias -55 to +125 C TSTG Storage Temperature -65 to +150 C IOUT Output Current 5 mA Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 6.2 Operating Range Range Ambient Temperature (TA) VCC Industrial -40C to +85C 1.8V to 5.5V Note: Giantec offers Industrial grade for Commercial applications (0C to +70C). 6.3 Capacitance [1, 2] Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = 0V 6 pF CI/O Input / Output Capacitance VI/O = 0V 8 pF Notes: [1] Tested initially and after any design or process changes that may affect these parameters and not 100% tested. [2] Test conditions: TA = 25C, f = 1 MHz, VCC = 5.0V. Giantec Semiconductor, Inc. A0 www.giantec-semi.com 9/17 GT93C56A 6.4 DC Electrical Characteristic Industrial: TA = -40C to +85C, VCC = 1.8V ~ 5.5V Symbol Parameter VCC Supply Voltage VOL1 Output LOW Voltage VOL2 Test Conditions Min. Max. Unit 1.8 5.5 V VCC = 1.8V~5.5V, IOL = 100 uA -- 0.2 V Output LOW Voltage VCC = 2.5V~5.5V, IOL = 2.1 mA -- 0.4 V VOH1 Output HIGH Voltage VCC = 1.8V~5.5V, IOH = -0.1mA VCC - 0.2 -- V VOH2 Output HIGH Voltage VCC = 2.5V~5.5V, IOH = -0.4mA 2.4 -- V VIH1 Input HIGH Voltage 1.8V to 5.5V 0.7*VCC VCC +1 V VIH2 Input HIGH Voltage 2.5V to 5.5V 2 VCC +1 V VIL1 Input LOW Voltage 1.8V to 5.5V -0.3 0.3*VCC V VIL2 Input LOW Voltage 2.5V to 5.5V -0.3 0.8 V ILI Input Leakage Current VIN = 0V to VCC (CS, SK,DIN,ORG) 0 2.5 A ILO Output Leakage Current VOUT = 0V to VCC, CS = 0V 0 2.5 A [1] Power Supply Characteristics Industrial: TA = -40C to +85C, VCC = 1.8V ~ 5.5V Symbol VCC ISB1 ISB2 ICC-Read ICC-Write Parameter [1] VCC Supply Voltage Standby current Standby current Read current Write current Min. Typ. 1.8 Max. Unit 5.5 V 1.8 CS = GND, SK = GND, -- 0.1 1 A 2.5 ORG = VCC or Floating -- 0.3 1 A 5.5 (x16), DIN = VCC or GND -- 0.5 1 A 1.8 CS = GND, SK = GND, -- 0.4 1 A 2.5 ORG = GND (x8), DIN = -- 6 10 A 5.5 VCC or GND -- 10 15 A 1.8 CS = VIH, SK = 1 MHz -- 0.5 mA 2.5 CS = VIH, SK = 2 MHz -- 0.5 mA 5.5 CS = VIH, SK = 3 MHz -- 1 mA 1.8 CS = VIH, SK = 1 MHz -- 1 mA 2.5 CS = VIH, SK = 2 MHz -- 1 mA 5.5 CS = VIH, SK = 3 MHz -- 2 mA Giantec Semiconductor, Inc. A0 Test Conditions www.giantec-semi.com 10/17 GT93C56A 6.5 AC Electrical Characteristic Industrial: TA = -40C to +85C, Supply voltage = 1.8V to 5.5V 1.8VVCC<2.5V 2.5VVCC<4.5V 4.5VVCC5.5V Min. Max. Min. Max. Min. Max. SCK Clock Frequency 0 1 0 2 0 3 MHz tR Input Rise Time -- 10 -- 10 -- 10 ns tF Input Fall Time -- 10 -- 10 -- 10 ns tSKH SK High Time 250 -- 200 -- 200 -- ns tSKL SK Low Time 250 -- 200 -- 100 -- ns tCS Minimum CS LOW Time 250 -- 200 -- 200 -- ns tCSS CS Setup Time 200 -- 100 -- 50 -- ns tCSH CS Hold Time 0 -- 0 -- 0 -- ns tDIS DIN Setup Time 100 -- 50 -- 50 -- ns tDIH DIN Hold Time 50 -- 50 -- 50 -- ns tPD1 Output Delay to 1 -- 400 -- 200 -- 100 ns tPD0 Output Delay to 0 -- 400 -- 200 -- 100 ns tSV CS to Status Valid -- 400 -- 200 -- 200 ns tDF CS to Dout in 3-state -- 200 -- 100 -- 100 ns tWP Write Cycle Time -- 10 -- 5 -- 5 ms Symbol Parameter fSCK Notes: [1] [2] [1] The parameters are characterized but not 100% tested. [2] AC measurement conditions: Unit CL = 100 pF Input pulse voltages: Per VIL and VIH spec Input rise and fall times: 10 ns Timing reference voltages: half VCC level Giantec Semiconductor, Inc. A0 www.giantec-semi.com 11/17 GT93C56A 7. Ordering Information Industrial Grade: -40C to +85C, Lead-free Voltage Range Part Number* Package (8-pin)* 1.8V to 5.5V GT93C56A-2GLI-TR 150-mil SOIC/SOP (JEDEC) GT93C56A-2ZLI-TR 3 x 4.4 mm TSSOP GT93C56A-2UDLI-TR 2 x 3 x 0.55 mm UDFN * 1. Contact Giantec Sales Representatives for availability and other package information. 2. The listed part numbers are packed in tape and reel -TR (4K per reel). UDFN is 5K per reel. 3. Refer to Giantec website for related declaration document on lead free, RoHS, halogen free or Green, whichever is applicable. 4. Giantec offers Industrial grade for Commercial applications (0C to +70C). Giantec Semiconductor, Inc. A0 www.giantec-semi.com 12/17 GT93C56A 8. Top Markings 8.1 GT93C56A-2GLI-TR (SOIC/SOP Package) : Giantec Logo 356A-2GLI: Part Number GT93C56A-2GLI 036: Date Code, year 2010, ww36 8.2 GT93C56A-2ZLI-TR (TSSOP Package) GT: Giantec Logo 356A-2ZLI: Part Number, GT93C56A-2ZLI 036: Date Code, year 2010, ww36 8.3 GT93C56A-2UDLI-TR (UDFN Package) GT: Giantec Logo 31A: Part Number, GT93C56A-2UDLI 036: Date Code, year 2010, ww36 Giantec Semiconductor, Inc. A0 www.giantec-semi.com 13/17 GT93C56A 9 Package Information 9.1 SOIC/SOP (JEDEC) Giantec Semiconductor, Inc. A0 www.giantec-semi.com 14/17 GT93C56A 9.2 TSSOP Giantec Semiconductor, Inc. A0 www.giantec-semi.com 15/17 GT93C56A 9.3 UDFN: Ultra-thin DFN Giantec Semiconductor, Inc. A0 www.giantec-semi.com 16/17 GT93C56A 10. Revision History Revision Date Descriptions A0 Nov. 2010 Initial version Giantec Semiconductor, Inc. A0 www.giantec-semi.com 17/17