NT5DS4M32EG 4Mx32 Double Data Rate SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM With Bi-directional Data Strobe and DLL (144-Ball FBGA) Nanya Technology Corp. NTC reserves the right to change products or specification without notice. REV 1.1 Oct 05, 2005 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM TABLE OF CONTENTS Table of Contents Timing - 2 - 31 Memory Part Numbering - 3 Basic Timing(@BL=2, CL=3) General Description & Device Features - 4 Multi Bank Interleaving Read(@BL=4,CL=3) Pin Configuration & Pin Description - 5 Multi Bank Interleaving Write(@BL=4,CL=3) - 33 Input/Output Functional Description - 6 Auto Precharge after Read Burst(@BL=8) - 34 Functional Block Diagram - 7 Auto Precharge after Write Burst(@BL=4) - 35 Simplified State Diagram - 8 Normal Write Burst(@BL=4) - 36 Functional Description - 9 Write Interrupt by Precharge & DM(@BL=8) - 37 Power up Sequence - 9 Read Interrupt by Precharge(@BL=8) - 38 Mode Register Set(MRS) - 10 Read Interrupt by Burst Stop & Write(@BL=8,CL=3) - 39 Extended Mode Register Set - 11 Read Interrupt by Read(@BL=8,CL=3) - 40 Burst Mode Operation - 12 DM Function only for Write(@BL=8) - 41 Burst Length & Sequence - 12 Power up Sequence & Auto Refresh(CBR) - 42 Bank Activation Command - 12 Mode Register Set - 43 Burst Read Operation - 13 I/V Characteristics for Input and Output Buffer - 44 Burst Write Operation - 13 Reduced Output Driver Characteristics - 45 Burst Interruption - 14 Impedance Match Output Driver Characteristics - 46 Read Interrupt by Read - 14 Read Interrupt by Burst Stop & Write - 14 Read Interrupt by Precharge - 15 Write Interrupt by Write - 15 Write Interrupt by Read & DM - 16 Write Interrupt by Precharge & DM - 18 DM Function - 18 Auto Precharge Operation - 19 Write with Auto Precharge - 20 - 20 Auto Refresh - 21 Self Refresh - 21 Power Down Mode - 22 - 23 Power & DC Operating Conditions - 23 DC Characteristics - 24 AC Input Operating Conditions - 24 AC Operating Test Conditions - 25 Capacitance - 25 Decoupling Capacitance Guide Line - 25 AC Characteristics(I) - 26 AC Characteristics(II) - 27 Simplified Truth Table - 28 Functional Truth Table - 29 Functional Truth Table for CKE - 30 REV 1.1 Oct 05, 2005 - 47 - 19 Precharge Command Absolute Maximum Ratings - 32 - 17 Burst Stop Command Read with Auto Precharge Package Dimension(FBGA) - 31 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM 1M x32Bit x4Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL GENERAL DESCRIPTION For 1M x 32Bit x 4 Bank DDR SDRAM The NT5DS4M32EG is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os. Synchronous features with Data Strobe allow extremely high performance up to 400M bps/pin. I/O transactions are possible on both edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. FEATURES * Data I/O transaction on both edges of Data strobe * VDD = 2.5V5% , VDDQ = 2.5V5% * 4 DQS (1 DQS/Byte) * SSTL_2 compatible inputs/outputs * DLL aligns DQ and DQS transaction with Clock * 4 banks operation transaction * MRS cycle with address key programs * Edge aligned data & data strobe output -. CAS latency 2,3 (clock) * Center aligned data & data strobe input -. Burst length (2, 4, 8 and Full page) * DM for write masking only -. Burst type (sequential & interleave) * Auto & self refresh * Full page burst length for sequential burst type only * 32ms refresh period (4K cycle) * Start address of the full page burst should be even * 144-Ball FBGA package * All inputs except data & DM are sampled at the rising * Maximum clock frequency up to 200MHz edge of the system clock * Maximum data rate up to 400Mbps/pin * Differential clock input(CK & /CK) * Available as Lead-free and Halogen-free products ORDERING INFORMATION Max Freq. Part NO. Max Data Rate CL=3 CL=2 NT5DS4M32EG-5G* 200MHz 111Mhz 400Mbps/pin NT5DS4M32EG-5* 200Mhz - 400Mbps/pin NT5DS4M32EG-6* 166Mhz - 333Mbps/pin Interface Package SSTL_2 144-Ball FBGA * Lead-free and Halogen-free product REV 1.1 Oct 05, 2005 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM PIN CONFIGURATION (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 A DQS0 DM0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ DM3 DQS3 B DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27 C DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 D DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24 E DQ17 DQ16 VDDQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VDDQ DQ15 DQ14 F DQ19 DQ18 VDDQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VDDQ DQ13 DQ12 G DQS2 DM2 NC VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ NC DM1 DQS1 H DQ21 DQ20 VDDQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VDDQ DQ11 DQ10 J DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8 K /CAS /WE VDD VSS A10 VDD VDD RFU1 VSS VDD NC NC L /RAS NC NC BA1 A2 A11 A9 A5 RFU2 CK /CK MCL M /CS NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF NOTE : 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. VSS Thermal balls are optional PIN Description CK, /CK Differential Clock Input CKE Clock Enable /CS Chip Select /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DQS Data Strobe DM RFU Data Mask REV 1.1 Oct 05, 2005 BA0, BA1 A0 ~ A11 DQ0 ~ DQ31 VDD VSS VDDQ VSSQ MCL Bank Select Address Address Input Data Input/Output Power Ground Power for DQ's Ground for DQ's NC Reserved for Future Use 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type CK, /CK# Input The differential system clock inputs. All of the input are sampled on the rising edge of the clock except DQ's and DM's that are sampled on both edges of the DQS. CKE Input CKE high activates and CKE low deactivates the internal clock,input buffers and output drivers. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. /CS Input /CS enables(registered Low) and disables(registered High) the command decoder. When /CS is registered High,new commands are ignored but previous operations are continued. /RAS Input Latches row addresses on the positive going edge of the CK with /RAS low. Enables row access & precharge. /CAS Input Latches Column addresses on the positive going edge of the CK with /CAS low. Enables column access. /WE Input Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. DQS0 ~DQS3 Input,Output DM0 ~ DM3 Input DQ0 ~ DQ31 Input,Output BA0, BA1 Input Select which bank is to be active. A0 ~ A11 Input Row,Column addresses are multiplexed on the same pin. Row address : RA0 ~ RA11, Column address : CA0 ~ CA7. Column address CA8 is used for auto precharge. VDD,VSS Power Supply Power and ground for the input buffers and core logic. VDDQ,VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. NC/RFU MCL # No Connection/ Reserved for future use NC Function Data inputs and outputs are synchronized with both edge of DQS. DQS0 for DQ0~DQ7, DQS1 for DQ8~DQ15, DQS2 for DQ16~DQ23, DQS3 for DQ24~DQ31 Data-In mask. Data-In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. Data inputs and outputs are multiplexed on the same pins. This pin is recommended to be left "No Connection" on the device Not internally connected : The timing reference point for the differential clocking is the cross point of CK and /CK. For any applications using the single ended clocking, apply VREF to /CK pin. REV 1.1 Oct 05, 2005 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM FUNCTIONAL BLOCK DIAGRAM (1Mbit x 32 I/O x 4 Bank) 32 Input Buffer I/O Control CK, /CK Data Input Register Serial to parallel LWE LDMi Bank Select 64 1M x 32 32 Output Buffer 1M x 32 64 2-bit prefetch Sense AMP ADDR Row Decoder Refresh Counter Row Buffer Address Register CK,/CK 1M x 32 x32 DQi 1M x 32 Column Decoder Column Buffer LCBR LRAS * Latency & Burst Length Strobe Gen. Programming Register LCKE LRAS LCBR LWE LWCBR LCAS DLL Data Strobe (DQS0~DQS3) LDMi CK,/CK Timing Register CK,/CK REV 1.1 Oct 05, 2005 CKE /CS /RAS /CAS /WE DMi 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM SIMPLIFIED STATE DIAGRAM SELF REFRESH F RE S F RE MODE SX MRS AUTO REFA IDLE REGISTER REFRESH SET CK EL CK EH ACT POWER DOWN POWER DOWN CK EL CK EH ROW ACTIVE BS T WRITE READ WRITEA READA READ WRITE READ WRITE WRITEA READA WRITEA READA WRITE A READ A PRE E PR E PR POWER APPLIED POWER PRE PRE- ON CHARGE Automatic Sequence Command Sequence WRITEA : Write with Autoprecharge READA : Read with Autoprecharge REV 1.1 Oct 05, 2005 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM FUNCTIONAL DESCRIPTION Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VREF & VTT 2. Start clock and maintain stable condition for minimum 200s 3. The minimum of 200s after stable power and clock (CK,/CK), apply NOP and CKE to be high. 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 Every "DLL Enable" command resets DLL. Therefore sequence 6 can be skipped during power-up. Instead of it, the additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6 & 7 is regardless of the order. Power-Up & Initialization Sequence /CK CK 2Clock min. tRP Command Precharge ALL Banks EMRS MRS DLL Reset 2Clock min. tRP Precharge ALL Banks Input must be stable for 200us REV 1.1 Oct 05, 2005 tRFC 1st Auto Refresh tRFC 2nd Auto Refresh 2Clock min. Mode Register Set Any Command 200 Clock min. 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs /CAS latency, address mode, burst length, test mode, DLL reset and various vendor specific option to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0,BA1 in the same cycle as /CS, /RAS, /CAS and /WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, address mode uses A3, /CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL for DLL reset. A7, A8, BA0, and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, address modes and /CAS latencies. BA1 BA0 RFU 0 A11 A10 A9 RFU A8 A7 DLL TM A6 A5 A4 A3 /CAS Latency A2 BT A1 Address Bus A0 Mode Register Burst Length Burst Type DLL Test Mode A8 DLL Reset A7 Mode 0 No 0 Normal 1 Yes 1 Test A3 Type 0 Sequential 1 Interleave Burst Length /CAS Latency A2 A1 A0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 1 0 1 1 1 BA0 Mode A6 A5 A4 Latency 0 MRS 0 0 0 1 EMRS 0 0 0 * RFU(Reserved for future use) should stay "0" during MRS cycle. Burst Type Sequential Interleave 0 Reserved Reserved 0 1 2 2 0 1 0 4 4 3 0 1 1 8 8 0 Rreserved 1 0 0 Reserved Reserved 0 1 Reserved 1 0 1 Reserved Reserved 1 0 Reserved 1 1 0 Reserved Reserved 1 1 Reserved 1 1 1 Full page Reserved 7 8 MRS Cycle /CK 0 1 2 3 4 5 6 CK Command NOP Precharge All Banks NOP NOP MRS * 1 tRP * 2 NOP Any Command NOP NOP tMRD = 2 tCK * 1 : MRS can be issued only at all banks precharge state. * 2 : Minimum tRP is required to issue MRS command. REV 1.1 Oct 05, 2005 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Extended Mode Register Set (EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0,A2~A5, A7~A11 and BA1 in the same cycle as /CS,/RAS,/CAS and /WE going low are written in the extended mode register. A1and A6 are used for setting driver strength to weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state A0 is used for DLL enable or disable."High"on BA0 is used for EMRS. All the other address pins except A0,A1, A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 RFU 1 A11 A10 A9 A8 A7 A6 A1 A0 RFU DIC DLL Output Driver Impedance Control A0 RFU A5 A4 DIC A3 A2 Address Bus Extended Mode Register BA0 Mode A6 A1 0 MRS 0 1 Weak 60% of full drive strength 0 DLL Enable Enable 1 EMRS 1 1 Matched impedance 30% of full drive strength 1 Disable * RFU(Reserved for Future Use) should stay "0" during MRS cycle. LOW Frequency Operation Mode DLL DISABLE MODE /CK CK 2Clock min. tRP Command Precharge ALL Banks EMRS Enter DLL Disable Mode DLL Disable Mode 2Clock min. MRS*1 Precharge ALL Banks CMD 2Clock min. tRP EMRS 2Clock min. MRS DLL RESET Exit DLL Disable Mode CL=2/3 BL=2/4/8 2Clock min. MRS Active Read*2 200 Clock min. Notes: - DLL disable mode is operating mode for low operating frequency between 143MHz ~ 83MHz without DLL. - This DLL disable mode is useful for power saving. - All banks precharge or a bank precharge command can omit before entering and exiting DLL disable mode. *1 : CL=2 & 3 and BL can set any burst length at DLL disable mode. *2 : A Read command can be applied as far as tRCD is satisfied after any bank active command. And it needs an additional 200 clock cycles for read operation after exiting DLL disable mode. REV 1.1 Oct 05, 2005 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory location (write cycle), or from memory location (read cycle). There are two parameters that define how the burst mode operates. These parameters including burst sequence and burst length are programmable and determined by address A0 ~ A3 during the Mode Register Set command. The burst type is used to define the sequence in which the burst data will be delivered or stored to the DDR SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the below table. The burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. The burst length can be programmed to have values of 2,4,8 or full page. For the full page operation, the starting address must be an even number and the burst stop at the end of burst. Burst Length and Sequence Burst Length Starting Address(A2,A1,A0) Sequential Mode Interleave Mode xx0 0-1 0-1 xx1 1-0 1-0 x00 0-1-2-3 0-1-2-3 x01 1-2-3-0 1-0-3-2 x10 2-3-0-1 2-3-0-1 x11 3-0-1-2 3-2-1-0 000 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 010 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 011 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 110 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 n = A0 - A7, A0 = 0 Cn, Cn+1, Cn+2, ..., Cn-1 Not supported 2 4 8 Full Page (256) Bank Activation Command The Bank Activation command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The DDR SDRAM has four independent Banks, so two Bank Select Addresses(BA0, BA1) are supported. The Bank Activation command must be applied before any Read or Write operation is executed.The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of /RAS to /CAS delay time(tRCDR/tRCDW min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation commands(Bank A to B and vice versa) is the Bank to Bank delay time (tRRD min). Bank Activation Command Cycle ( /CAS Latency = 3 ) 0 1 2 n n+1 n+2 /CK CK Address Bank A Row Addr. Bank A Col. Addr. Bank A Activate NOP NOP READ A with Auto Precharge Row cycle Time (tRC) REV 1.1 Oct 05, 2005 Bank B Row Addr. /RAS-/RAS delay time(tRRD) /RAS-/CAS delay time(tRCDR for READ) Command Bank A Row Addr. Bank A Activate NOP Bank B Activate : Don't care 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the burst read command is issued by asserting /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock after tRCD from the bank activation. The address inputs (A0~A7) determine the starting address for the Burst. The Mode Register sets type of burst (Sequential or interleave) and burst length(2,4,8, Full page). The first output data is available after the /CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe adopted by DDR SDRAM until the burst length is completed. < Burst Length = 4, /CAS Latency = 3 > 0 1 3 2 4 5 6 8 7 /CK CK Command READ NOP NOP NOP NOP NOP NOP NOP tRPST tRPRE DQS NOP /CAS Latency = 3 DQ's Dout 0 Dout 1 Dout 2 Dout 3 Burst Write Operation The Burst Write command is issued by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no real write latency required for burst write cycle. The first data for burst write cycle must be applied at the first rising edge of the data strobe enabled after tDQSS from the rising edge of the clock that the write command is issued.The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. < Burst Length = 4 > 0 1 3 2 4 5 6 7 8 /CK CK Command DQS DQ's REV 1.1 Oct 05, 2005 NOP WRITEA NOP WRITEB tDQSSmax tWPREH tWPRES NOP NOP NOP NOP NOP tWPST Din a0 Din a1 Din a2 Din a3 Din b0 Din b1 Din b2 Din b3 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Burst Interruption Read Interrupted by Read Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining address are overridden by the new address with the full burst length. The data from the previous Read command continues to appear on the outputs until the /CAS latency from the interrupting Read command is satisfied. Read to Read interval is minimum 1 tCK. < Burst Length = 4, /CAS Latency = 3 > 0 1 READ A READ B 3 2 4 5 6 8 7 /CK CK Command NOP NOP NOP NOP NOP NOP NOP DQS /CAS Latency = 3 DQ's Douta0 Douta1 Doutb0 Doutb1 Doutb2 Doutb3 Read Interrupted by Burst stop & Write To interrupt Burst Read with a write command, Burst stop command must be asserted to avoid data contention on the I/O bus by placing the DQ's(Output drivers) in a high impedance state at least one clock cycle before the Write Command is initiated. Once the burst stop command has been issued, the minimum delay to a write command is CL(RU). [CL is /CAS Latency and RU means round up to the nearest integer.] < Burst Length = 4, /CAS Latency = 3 > 0 1 3 2 4 5 6 8 7 /CK CK Command DQS /CAS Latency = 3 DQ's REV 1.1 Oct 05, 2005 READ Burst stop NOP NOP NOP WRITE NOP NOP tDQSS tWPREH tRPRE tWPRES Preamble Dout0 Dout1 Din 0 Din 1 Din 2 Din 3 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Read Interrupted by Precharge Burst Read can be interrupted by precharge of the same bank. The minimum 1 clock cycle is required for the read precharge interval. Precharge command to output disable latency is equivalent to the /CAS latency. < Burst Length = 8, /CAS Latency = 3 > 0 1 2 3 4 5 6 8 7 /CK CK 1tCK Command READ Precharge NOP NOP NOP NOP NOP NOP tRPST tRPRE DQS NOP /CAS Latency = 3 DQ's Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 Interrupted by prechagre Read followed by Write Read followed by write operation in the same or different bank is possible as below picture. Following first Read command, consecutive Write command can be initiated after CL+BL/2 clock. In other words, minimum earlist possible Write command that does not interrupt the previous read data can be issued after CL+BL/2 clock is met. < Burst Length = 8, /CAS Latency = 3 > 0 1 2 3 4 5 6 7 8 9 10 NOP NOP NOP NOP WRITE NOP NOP NOP /CK CK Command READ NOP NOP DQS DQ's Dout0 Dout1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Read followed by write command latency BL2 BL4 BL8 CL2 3 4 6 CL3 4 5 7 REV 1.1 Oct 05, 2005 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Write Interrupted by Write Burst Write can be interrupted by the new Write Command before completion of the previous burst write, with the onlyrestriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new addresses and data will be written into the device until the programmed burst length is satisfied. < Burst Length = 4 > 0 1 2 3 4 5 6 8 7 /CK CK 1tCK Command NOP WRITEA WRITEB NOP NOP NOP NOP NOP NOP tWPREH DQS /CAS Latency = 3 tWPRES DQ's Din a0 Din a1 Din b0 Din b1 Din b2 Din b3 Write Interrupted by Read & DM A burst write can be interrupted by a read command of any bank. The DQ's must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of the write command. < Burst Length = 8 > 0 1 2 3 4 5 6 7 8 /CK CK Command WRITE NOP NOP NOP NOP READ NOP NOP NOP tWTR tDQSSmax DQS /CAS Latency=3 tWPRES DQ's Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout0 Dout1 DM tWTR tDQSSmin DQS /CAS Latency=3 tWPRES DQ's Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout0 Dout1 DM REV 1.1 Oct 05, 2005 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Write Interrupted by Precharge & DM A burst Write can be interrupted by a precharge of the same bank before completion of the previous burst. A write recovery time(tWR) is required from the last data to precharge command. When Precharge command is asserted, any residual data from the burst write cycle must be masked by DM. < Burst Length = 8 > 0 1 2 3 4 5 6 8 7 /CK CK Command NOP WRITE A NOP NOP NOP NOP Precharge NOP tWR tDQSSmax tDQSSmax DQS tWPREH tWPREH tWPRES Max tDQSS WRITE B DQ's tWPRES Din a0 Din a1 Din a2 Din a3 Din a4 Din a5 Din a6 Din a7 DM tWR tDQSSmin Din a0 Din a1 tDQSSmin DQS tWPREH tWPREH tWPRES tWPRES Min tDQSS DQ's Din a0 Din a1 Din a2 Din a3 Din a4 Din a5 Din a6 Din a7 Din b0 Din b1 Din b2 DM REV 1.1 Oct 05, 2005 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM BURST STOP COMMAND The Burst stop command is initiated by having /RAS and /CAS high with /CS and /WE low at the rising edge of the clock only. The Burst Stop command has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. When the Burst Stop command is issued during a burst read cycle, both the data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the /CAS Latency set in the Mode Register. The Burst Stop command, however, is not supported during a write burst operation. < Burst Length = 4, /CAS Latency = 3 > 0 1 2 3 4 5 6 7 8 /CK CK 1tCK Command Burst Stop READ NOP NOP NOP NOP NOP NOP NOP DQS /CAS Latency = 3 The burst ends after a delay equal to the /CAS Latency DQ's Dout 0 Dout 1 DM FUNCTION The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle. When the Data Mask is activated (DM high) during write operation, the write data is masked immediately (DM to Data-mask Latency is Zero). DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge. < Burst Length = 8 > 0 1 2 3 4 5 6 7 8 /CK CK Command WRITE NOP NOP NOP NOP NOP NOP NOP NOP tDQSS DQS DQ's tWPREH tWPRES Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 DM DM Masked by DM=H REV 1.1 Oct 05, 2005 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM AUTO-PRECHARGE OPERATION The Auto precharge command can be issued by having column address A8 High when a Read or a Write command is asserted into the DDR SDRAM. If A8 is low when Read or Write command is issued, normal Read or Write burst operation is asserted and the bank remains active after the completion of the burst sequence. When the Auto precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during read or write cycle after tRAS(min) is satisfied. Read with Auto Precharge If a Read with Auto-precharge command is initiated, the DDR SDRAM automatically starts the precharge operation on 2 clock previous to the end of burst from a Read with Auto-Precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. The bank started the Precharge operation once cannot be reactivated and the new command can not be asserted until the Precharge time(tRP) is satisfied. < Burst Length = 8, /CAS Latency = 3 > 0 1 2 3 4 5 6 8 7 /CK CK BANK A ACTIVE Command NOP NOP READ A Auto Precharge NOP NOP NOP NOP NOP tRCDR(min) * Bank can be reactivated at tRP completion of tRP tRAS(min) DQS /CAS Latency = 3 DQ's Douta0 Douta1 Douta2 Douta3 Douta4 Douta5 Auto-Precharge start point tRC(min) When the Read with Auto precharge command is issued, new command can be asserted at T5,T6 and T7 respectively as follows. Asserted command *1 For same Bank For Different Bank 5 6 7 5 6 7 READ READ + No AP*1 READ + No AP Illegal Legal Legal Legal READ+AP READ + AP READ + AP Illegal Legal Legal Legal Active Illegal Illegal Illegal Legal Legal Legal Precharge Legal Legal Illegal Legal Legal Legal : AP = Auto Precharge REV 1.1 Oct 05, 2005 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Write with Auto Precharge If A8 is high when Write command is issued, the write with Auto-Precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). < Burst Length = 4, /CAS Latency = 3 > 0 1 2 3 4 5 6 7 8 /CK CK BANK A ACTIVE Command NOP WRITE A Auto Precharge NOP NOP NOP NOP NOP NOP tWPREH DQS tWPRES /CAS Latency = 3 DQ's * Bank can be reactivated at completion of tRP Din a0 Din a1 Din a2 Din a3 tWR tRP Internal precharge starts Asserted command For same Bank For Different Bank 3 4 5 6 7 8 3 4 5 6 7 WRITE WRITE + No AP *1 WRITE + No AP WRITE + No AP Illegal Illegal Illegal Legal Legal Legal Legal Legal WRITE + AP WRITE + AP WRITE + AP WRITE+AP Illegal Illegal Illegal Legal Legal Legal Legal Legal READ Illegal READ + No AP + DM *2 READ + No AP + DM READ + No AP READ + No AP Illegal Illegal Illegal Illegal Legal Legal READ + AP Illegal READ + AP + DM READ + AP + DM READ + AP READ + AP Illegal Illegal Illegal Illegal Legal Legal Active Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal Precharge Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal *1 AP *2 DM = Auto Precharge : Refer to "Write Interrupted by Rean & DM" in page 16. REV 1.1 Oct 05, 2005 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM PRECHARGE COMMAND The precharge command is issued when /CS, /RAS, and /WE are low and /CAS is high at the rising edge of the clock, CK. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The Bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied from the start of the last burst write cycle until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. < Bank Selection for Precharge by Bank address bits > A8/AP BA1 BA0 Precharge 0 0 0 Bank A Only 0 0 1 Bank B Only 0 1 0 Bank C Only 0 1 1 Bank D Only 1 X X All Banks AUTO REFRESH An Auto Refresh command is issued by having /CS, /RAS and /CAS held low with CKE and /WE high at the rising edge of the clock, CK. All banks must be precharged and idle for a tRP(min) before the Auto Refresh command is applied. The refresh addressing is generated by the internal refresh address counter. This makes the address bits "Don't care" during an Auto Refresh command. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the tRFC(min). 0 1 2 3 4 5 6 7 8 9 10 11 /CK CK Command Auto Refresh Precharge ALL Banks CMD CKE=High tRP REV 1.1 Oct 05, 2005 tRFC 20 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM SELF REFRESH A self refresh command is defined by having /CS, /RAS, /CAS and CKE low with /WE high at the rising edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSR for locking of DLL. /CK CK Command Precharge All Bank Self Refresh Active Read tIS CKE tXSA *1 tXSR *2 *1 Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after any bank active command. *2 Exit self refresh to read command. POWER DOWN MODE The power down is entered when CKE Low, and exited when CKE High. Once the power down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce power consumption. The all banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tCK+tIS prior to Row active command. During power down mode, refresh operations can't be performed, therefore the device cannot remain in power down mode longer than the refresh period(tREF) of the device. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 /CK CK Command Precharge Precharge power down Entry Precharge power down Exit Active Active power down Entry NOP Active power down Exit NOP CKE tPDEX tIS REV 1.1 Oct 05, 2005 Read tIS tIS tIS 21 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage Temperature TSTG -55 ~ +150 C Power dissipation PD 2.0 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out) Recommended operating conditions (Voltage referenced to Vss=0V, TA=0 to 70C) Parameter Symbol Min Typ Max Unit Note Device supply Voltage VDD 2.375 2.50 2.625 V 1 Output supply Voltage VDDQ 2.375 2.50 2.625 V 1 Reference Voltage VREF 0.49* VDDQ - 0.51* VDDQ V 2 Termination Voltage Vtt VREF -0.04 VREF VREF +0.04 V 3 Input logic high Voltage VIH VREF +0.15 - VDDQ +0.30 V 4 Input logic low Voltage VIL -0.30 - VREF -0.15 V 5 Output logic high current IOH -15.2 - - mA 7 Output logic low current IOL 15.2 - - mA 8 II -5 - 5 uA 6 IOZ -5 - 5 uA 9 Input leakage current Output leakage current Note : 1. For -25/-28/-33/-36/-4/-5, VDD / VDDQ = 2.5V 5% / 2.5V 5% 2. VREF is expected to equal 0.50* VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed 2% of the DC value. Thus, from 0.50* VDDQ, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.) = VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. VIL(mim.) =-1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V VIN VDD is acceptable. For all other pins that are not under test VIN = 0V. 7. VOH (Output logic high Voltage(min)) = Vtt(min) + 0.76 8. VOL (Output logic low Voltage(max)) = Vtt(max) - 0.76 9. DQs are disabled; 0V VOUT VDDQ REV 1.1 Oct 05, 2005 22 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to Vss=0V, VDD/VDDQ=2.5V5%/ 2.5V5%,, TA=0 to 70C) Version Parameter Symbol Test Condition Unit Note -5 Icc1 Burst Length=2, tRC tRC(min) IOL=0mA, tCK=tCK(min) 160 mA Precharge Standby Current in Power-down mode Icc2P CKE VIL(max), tCK=tCK(min) 15 mA Precharge Standby Current in Non Power-down mode Icc2N CKE VIH(min), /CS VIH(min), tCK=tCK(min). 40 mA Active Standby Current in Power-down mode Icc3P CKE VIL(max), tCK=tCK(min) 17 mA Active Standby Current in Non Power-down mode Icc3N CKE VIH(min), /CS VIH(min), tCK=tCK(min). 70 mA Operating current (One Bank Active) Operating Current (Burst mode) Icc4 IOL=0mA, tCK=tCK(min), Page Burst, All Banks activated. 420 mA Auto Refresh current Icc5 tRC tRFC(min) 200 mA Self Refresh current Icc6 CKE 0.2V 6 mA Operating Current (4Bank Interleaving) Icc7 Burst Length=4, tRC tRC(min) IOL=0mA, tCK=tCK(min) 560 mA 1 2 Notes : 1. Measured with outputs open. 2. Refresh period is 32ms. AC INPUT OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to Vss=0V, VDD/VDDQ=2.5V5%/ 2.5V5%,, TA=0 to 70C) Parameter Symbol Min Typ Max Unit Note Input High (Logic1) Voltage : DQ VIH VREF+0.35 - - V Input Low (Logic0) Voltage : DQ VIL - - VREF -0.35 V Clock input Differential Voltage ; CK and /CK VID 0.7 - VDDQ+0.6 V 1 Clock input Crossing point Voltage ; CK and /CK VIX 0.5* VDDQ -0.2 - 0.5* VDDQ +0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK 2. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variation in the DC level of the same REV 1.1 Oct 05, 2005 23 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM AC OPERATING TEST CONDITIONS (VDD=2.5V0.125V, TA=0 to 70C) Parameter Value Unit 0.50* VDDQ V CK and /CK signal maximum peak swing 1.5 V CK signal minimum slew rate 1.0 V/ns VREF+0.35 / VREF-0.35 V VREF V Vtt V Input reference voltage for CK (for signal ended) Input levels (VIH/VIL) Input timing measurement refrence level Output timing measurement refrence level Output load condition Note See Fig.1 Vtt=0.5*VDDQ O RT=50 Output O n Z0=50 VREF =0.5*VDDQ CLOAD=20pF Fig.1) Output Load Circuit CAPACITANCE (VDD=2.5V, TA=25C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance(CK, /CK,) CIN1 2.0 3.0 pF Input capacitance (A0~A11, BA0~BA1) CIN2 2.0 3.0 pF Input capacitance (CKE, /CS, /RAS, /CAS, /WE) CIN3 2.0 3.0 pF Data & DQS input/output capacitance (DQ0~DQ31) COUT 4.0 5.0 pF Input capacitance (DM0 ~ DM3) CIN4 4.0 5.0 pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit Decoupling Capacitance between VDD and VSS CDC1 0.1+0.01 uF Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1+0.01 uF Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other. All VSS pins are connected in chip. All VSSQ pins are connected in chip. REV 1.1 Oct 05, 2005 24 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM AC CHARACTERISTICS(I) Parameter Symbol CL=3 -5G -5 -6 Min Max Min Max Min Max Unit Note 5.0 12 5.0 12 6.0 12 ns 2,3 tCK 9.0 12 - - - - ns 2,3 CK high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQS out access time from CK tDQSCK -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns Output access time from CK tAC -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns Data strobe edge to Dout edge tDQSQ - +0.45 - +0.45 - +0.45 ns Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.8 1..2 0.8 1..2 0.8 1..2 tCK DQS-in setup time tWPRES 0 - 0 - 0 - ns DQS-in hold time tWPREH 0.30 - 0.30 - 0.30 - tCK DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS-in high level width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS-in low level width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 tCK Address and Control input setup tIS 1.0 - 1.0 - 1.0 - ns Address and Control input hold tIH 1.0 - 1.0 - 1.0 - ns DQ and DM setup time to DQS tDS 0.45 - 0.45 - 0.45 - ns DQ and DM hold time to DQS tDH 0.45 - 0.45 - 0.45 - ns Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns 1 Data output hold time from DQS tQH - ns 1 CK cycle time CL=2 tHP -0.45 tHP - -0.45 - tHP -0.45 1 Note 1: -. The JEDEC DDR specification currently defines the output data valid window(tDV) as the period when the data strobe and all data associated with that data strobe are coincidentally valid. -. The previously used definition of tDV(=0.35tDK) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applied to the device is better than 45/55% -. A new AC timing term,tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax Note 2 (refer to page 11) -. For Low frequency operation without DLL (143MHz~83MHz) in CL2/3, also can set DLL disable mode for power saving. Note 3 -. Under set DLL disable mode by EMRS, -. The tDQSCK can be 0.0ns in 100MHz operation. (-10) -. The tDQSCK can be +3.0ns in 143MHz operation. (-7) -. The tDQSCK can be -2.0ns in 66MHz operation. (-12) REV 1.1 Oct 05, 2005 25 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM AC CHARACTERISTICS(II) Parameter Symbol -5G -5 -6 Min Max Min Max Min Max Unit Note Row cycle time tRC 60 - 60 - 60 - ns Refresh cycle time tRFC 70 - 70 - 70 - ns Row active time tRAS 40 100K 40 100K 40 100K ns /RAS to /CAS delay for Read tRCDR 18 - 18 - 18 - ns /RAS to /CAS delay for Write tRCDW 10 - 10 - 10 - ns Row precharge time tRP 18 - 18 - 18 - ns Row active to Row active tRRD 2 - 2 - 2 - tCK Last data in to Row precharge(@Normal) tWR 2 - 2 - 2 - tCK 1 Last data in to Row precharge(@Auto) tWR_A 2 - 2 - 2 - tCK 1 Internal Write in to Read command tWTR 2 - 2 - 2 - tCK 1 Col. address to Col. address tCCD 1 - 1 - 1 - tCK Mode register set cycle time tMRD 2 - 2 - 2 - tCK tDAL 6 - 6 - 6 - tCK Auto precharge write recovery + Precharge Exit self refresh to active command tXSA 75 - 75 - 75 - ns Exit self refresh to read command tXSR 200 - 200 - 200 - tCK Power down exit time tPDEX 1tCK + tIS - 1tCK + tIS - 1tCK + tIS - ns Refresh interval time tREF 7.8 - 7.8 - 7.8 - us Note 1 1. For normal write operation, even numbers of Din are to be written inside DRAM -. AC parameters for DLL Disable Mode(143MHz ~ 83MHz, CL2/3 Only). REV 1.1 Oct 05, 2005 26 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM SIMPLIFIED TRUTH TABLE COMMAND Register CKEn-1 CKEn /CS /RAS /CAS /WE DM Extended Mode Register H X L L L L X OP CODE Mode Register Set H X L L L L X OP CODE L L L H X X L H H H H X X X X X Auto Refresh Refresh Entry Self Refresh Exit Bank Active & Row Address Read & Column Addr. Auto Precharge Disable Write & Column Addr. Auto Precharge Disable Auto Precharge Enable Auto Precharge Enable Burst Stop Precharge Bank Selection H L L H H X L L H H X V H X L H L H X V H X L H L L X H X L H H L X H All Banks Active Power Down H X Entry H L Exit L H Entry H L Exit L H Precharge Power Down Mode DM No Operation Command BA0,1 L L H L H X X X L V V V X X X X H X X X L H H H H X X X H H H L H H X X H X X X L H H H X X V A8 /AP A11~A9, A7~A0 Note 1,2 3 3 3 3 Row Address L Column Address H L Column Address H X V L X H 4 4 4 4,6 7 X 5 X X X X X V X X X 8 ( V=Valid, X=Don't care, H=Logic High, L=Logic Low ) Note : 1. OP CODE : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program Keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state A new command can be issued after 2 clock cycle of EMRS/MRS 3. Auto refresh function are as same as CBR refresh of DRAM. The automatic precharge without row precharge command is meant by "Auto". Auto/Self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A8/AP is "high" at row precharge ,BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges(Write DM latency is 0). REV 1.1 Oct 05, 2005 27 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM FUNCTION TRUTH TABLE Current State IDLE ROW ACTIVE /CS /RAS /CAS /WE Address Command Action H X X X X DESEL NOP L H H H X NOP NOP L H H L X TERM NOP L H L X BA0, CA, A8 READ/WRITE ILLEGAL*2 L L H H BA, RA ACT Bank Active, Latch RA L L H L BA, A8 PRE/PREA NOP*4 L L L H X REFA AUTO-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 H X X X X DESEL NOP L H H H X NOP NOP L H H L X TERM NOP L H L H BA, CA, A8 READ/READA Begin Read, Latcch CA, Determine Auto-Precharge L H L L BA, CA, A8 WRITE/WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A8 PRE/PREA Precharge/Precharge All L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END) L H H L X TERM Terminate Burst L H L H BA, CA, A8 READ/READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 L H L L BA, CA, A8 WRITE/WRITEA ILLEGAL L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A8 PRE/PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END) L H H L X TERM ILLEGAL L H L H BA, CA, A8 READ/READA ILLEGAL L H L L BA, CA, A8 WRITE/WRITEA Terminate Burst, Latch CA, Begin new Write, Determine Precharge*3 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A8 PRE/PREA Terminate Burst with DM=high precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END) L H H L X TERM ILLEGAL L H L X BA, CA, A8 READ/WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A8 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ WRITE READ with AUTO PRECHARGE REV 1.1 Oct 05, 2005 28 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM FUNCTION TRUTH TABLE (continued) Current State WRITE with AUTO PRECHARGE PRECHARGING ROW ACTIVATING WRITE RECOVERING REFRESHING /CS /RAS /CAS /WE Address Command Action H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END) L H H L X TERM ILLEGAL L H L X BA, CA, A8 READ/WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A8 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP(Idle after tRP) L H H H X NOP NOP(Idle after tRP) L H H L X TERM NOP L H L X BA, CA, A8 READ/WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A8 PRE/PREA NOP*4(Idle after tRP) L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP(ROW Active after tRCD) L H H H X NOP NOP(ROW Active after tRCD) L H H L X TERM NOP L H L X BA, CA, A8 READ/WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A8 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP L H H H X NOP NOP L H H L X TERM NOP L H L H BA, CA, A8 READ ILLEGAL*2 L H L L BA, CA, A8 WRITE/WRITEA New Write, Determine AP. L L H H BA, RA ACT ILLEGAL*2 L L L H BA, A8 PRE/PREA ILLEGAL*2 L L L L X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP(Idle after tRP) L H H H X NOP NOP(Idle after tRP) L H H L X TERM NOP L H L X BA, CA, A8 READ/WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A8 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ABBREVIATIONS : H=High Level, L=Low Level, V=Valid, X=Don't care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state, May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Same bank's previous Auto precharge will not be performed. But if Bank is different, previous Auto precharge will be performed. ILLEGAL = Device operation and/or data-integrity are not guaranteed. REV 1.1 Oct 05, 2005 29 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM FUNCTION TRUTH TABLE for CKE Current State SELFREFRESHING Both Bank Precharge POWER DOWN ALL BANKS IDLE Any State other than listed above CKE n-1 CKE n /CS /RAS /CAS /WE Add H X X X X X X INVALID L H H X X X X Exit Self-Refresh*1 L H L H H H X Exit Self-Refresh*1 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Self-Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down*2 L H L H H H X Exit Power Down*2 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Power Down) H H X X X X X Refer to Function True Table H L H X X X X Enter Power Down*3 H L L H H H X Enter Power Down*3 H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H H RA Row(& Bank) Active H L L L L H X Enter Self-Refresh *3 H L L L L L OP Code Mode Register Access L X X X X X X Refer to Current State=Power Down H H X X X X X Refer to Function True Table H L X X X X X Begin Clock Suspend next cycle *4 L H X X X X X Exit Clock Suspend next cycle *4 L L X X X X X Maintain Clock Suspend Action ABBREVIATIONS : H=High Level, L=Low Level, V=Valid, X=Don't care Note : 1. After CKE's low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE's low to high transition to issue a new command. 2. CKE low to high transition is asynchronous as if restarts internal clock. A minimum setup time "tIS + one clock" must be satisfied before any command other than exit. 3. Power-down and self-refresh can be entered only from the all banks idle state. 4. Must be a legal command. REV 1.1 Oct 05, 2005 30 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Timing Basic Timing (Setup, Hold and Access Time @BL=2, CL=3) /CK CK CKE /CS /RAS /CAS Ca 0 BA[1:0] BAa A8/AP ADDR READA (A0~A7,A9~A11) /WE DQS DQ DM COMMAND 1 2 tRPRE tDQSQ 3 Qa0 tCH 4 High tCK tCL tIH tIS 5 BAc 6 Cc BAb Cb tDS tDH tDS tDH Db1 7 Dc0 tDQSS tDQSL tWPREH tDQSH tWPRES Db0 WRITEC 8 Hi-Z tWPST Hi-Z Dc1 Oct 05, 2005 tRPST Qa1 WRITEB REV 1.1 31 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Multi Bank Interleaving READ (@BL=4, CL=3) /CK CK CKE /CS 0 BAb /RAS BAa /CAS BA[1:0] Rb 1 tRRD Ra Ra A8/AP ADDR ACTIVEA (A0~A7,A9~A11) /WE DQS DQ DM COMMAND 2 Rb ACTIVEB 3 4 High 5 BAa Ca READA 6 7 BAb Cb READB 8 Qa0 Qa1 9 Qa2 Qa3 10 Qb0 REV 1.1 Oct 05, 2005 32 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Multi Bank Interleaving WRITE (@BL=4, CL=3) /CK CK CKE /CS /RAS 0 BAa /CAS BA[1:0] Ra Ra A8/AP ADDR ACTIVEA (A0~A7,A9~A11) /WE DQS DQ DM COMMAND 1 tRCDW 2 BAa Ca WRITEA tDQSSmin 3 BAb Rb Rb Da0 ACTIVEB Da1 4 HIGH tRCDW Da2 Da3 5 BAb Cb WRITEB 6 Db0 Db1 7 Db2 Db3 8 REV 1.1 Oct 05, 2005 33 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Auto Precharge after READ Burst (@BL=8 ) *1 /CK CK CKE /CS /RAS /CAS BA[1:0] A8/AP ADDR (A0~A7,A9~A11) /WE DQS(CL=3) DQ(CL=3) DM 0 BAa Ca COMMAND READA 1 2 tRAS(min) 3 Qa0 4 High Qa1 The row active command of the precharged bank can be issued after tRP from this point. Qa2 Qa3 5 tRP Qa5 6 Qa6 Qa7 Auto precharge start *1 Qa4 7 8 BAa Ra Ra ACTIVEA (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. Oct 05, 2005 34 REV 1.1 NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Auto Precharge after WRITE Burst (@BL=4) *1 /CK CK CKE /CS /RAS /CAS BA[1:0] A8/AP ADDR (A0~A7,A9~A11) /WE DQS DQ DM COMMAND 0 BAa BAa 1 Da0 tWPREH tWPRES WRITEA Da1 2 Da2 Da3 3 4 High tWR The row active command of the precharged bank can be issued after tRP from this point. 5 tRP 6 Auto precharge start *1 7 8 BAa Ra Ra ACTIVEA (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. Oct 05, 2005 35 REV 1.1 NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Normal WRITE Burst (@BL=4) /CK CK CKE /CS /RAS /CAS BA[1:0] A8/AP ADDR (A0~A7,A9~A11) /WE DQS DQ DM COMMAND 0 2 Da0 tWPREH tWPRES 1 BAa Ca WRITEA Da1 3 Da2 Da3 4 High 5 tWR 6 BAa PRECHARGE 7 8 REV 1.1 Oct 05, 2005 36 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Write Interrupted by Precharge & DM (@BL=8) /CK CK CKE /CS /RAS /CAS BA[1:0] A8/AP ADDR (A0~A7,A9~A11) /WE DQS DQ DM COMMAND 0 BAa Ca WRITEA tWPREH tWPRES 1 Da0 Da1 2 Da2 Da3 3 Da4 tWR Da5 4 High BAa Da6 PRECHARGE Da7 BAb 5 BAc 6 Cb WRITEB tCCD Cc Db0 WRITEC Db1 7 Dc0 Dc1 8 Dc2 Dc3 REV 1.1 Oct 05, 2005 37 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Read Interrupted by Precharge (@BL=8) /CK CK CKE /CS /RAS /CAS BA[1:0] A8/AP ADDR (A0~A7,A9~A11) /WE DQS(CL=3) DQ(CL=3) DM COMMAND 0 1 BAa Ca READA 2 3 4 High BAa Qa0 PRE CHARGE Qa1 5 Qa2 Qa3 6 Qa4 Qa5 7 8 REV 1.1 Oct 05, 2005 38 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Read Interrupted by Burst stop & Write (@BL=8, CL=3) /CK CK CKE /CS /RAS /CAS BA[1:0] A8/AP ADDR (A0~A7,A9~A11) /WE DQS DQ DM 0 BAa Ca COMMAND READA 1 Burst Stop 2 3 Qa0 4 High Qa1 5 BAb Cb WRITEB 6 Db0 Db1 7 Db2 Db3 8 Db4 Qa5 REV 1.1 Oct 05, 2005 39 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Read Interrupted by Read (@BL=8, CL=3) /CK CK CKE /CS /RAS /CAS BA[1:0] A8/AP ADDR (A0~A7,A9~A11) /WE DQS DQ DM COMMAND 0 BAa Ca READA tCCD 1 BAb Cb READB 2 3 Qa0 4 High Qa1 Qb0 Qb1 5 Qb2 Qb3 6 Qb4 Qb5 7 Qb6 Qb7 8 REV 1.1 Oct 05, 2005 40 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM DM Function (@BL=8) only for write /CK CK CKE /CS /RAS /CAS BA[1:0] A8/AP ADDR (A0~A7,A9~A11) /WE DQS DQ DM COMMAND 0 2 Da0 tWPREH tWPRES 1 BAa Ca WRITEA Da1 tDS tDH 3 Da2 Da3 4 High Da4 Da5 tDS 5 Da6 Da7 tDH 6 7 8 REV 1.1 Oct 05, 2005 41 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Power up Sequence & Auto Refresh ( CBR ) /CK CK CKE /CS /RAS /CAS BA[1:0] BA[1:0] A8/AP ADDR 0 High High - Z High - Z (A0~A7,A9~A11) /WE DQS DQ DM Inputs must be stable for 200us 1 Precharge Command All Bank tRP 2 EMRS Command tMRD 3 MRS DLL Reset Command tMRD 4 High Precharge Command All Bank tRP 5 tRFC 6 2nd Auto Refresh Command tRFC 7 Mode Register Set Command Minimum of 2 Refresh Cycles are required 1st Auto Refresh Command tMRD 8 Any Command (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. Oct 05, 2005 42 REV 1.1 NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Mode Register Set /CK CK CKE /CS /RAS /CAS BA[1:0] A8/AP ADDR 0 High - Z High - Z High (A0~A7,A9~A11) /WE DQS DQ DM 1 Precharge All Bank Command 2 tRP 3 4 High Mode Register Set Command 5 tMRD 6 Any Command 7 8 REV 1.1 Oct 05, 2005 43 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM IBIS : I/V CHARACTERISTICS FOR INPUT AND OUTPUT BUFFERS Weak Output Driver Characteristics. 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below figure. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of below figure 80.0 Maximum 70.0 60.0 Typical High 50.0 Iout(mA) 40.0 Typical Low Minimum 30.0 20.0 10.0 0.0 0.1 0.6 1.1 1.6 2.1 Vout(V) 3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below figure. 4. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of below figure 0.0 -10.0 -20.0 Minimum Typical Low -30.0 Iout(mA) -40.0 -50.0 -60.0 -70.0 -80.0 Typical High -90.0 -100.0 Maximum -110.0 0.1 0.6 1.1 1.6 2.1 Vout(V) 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The full variation in the ratio of the nominal pullup to pulldown current should be unity 0%, for device drain to source voltages from 0 to VDDQ/2 REV 1.1 Oct 05, 2005 44 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Pulldown Current(mA) Voltage (V) Pullup Current(mA) Maximum Ty pical Low Ty pical High Minimum Maximum 2.5 4.8 -3.3 -4.1 -2.5 -4.9 5.0 9.4 -6.6 -7.8 -5.0 -9.7 Ty pical Low Ty pical High Minimum 0.1 3.3 3.7 0.2 6.6 7.3 0.3 9.8 10.9 7.4 14.0 -9.8 -11.4 -7.4 -14.5 0.4 13.0 14.4 10.0 18.3 -12.9 -14.9 -10.0 -19.2 0.5 16.1 17.8 12.4 22.6 -16.1 -18.4 -12.4 -23.9 0.6 18.7 21.1 14.9 26.7 -18.5 -21.9 -14.9 -28.4 0.7 21.3 23.9 17.4 30.7 -20.5 -25.3 -17.4 -32.9 0.8 23.6 26.9 19.9 34.1 -22.2 -28.7 -19.5 -37.3 0.9 25.6 29.8 21.4 37.7 -23.6 -32.1 -20.6 -41.7 1.0 27.7 32.6 23.0 41.2 -24.8 -35.4 -20.9 -46.0 1.1 29.2 35.2 24.2 44.5 -25.8 -38.6 -21.1 -50.7 1.2 30.3 37.7 25.0 47.7 -26.6 -41.9 -21.2 -54.3 1.3 31.3 40.1 25.4 50.7 -27.0 -45.2 -21.3 -58.4 1.4 32.0 42.4 25.6 53.5 -27.2 -48.4 -21.4 -62.4 1.5 32.5 44.4 25.8 56.0 -27.4 -51.6 -21.5 -66.4 1.6 32.7 46.4 25.9 58.6 -27.5 -54.7 -21.6 -70.4 1.7 32.9 48.1 26.2 60.6 -27.6 -57.8 -21.7 -73.8 1.8 33.2 49.8 26.4 62.6 -27.7 -60.7 -21.8 -77.8 1.9 33.5 51.5 26.5 64.6 -27.8 -64.1 -21.8 -81.3 2.0 33.8 52.5 26.7 66.6 -27.9 -67.0 -21.9 -84.7 2.1 33.9 53.5 26.8 68.3 -28.0 -69.8 -21.9 -88.1 2.2 34.2 54.5 26.9 69.9 -28.1 -72.7 -22.0 -91.6 2.3 34.5 55.0 27.0 71.5 -28.2 -75.6 -22.0 -95.0 2.4 34.6 55.5 27.0 72.9 -28.2 -78.4 -22.1 -97.0 2.5 34.9 56.0 27.1 74.1 -28.3 -81.3 -22.2 -101.3 Temperature (Ambient) Typical 25 C Minimum 70C Maximum 0C VDD/VDDQ Typical Minimum Maximum 2.50V / 2.50V 2.375V / 2.375V 2.625V / 2.625V The above characteristics are specified under best, worst and normal process variation/conditions REV 1.1 Oct 05, 2005 45 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM Impedance Match Output Driver Characteristics. IN JEDEC REV 1.1 Oct 05, 2005 46 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5DS4M32EG 4Mx32 Double Data Rate SDRAM PACKAGE DIMENSIONS (144-Balls FBGA with Pb Free) A1 INDEX MARK 12.0 12.0 <Top View> 0.80x11=8.8 0.10 MAX 0.80 0.80 A B C E F G 0.40 H J 0.80x11=8.8 D 0.45 0.05 K L M 12 11 10 9 8 7 6 5 4 3 2 1 0.35 0.05 0.40 1.40 Max REV 1.1 Oct 05, 2005 < Bottom View > 47 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.