REV 1.3.3 2/10/04
Characteristics subject to change without notice.
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X9251
Quad Digitally-Controlled (XDCP
TM
) Potentiometer
FEATURES
• Four potentiometers in one package
• 256 resistor taps–0.4% resolution
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance: 100
Ω
typical @ V
CC
= 5V
•4 Non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper positions
• Standby current < 5µA max
•V
CC
: 2.7V to 5.5V Operation
• 50K
Ω
, 100K
Ω
versions of total resistance
• 100 yr. data retention
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per
register
•24-lead SOIC, 24-lead TSSOP, 24-lead CSP
(Chip Scale Package)
•Low power CMOS
DESCRIPTION
The X9251 integrates four digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are imple-
mented with a combination of resistor elements and
CMOS switches. The position of the wipers are
controlled by the user through the SPI bus interface.
Each potentiometer has associated with it a volatile
Wiper Counter Register (WCR) and four non-volatile
Data Registers that can be directly written to and read
by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls
the content of the default Data Registers of each DCP
(DR00, DR10, DR20, and DR30) to the corresponding
WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
Single Supply / Low Power / 256-tap / SPI bus
A
PPLICATION
N
OTES
AND
D
EVELOPMENT
S
YSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
FUNCTIONAL DIAGRAM
POWER UP,
INTERFACE
CONTROL
AND
VCC
VSS
SPI
RH0
RL0
DCP0
RW0
A1
SO
SI
CS
HOLD
SCK
WP
WCR0
DR00
DR01
DR02
DR03
RH1
RL1
DCP1
RW1
WCR1
DR10
DR11
DR12
DR13
RH2
RL2
DCP2
RW2
WCR2
DR20
DR21
DR22
DR23
RH3
RL3
DCP3
RW3
WCR3
DR30
DR31
DR32
DR33
A0
Interface
STATUS
X9251
Characteristics subject to change without notice.
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ORDERING INFO
Ordering
Number
Potentiomenter
Organization Package
Operating
Temperature
Range
V
CC
Limits
X9251US24 50k
Ω
24-lead SOIC 0°C to 70°C 5V±10%
X9251US24-2.7 50k
Ω
24-lead SOIC 0°C to 70°C 2.7 to 5.5V
X9251US24I 50k
Ω
24-lead SOIC -40°C to +85°C 5V±10%
X9251US24I-2.7 50k
Ω
24-lead SOIC -40°C to +85°C 2.7 to 5.5V
X9251UV24 50k
Ω
24-lead TSSOP 0°C to 70°C 5V±10%
X9251UV24-2.7 50k
Ω
24-lead TSSOP 0°C to 70°C 2.7 to 5.5V
X9251UV24I 50k
Ω
24-lead TSSOP -40°C to +85°C 5V±10%
X9251UV24I-2.7 50k
Ω
24-lead TSSOP -40°C to +85°C 2.7 to 5.5V
X9251UB24 50k
Ω
24-lead CSP 0°C to 70°C 5V±10%
X9251UB24-2.7 50k
Ω
24-lead CSP 0°C to 70°C 2.7 to 5.5V
X9251UB24I 50k
Ω
24-lead CSP -40°C to +85°C 5V±10%
X9251UB24I-2.7 50k
Ω
24-lead CSP -40°C to +85°C 2.7 to 5.5V
X9251TS24 100k
Ω
24-lead SOIC 0°C to 70°C 5V±10%
X9251TS24-2.7 100k
Ω
24-lead SOIC 0°C to 70°C 2.7 to 5.5V
X9251TS24I 100k
Ω
24-lead SOIC -40°C to +85°C 5V±10%
X9251TS24I-2.7 100k
Ω
24-lead SOIC -40°C to +85°C 2.7 to 5.5V
X9251TV24 100k
Ω
24-lead TSSOP 0°C to 70°C 5V±10%
X9251TV24-2.7 100k
Ω
24-lead TSSOP 0°C to 70°C 2.7 to 5.5V
X9251TV24I 100k
Ω
24-lead TSSOP -40°C to +85°C 5V±10%
X9251TV24I-2.7 100k
Ω
24-lead TSSOP -40°C to +85°C 2.7 to 5.5V
X9251TB24 100k
Ω
24-lead CSP 0°C to 70°C 5V±10%
X9251TB24-2.7 100k
Ω
24-lead CSP 0°C to 70°C 2.7 to 5.5V
X9251TB24I 100k
Ω
24-lead CSP -40°C to +85°C 5V±10%
X9251TB24I-2.7 100k
Ω
24-lead CSP -40°C to +85°C 2.7 to 5.5V
X9251
Characteristics subject to change without notice.
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CIRCUIT LEVEL APPLICATIONS
•Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
•Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
•Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
•Vary the frequency and duty cycle of timer ICs
•Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
•Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
•Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
•Trim offset and gain errors in artificial intelligent
systems
X9251
Characteristics subject to change without notice.
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PIN CONFIGURATION
PIN ASSIGNMENTS
Note 1:
A0–A1 device address pins must be tied to a logic level.
Pin
(SOIC)
Pin
(CSP) Symbol Function
1E2SOSerial Data Output for SPI bus
2F2A0Device Address for SPI bus. (See Note 1)
3F1R
W3
Wiper Terminal of DCP3
4D2R
H3
High Terminal of DCP3
5E1R
L3
Low Terminal of DCP3
7C1V
CC
System Supply Voltage
8B1R
L0
Low Terminal of DCP0
9C2R
H0
High Terminal of DCP0
10 A1 R
W0
Wiper Terminal of DCP0
11 A2 CS SPI bus. Chip Select active low input
12 B2 WP Hardware Write Protect – active low
13 B3 SI Serial Data Input for SPI bus
14 A3 A1 Device Address for SPI bus. (See Note 1)
15 A4 R
L1
Low Terminal of DCP1
16 C3 R
H1
High Terminal of DCP1
17 B4 R
W1
Wiper Terminal of DCP1
18 C4 V
SS
System Ground
20 E4 R
W2
Wiper Terminal of DCP2
21 D3 R
H2
High Terminal of DCP2
22 F4 R
L2
Low Terminal of DCP2
23 F3 SCK Serial Clock for SPI bus
24 E3 HOLD Device select. Pauses the SPI serial bus.
6, 19 D1, D4 NC No Connect
2 3 4
A
B
C
D
E
F
Top View–Bumps Down
RW0
RL0
NC
A0
HOLD
RL1
VCC
RL3
RW3
SO
SI RW1
SCK RL2
WP
NC
RH0 RH1
RH3
VSS
RW2
CS A1
1
CSP
RH2
SO
A0
RW3
NC
VCC
RL0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
RL2
RH2
RW2
NC
VSS
RW1
RH1
RL1
SOIC/TSSOP
X9251
RH3
14
13
11
12
RL3
RH0
RW0
CS A1
SI
WP
X9251
Characteristics subject to change without notice.
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PIN DESCRIPTIONS
Bus Interface Pins
S
ERIAL
O
UTPUT
(SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
S
ERIAL
I
NPUT
(SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the device
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9251.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
DEVICE ADDRESS (A1–A0)
The address inputs are used to set the two least
significant bits of the slave address. A match in the
slave address serial data stream must be made with
the address input in order to initiate communication
with the X9251. Device pins A1-A0 must be tie to a
logic level which specify the internal address of the
device, see Figures 2, 3, 4, 5 and 6.
CHIP SELECT (CS)
When CS is HIGH, the X9251 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device is in the standby
state. CS LOW enables the X9251, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer. Since
there are 4 potentiometers, there are 4 sets of RH and
RL such that RH0 and RL0 are the terminals of DCP0
and so on.
RW
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 4 sets of RW such that RW0
is the terminals of DCP0 and so on.
Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin
is the system ground.
Other Pins
NO CONNECT
No connect pins should be left floating. This pins are
used for Xicor manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents non-volatile writes to
the Data Registers.
X9251
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PRINCIPLES OF OPERATION
The X9251 is an integrated circuit incorporating four
DCPs and their associated registers and counters, and
a serial interface providing direct communication
between a host and the potentiometers.
DCP Description
Each DCP is implemented with a combination of
resistor elements and CMOS switches. The physical
ends of each DCP are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL pins). The
RW pin is an intermediate node, equivalent to the
wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH,
VL, VW. The VCC ramp rate specification is always in
effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
8 8
COUNTER
IF WCR = 00[H] then RW is closet to RL
IF WCR = FF[H] then RW is closet to RH
WIPER
(WCR#)
#: 0, 1, 2, or 3
One of Four Potentiometers
DR#2
DR#1
DR#3
- - -
DECODE
DCP
CORE RW
RH
RL
X9251
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Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one
for each potentiometer. The Wiper Counter Register
can be envisioned as a 8-bit parallel and serial load
counter with its outputs decoded to select one of 256
wiper positions along its resistor array. The contents of
the WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step
at a time by the Increment/Decrement instruction (see
Instruction section for more details). Finally, it is loaded
with the contents of its Data Register zero (DR#0)
upon power-up. (See Figure 1.)
The wiper counter register is a volatile register; that is,
its contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the
value in DR#0 upon power-up, this may be different
from the value present at power-down. Power-up
guidelines are recommended to ensure proper
loadings of the DR#0 value into the WCR#.
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a non-volatile operation and takes a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
WIP: Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress.
Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile).
Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Non-volatile).
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
(MSB) (LSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(MSB) (LSB)
X9251
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SERIAL INTERFACE
The X9251 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in, on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
IDENTIFICATION BYTE
The first byte sent to the X9251 from the host, following
a CS going HIGH to LOW, is called the Identification
Byte. The most significant four bits of the Identification
Byte are a Device Type Identifier, ID[3:0]. For the
X9251, this is fixed as 0101 (refer to Table 3).
The least significant four bits of the Identification Byte
are the Slave Address bits, AD[3:0]. For the X9251, A3
is 0, A2 is 0, A1 is the logic value at the input pin A1,
and A0 is the logic value at the input pin A0. Only the
device which Slave Address matches the incoming
bits sent by the master executes the instruction. The
A1 and A0 inputs can be actively driven by CMOS
input signals or tied to VCC or VSS.
INSTRUCTION BYTE
The next byte sent to the X9251 contains the
instruction and register pointer information. The four
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least two significant bits point to one of four Wiper
Counter Registers or DCPs.The format is shown below
in Table 4.
Table 3. Identification Byte Format
Table 4. Instruction Byte Format
Data Register Selection
#: 0, 1, 2, or 3
Register RB RA
DR#0 0 0
DR#1 0 1
DR#2 1 0
DR#3 1 1
ID3 ID2 ID1 ID0 A3 A2 A1 A0
010100Pin A1
Logic Value
Pin A0
Logic Value
(MSB) (LSB)
Device Type
Identifier Slave Address
I3 I2 I1 I0 RB RA P1 P0
(MSB) (LSB)
Instruction Register DCP Selection
Opcode Selection (WCR Selection)
X9251
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Table 5. Instruction Set
Note: 1/0 = data is one or zero
Instruction
Instruction Set
OperationI3 I2 I1 I0 RB RA P1 P0
Read Wiper Counter
Register
10010 01/0 1/0 Read the contents of the Wiper Counter
Register pointed to by P1-P0
Write Wiper Counter
Register
10100 01/0 1/0 Write new value to the Wiper Counter
Register pointed to by P1-P0
Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register
pointed to by P1-P0 and RB-RA
Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register
pointed to by P1-P0 and RB-RA
XFR Data Register to
Wiper Counter Register
11011/0 1/0 1/0 1/0 Transfer the contents of the Data Register
pointed to by P1-P0 and RB-RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register
11101/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter
Register pointed to by P1-P0 to the Data
Register pointed to by RB-RA
Global XFR Data Registers
to Wiper Counter Registers
00011/0 1/0 0 0 Transfer the contents of the Data Registers
pointed to by RB-RA of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
10001/0 1/0 0 0 Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB-RA of all four pots
Increment/Decrement
Wiper Counter Register
00100 01/0 1/0 Enable Increment/decrement of the Control
Latch pointed to by P1-P0
X9251
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Instructions
Four of the nine instructions are three bytes in length.
These instructions are:
–Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
–Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
–Read Data Register – read the contents of the
selected Data Register,
–Write Data Register – write a new value to the
selected Data Register,
–Read Status – this command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action is delayed by tWRL. A transfer from
the WCR (current wiper position), to a Data Register is
a write to non-volatile memory and takes a minimum of
tWR to complete. The transfer can occur between one
of the four potentiometer’s WCR, and one of its
associated registers, DRs; or it may occur globally,
where the transfer occurs between all potentiometers
and one associated register. The Read Status Register
instruction is the only unique format (see Figure 5).
Four instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9251; either between the host and one
of the data registers or directly between the host and
the Wiper Counter Register. These instructions are:
–XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
–XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
–Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified
Data Registers to the associated Wiper Counter
Registers.
–Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (see
Figures 6 and 7). The Increment/Decrement command
is different from the other commands. Once the
command is issued and the X9251 has responded with
an Acknowledge, the master can clock the selected
wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each
SCK clock pulse (tHIGH) while SI is HIGH, the selected
wiper moves one wiper position towards the RH
terminal. Similarly, for each SCK clock pulse while SI is
LOW, the selected wiper moves one wiper position
towards the RL terminal. A detailed illustration of the
sequence and timing for this operation are shown. See
Instruction format for more details.
X9251
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Figure 2. Two-Byte Instruction Sequence
Figure 3. Three-Byte Instruction Sequence SPI Interface; Write Case
Figure 4. Three-Byte Instruction Sequence SPI Interface, Read Case
ID3 ID2 ID1 ID0 0 A1 A0 I3 I2 I1 RB RA P0
SCK
SI
CS
0101
Device ID Internal Instruction
Opcode
Address
Register
0
I0 P1
Address DCP/WCR
Address
0
0
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCK
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address
Register
Address
DCP/WCR
Address
00
P1
Data for WCR[7:0] or DR[7:0]
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCK
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address
Register
Address
DCP/WCR
Address
00
P1
WCR[7:0]
S0
XXXXX
XXX
Don’t Care
or
Data Register Bit [7:0]
X9251
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Figure 5. Three-Byte Instruction Sequence (Read Status Register)
Figure 6. Increment/Decrement Instruction Sequence
Figure 7. Increment/Decrement Timing Spec
WIP
Status
Bit
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCK
SI
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address
Register
Address
Pot/WCR
Address
00
P1
00000
00
1011
0101
A1 A0 I3I2 I1 I0 RB RA P0
SCK
SI
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address
Register
Address
Pot/WCR
Address
00
P1
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
SCK
SI
R
W
INC/DEC CMD ISSUED
tWRID
VOLTAGE OUT
X9251
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INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Wiper Position
(Sent by X9251 on SO) CS
Rising
Edge
010100A1A010010000
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by Host on SI) CS
Rising
Edge
010100A1A010100000
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by X9271 on SO) CS
Rising
Edge
010100A1A01011RBRAP1 P0 D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by Host on SI) CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01100RBRAP1 P0 D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses CS
Rising
Edge
010100A1 A0 0001RBRA00
X9251
Characteristics subject to change without notice. 14 of 25
REV 1.3.3 2/10/04 www.xicor.com
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Increment/Decrement Wiper Counter Register (WCR)
Read Status Register (SR)
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01000RBRA00
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01110RBRA0 0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses CS
Rising
Edge
010100A1A01101RBRA0 0
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Increment/Decrement
(Sent by Master on SI) CS
Rising
Edge
010100A1A00010XX00I/DI/D. . . .I/DI/D
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by X9251 on SO) CS
Rising
Edge
010100A1A0010100010 000 0 00 WIP
X9251
Characteristics subject to change without notice. 15 of 25
REV 1.3.3 2/10/04 www.xicor.com
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on SCK, any address input, VCC
with respect to VSS..................................–1V to +7V
∆V = | (VH–VL) | ................................................... 5.5V
Lead temperature (soldering, 10 seconds).........300°C
IW (10 seconds) ................................................. ±6mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (RH – RL) / 255, single pot
(4) During power up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.
Symbol
Parameter Limits
Test ConditionsMin. Typ. Max. Units
RTOTAL End to End Resistance 100 kΩT version
RTOTAL End to End Resistance 50 kΩU version
End to End Resistance Tolerance ±20 %
Power Rating 50 mW 25°C, each pot
IW Wiper Current ±3 mA
RWWiper Resistance 300 ΩIW = @ VCC = 3V
150 ΩIW = @ VCC = 5V
VTERM Voltage on any RH or RL Pin VSS VCC VV
SS = 0V
Noise -120 dBV/ Hz Ref: 1V
Resolution 0.4 %
Absolute Linearity (1) -1 +1 MI(3) Rw(n)(actual) – Rw(n)(expected)(5)
Relative Linearity (2) -0.6 +0.6 MI(3) Rw(n + 1) – [Rw(n) + MI](5)
Temperature Coefficient of RTOTAL ±300 ppm/°C
Ratiometric Temp. Coefficient -20 +20 ppm/°C
CH/CL/CWPotentiometer Capacitances 10/10/25 pF See Macro model
V(VCC)
RTOTA
L
V(VCC)
RTOTA
L
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Device Supply Voltage (VCC)(4) Limits
X9251 5V ±10%
X9251-2.7 2.7V to 5.5V
X9251
Characteristics subject to change without notice. 16 of 25
REV 1.3.3 2/10/04 www.xicor.com
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
A.C. TEST CONDITIONS
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be
issued. These parameters are periodically sampled and not 100% tested.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
ICC1 VCC supply current
(active)
400 µAf
SCK = 2.5 MHz, SO = Open, VCC=6V
Other Inputs = VSS
ICC2 VCC supply current
(non-volatile write)
15mAf
SCK = 2.5MHz, SO = Open, VCC=6V
Other Inputs = VSS
ISB VCC current (standby) 3 µA SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V
ILI Input leakage current 10 µAV
IN = VSS to VCC
ILO Output leakage current 10 µAV
OUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 1 V
VIL Input LOW voltage –1 VCC x 0.3 V
VOL Output LOW voltage 0.4 V IOL = 3mA
VOH Output HIGH voltage VCC - 0.8 V IOH = -1mA, VCC ≥ +3V
VOH Output HIGH voltage VCC - 0.4 V IOH = -0.4mA, VCC ≤ +3V
Parameter Min. Units
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Symbol Test Max. Units Test Conditions
CIN/OUT(6) Input / Output capacitance (SI) 8pFVOUT = 0V
COUT(6) Output capacitance (SO) 8pFVOUT = 0V
CIN(6) Input capacitance (A0, A1, CS, WP, HOLD, and SCK) 6pFVIN = 0V
Symbol Parameter Min. Max. Units
tr VCC(6) VCC Power-up rate 0.2 50 V/ms
tPUR(7) Power-up to initiation of read operation 1 ms
tPUW(7) Power-up to initiation of write operation 50 ms
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
X9251
Characteristics subject to change without notice. 17 of 25
REV 1.3.3 2/10/04 www.xicor.com
EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
Symbol Parameter Min. Max. Units
fSCK SPI clock frequency 2 MHz
tCYC SPI clock cycle rime 500 ns
tWH SPI clock high rime 200 ns
tWL SPI clock low time 200 ns
tLEAD Lead time 250 ns
tLAG Lag time 250 ns
tSU SI, SCK, HOLD and CS input setup time 50 ns
tHSI, SCK, HOLD and CS input hold time 50 ns
tRI SI, SCK, HOLD and CS input rise time 2 µs
tFI SI, SCK, HOLD and CS input fall time 2 µs
tDIS SO output disable time 0 250 ns
tVSO output valid time 200 ns
tHO SO output hold time 0 ns
tRO SO output rise time 100 ns
tFO SO output fall time 100 ns
tHOLD HOLD time 400 ns
tHSU HOLD setup time 100 ns
tHH HOLD hold time 100 ns
tHZ HOLD low to output in high Z 100 ns
tLZ HOLD high to output in low Z 100 ns
TINoise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns
tCS CS deselect time 2 µs
tWPASU WP, A0 setup time 0 ns
tWPAH WP, A0 hold time 0 ns
RH
10pF
CLCL
RW
RTOTAL
CW
25pF
10pF
RL
SPICE Macromodel
VCC
2kΩ
10pF
SO pin
2kΩ
X9251
Characteristics subject to change without notice. 18 of 25
REV 1.3.3 2/10/04 www.xicor.com
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
.
Symbol Parameter Typ. Max. Units
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Units
tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X9251
Characteristics subject to change without notice. 19 of 25
REV 1.3.3 2/10/04 www.xicor.com
TIMING DIAGRAMS
Input Timing
Output Timing
Hold Timing
...
CS
SCK
SI
SO
MSB LSB
High Impedance
tLEAD
tH
tSU tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
...
CS
SCK
SO
SI ADDR
MSB LSB
tDIS
tHO
tV
...
...
CS
SCK
SO
SI
HOLD
tHSU tHH
tLZ
tHZ
tHOLD
tRO tFO
X9251
Characteristics subject to change without notice. 20 of 25
REV 1.3.3 2/10/04 www.xicor.com
XDCP Timing (for All Load Instructions)
Write Protect and Device Address Pins Timing
...
CS
SCK
SI MSB LSB
VWx
tWRL
...
SO High Impedance
CS
WP
A0
A1
tWPASU tWPAH
(Any Instruction)
X9251
Characteristics subject to change without notice. 21 of 25
REV 1.3.3 2/10/04 www.xicor.com
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider Tw o terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysterisis
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
100KΩ
10KΩ10KΩ
10KΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9251
Characteristics subject to change without notice. 22 of 25
REV 1.3.3 2/10/04 www.xicor.com
Application Circuits (continued)
Attenuator Filter
Inverting Amplifier Equivalent L-R Circuit
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2
GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
R2
R4R1 = R2 = R3 = R4 = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
VO
X9251
Characteristics subject to change without notice. 23 of 25
REV 1.3.3 2/10/04 www.xicor.com
PACKAGING INFORMATION
Symbol
Millimeters Inches
Min Nom. Max Min Nom. Max
Package Width A 2.755 2.785 2.815
Package Length B 4.507 4.537 4.567
Package Height C 0.644 0.677 0.710
Body Thickness D 0.444 0.457 0.470
Ball Height E 0.200 0.220 0.240
Ball Diameter F 0.300 0.320 0.340
Ball Pitch – Width J 0.5
Ball Pitch – Length K 0.5
Ball to Edge Spacing – Width L 0.618 0.643 0.668
Ball to Edge Spacing – Length M 1.056 1.081 1.106
Ball Matrix
4321
ARL1 A1 CS RW0
BRW1 SI WP RL0
CVSS RH1 RH0 VCC
DNC RH2 RH3 NC
ERW2 HOLD SO RL3
FRL2 SCK A0 RW3
9251TRR
YWW I
LOT #
f
k
m
lj
b
a
A4 A3 A2 A1
A4 A3 A2 A1
A4 A3 A2 A1
A4 A3 A2 A1
A4 A3 A2 A1
A4 A3 A2 A1
e
d
e
e
24-Bump Chip Scale Package (CSP B24)
Package Outline Drawing
Top View (Marking Side) Bottom View (Bumped Side) Side View
Side View
X9251
Characteristics subject to change without notice. 24 of 25
REV 1.3.3 2/10/04 www.xicor.com
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
24-Lead Plastic, TSSOP, Package Code V24
.169 (4.3)
.177 (4.5).252 (6.4) BSC
.026 (.65) BSC
.303 (7.70)
.311 (7.90)
.002 (.06)
.005 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
See Detail “A”
.031 (.80)
.041 (1.05)
.010 (.25)
.020 (.50)
.030 (.75)
Gage Plane
Seating Plane
Detail A (20X)
(4.16) (7.72)
(1.78)
(0.42)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
0°–8°
X9251
Characteristics subject to change without notice. 25 of 25
REV 1.3.3 2/10/04 www.xicor.com
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
©Xicor, Inc. 2004 Patents Pending
PACKAGING INFORMATION
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
0.014 (0.35)
0.020 (0.50)
Pin 1
Pin 1 Index
0.050 (1.27)
0.598 (15.20)
0.610 (15.49)
0.003 (0.10)
0.012 (0.30)
0.092 (2.35)
0.105 (2.65)
(4X) 7°
24-Lead Plastic, SOIC, Package Code S24
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.420"
0.050" Typical
0.050"
Typical
0.030" Typical
24 Places
FOOTPRINT
0.010 (0.25)
0.020 (0.50)
0.015 (0.40)
0.050 (1.27)
0.009 (0.22)
0.013 (0.33)
0° – 8°
X 45°
