APPLICATION NOTES AND DEVELOPMENT SYSTEM A V A I L A B L E AN99 * AN115 * AN124 *AN133 * AN134 * AN135 Single Supply / Low Power / 256-tap / SPI bus X9251 Quad Digitally-Controlled (XDCPTM) Potentiometer FEATURES DESCRIPTION * Four potentiometers in one package * 256 resistor taps-0.4% resolution * SPI Serial Interface for write, read, and transfer operations of the potentiometer * Wiper resistance: 100 typical @ VCC = 5V * 4 Non-volatile data registers for each potentiometer * Non-volatile storage of multiple wiper positions * Standby current < 5A max * VCC: 2.7V to 5.5V Operation * 50K, 100K versions of total resistance * 100 yr. data retention * Single supply version of X9250 * Endurance: 100,000 data changes per bit per register * 24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip Scale Package) * Low power CMOS The X9251 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM HOLD A1 SPI Interface A0 SO RH1 RH0 VCC WCR0 DR00 DR01 DR02 DR03 POWER UP, INTERFACE CONTROL AND STATUS DCP0 WCR1 DR10 DR11 DR12 DR13 DCP1 RH3 RH2 WCR2 DR20 DR21 DR22 DR23 DCP2 WCR3 DR30 DR31 DR32 DR33 DCP3 SI SCK CS VSS REV 1.3.3 2/10/04 WP RW0 RL0 www.xicor.com RW1 RL1 RW2 RL2 RW3 RL3 Characteristics subject to change without notice. 1 of 25 X9251 ORDERING INFO Package Operating Temperature Range VCC Limits 50k 24-lead SOIC 0C to 70C 5V10% 50k 24-lead SOIC 0C to 70C 2.7 to 5.5V Ordering Number Potentiomenter Organization X9251US24 X9251US24-2.7 X9251US24I 50k 24-lead SOIC -40C to +85C 5V10% X9251US24I-2.7 50k 24-lead SOIC -40C to +85C 2.7 to 5.5V X9251UV24 50k 24-lead TSSOP 0C to 70C 5V10% X9251UV24-2.7 50k 24-lead TSSOP 0C to 70C 2.7 to 5.5V X9251UV24I 50k 24-lead TSSOP -40C to +85C 5V10% X9251UV24I-2.7 50k 24-lead TSSOP -40C to +85C 2.7 to 5.5V X9251UB24 50k 24-lead CSP 0C to 70C 5V10% X9251UB24-2.7 50k 24-lead CSP 0C to 70C 2.7 to 5.5V X9251UB24I 50k 24-lead CSP -40C to +85C 5V10% X9251UB24I-2.7 50k 24-lead CSP -40C to +85C 2.7 to 5.5V X9251TS24 100k 24-lead SOIC 0C to 70C 5V10% X9251TS24-2.7 100k 24-lead SOIC 0C to 70C 2.7 to 5.5V X9251TS24I 100k 24-lead SOIC -40C to +85C 5V10% X9251TS24I-2.7 100k 24-lead SOIC -40C to +85C 2.7 to 5.5V X9251TV24 100k 24-lead TSSOP 0C to 70C 5V10% X9251TV24-2.7 100k 24-lead TSSOP 0C to 70C 2.7 to 5.5V X9251TV24I 100k 24-lead TSSOP -40C to +85C 5V10% X9251TV24I-2.7 100k 24-lead TSSOP -40C to +85C 2.7 to 5.5V X9251TB24 100k 24-lead CSP 0C to 70C 5V10% X9251TB24-2.7 100k 24-lead CSP 0C to 70C 2.7 to 5.5V X9251TB24I 100k 24-lead CSP -40C to +85C 5V10% X9251TB24I-2.7 100k 24-lead CSP -40C to +85C 2.7 to 5.5V REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 2 of 25 X9251 CIRCUIT LEVEL APPLICATIONS SYSTEM LEVEL APPLICATIONS * Vary the gain of a voltage amplifier * Adjust the contrast in LCD displays * Provide programmable dc reference voltages for comparators and detectors * Control the power level of LED transmitters in communication systems * Control the volume in audio circuits * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Trim out the offset voltage error in a voltage amplifier circuit * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits * Vary the frequency and duty cycle of timer ICs * Vary the dc biasing of a pin diode attenuator in RF circuits * Control the gain in audio and home entertainment systems * Provide the variable DC bias for tuners in RF wireless systems * Set the operating points in temperature control systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems * Provide a control variable (I, V, or R) in feedback circuits REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 3 of 25 X9251 PIN CONFIGURATION CSP SOIC/TSSOP SO 1 24 HOLD A0 RW3 2 23 SCK 3 22 RL2 RH3 4 21 RH2 RL3 5 20 RW2 NC 6 VCC X9251 7 19 NC 18 VSS RL0 8 17 RW1 RH0 9 16 RH1 RW0 10 15 RL1 CS 11 14 A1 WP 12 13 A B 1 2 3 4 RW0 CS A1 RL1 RL0 WP SI RW1 VCC RH0 RH1 VSS NC RH3 RH2 NC RL3 SO HOLD RW2 RW3 A0 SCK RL2 C D E F SI Top View-Bumps Down PIN ASSIGNMENTS Pin (SOIC) Pin (CSP) Symbol 1 E2 SO Serial Data Output for SPI bus 2 F2 A0 Device Address for SPI bus. (See Note 1) 3 F1 RW3 Wiper Terminal of DCP3 4 D2 RH3 High Terminal of DCP3 Function 5 E1 RL3 Low Terminal of DCP3 7 C1 VCC System Supply Voltage 8 B1 RL0 Low Terminal of DCP0 9 C2 RH0 High Terminal of DCP0 10 A1 RW0 Wiper Terminal of DCP0 11 A2 CS SPI bus. Chip Select active low input 12 B2 WP Hardware Write Protect - active low 13 B3 SI Serial Data Input for SPI bus 14 A3 A1 Device Address for SPI bus. (See Note 1) 15 A4 RL1 Low Terminal of DCP1 16 C3 RH1 High Terminal of DCP1 17 B4 RW1 Wiper Terminal of DCP1 18 C4 VSS System Ground 20 E4 RW2 Wiper Terminal of DCP2 21 D3 RH2 High Terminal of DCP2 22 F4 RL2 Low Terminal of DCP2 23 F3 SCK Serial Clock for SPI bus 24 E3 HOLD 6, 19 D1, D4 NC Device select. Pauses the SPI serial bus. No Connect Note 1: A0-A1 device address pins must be tied to a logic level. REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 4 of 25 X9251 PIN DESCRIPTIONS Potentiometer Pins Bus Interface Pins RH, RL SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RH and RL such that RH0 and RL0 are the terminals of DCP0 and so on. SERIAL INPUT (SI) RW SI is the serial data input pin. All opcodes, byte addresses and data to be written to the device registers are input on this pin. Data is latched by the rising edge of the serial clock. The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RW such that RW0 is the terminals of DCP0 and so on. SERIAL CLOCK (SCK) Supply Pins The SCK input is used to clock data into and out of the X9251. SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) HOLD (HOLD) The VCC pin is the system supply voltage. The VSS pin is the system ground. SERIAL OUTPUT (SO) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A1-A0) Other Pins NO CONNECT No connect pins should be left floating. This pins are used for Xicor manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents non-volatile writes to the Data Registers. The address inputs are used to set the two least significant bits of the slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9251. Device pins A1-A0 must be tie to a logic level which specify the internal address of the device, see Figures 2, 3, 4, 5 and 6. CHIP SELECT (CS) When CS is HIGH, the X9251 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device is in the standby state. CS LOW enables the X9251, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 5 of 25 X9251 PRINCIPLES OF OPERATION The X9251 is an integrated circuit incorporating four DCPs and their associated registers and counters, and a serial interface providing direct communication between a host and the potentiometers. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Counter Register (WCR). Power Up and Down Recommendations. There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC ramp rate specification is always in effect. Figure 1. Detailed Potentiometer Block Diagram One of Four Potentiometers RH #: 0, 1, 2, or 3 SERIAL BUS INPUT SERIAL DATA PATH FROM INTERFACE CIRCUITRY DR#1 DR#0 8 DR#2 IF WCR = 00[H] then RW is closet to RL IF WCR = FF[H] then RW is closet to RH 8 WIPER COUNTER REGISTER (WCR#) DR#3 COUNTER --DECODE DCP CORE RW INC/DEC LOGIC UP/DN MODIFIED SCK REV 1.3.3 2/10/04 PARALLEL BUS INPUT www.xicor.com UP/DN CLK RL Characteristics subject to change without notice. 6 of 25 X9251 Wiper Counter Register (WCR) The X9251 contains four Wiper Counter Registers, one for each potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (see Instruction section for more details). Finally, it is loaded with the contents of its Data Register zero (DR#0) upon power-up. (See Figure 1.) Data Registers (DR) Each of the four DCPs has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a non-volatile operation and takes a maximum of 10ms. The wiper counter register is a volatile register; that is, its contents are lost when the X9251 is powered-down. Although the register is automatically loaded with the value in DR#0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR#0 value into the WCR#. Status Register (SR) This 1-bit Status Register is used to store the system status. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bits [7:0] are used to store one of the 256 wiper positions or data (0~255). WIP: Write In Progress status bit, read only. - When WIP=1, indicates that high-voltage write cycle is in progress. - When WIP=0, indicates that no high-voltage write cycle is in progress. Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile). WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 (MSB) WCR0 (LSB) Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Non-volatile). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (MSB) REV 1.3.3 2/10/04 Bit 2 Bit 1 Bit 0 (LSB) www.xicor.com Characteristics subject to change without notice. 7 of 25 X9251 SERIAL INTERFACE The X9251 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in, on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. IDENTIFICATION BYTE The first byte sent to the X9251 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the Identification Byte are a Device Type Identifier, ID[3:0]. For the X9251, this is fixed as 0101 (refer to Table 3). The least significant four bits of the Identification Byte are the Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0, A1 is the logic value at the input pin A1, and A0 is the logic value at the input pin A0. Only the device which Slave Address matches the incoming bits sent by the master executes the instruction. The A1 and A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE The next byte sent to the X9251 contains the instruction and register pointer information. The four most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers of each associated XDCP. The least two significant bits point to one of four Wiper Counter Registers or DCPs.The format is shown below in Table 4. Table 3. Identification Byte Format Device Type Identifier Slave Address ID3 ID2 ID1 ID0 A3 A2 A1 A0 0 1 0 1 0 0 Pin A1 Logic Value Pin A0 Logic Value (MSB) (LSB) Table 4. Instruction Byte Format Register Selection Instruction Opcode I3 I2 I1 I0 RB (MSB) DCP Selection (WCR Selection) RA P1 P0 (LSB) Data Register Selection Register RB RA DR#0 0 0 DR#1 0 1 DR#2 1 0 DR#3 1 1 #: 0, 1, 2, or 3 REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 8 of 25 X9251 Table 5. Instruction Set Instruction I3 I2 Instruction Set I1 I0 RB RA P1 P0 Operation 1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register pointed to by P1-P0 Write new value to the Wiper Counter Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and RB-RA Write new value to the Data Register pointed to by P1-P0 and RB-RA Transfer the contents of the Data Register pointed to by P1-P0 and RB-RA to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P1-P0 to the Data Register pointed to by RB-RA Transfer the contents of the Data Registers pointed to by RB-RA of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB-RA of all four pots Enable Increment/decrement of the Control Latch pointed to by P1-P0 Read Wiper Counter Register Write Wiper Counter Register Read Data Register 1 0 1 0 0 0 1/0 1/0 1 0 1 1 1/0 1/0 1/0 1/0 Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 1/0 1/0 XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Global XFR Data Registers to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Global XFR Wiper Counter Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 1/0 1/0 Note: 1/0 = data is one or zero REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 9 of 25 X9251 Instructions Four of the nine instructions are three bytes in length. These instructions are: - Read Wiper Counter Register - read the current wiper position of the selected potentiometer, - Write Wiper Counter Register - change current wiper position of the selected potentiometer, - Read Data Register - read the contents of the selected Data Register, - Write Data Register - write a new value to the selected Data Register, - Read Status - this command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the three byte instructions is illustrated in Figure 3. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action is delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometer's WCR, and one of its associated registers, DRs; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (see Figure 5). Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9251; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: REV 1.3.3 2/10/04 - XFR Data Register to Wiper Counter Register - This transfers the contents of one specified Data Register to the associated Wiper Counter Register. - XFR Wiper Counter Register to Data Register - This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. - Global XFR Data Register to Wiper Counter Register - This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. - Global XFR Wiper Counter Register to Data Register - This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (see Figures 6 and 7). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9251 has responded with an Acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper moves one wiper position towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper moves one wiper position towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown. See Instruction format for more details. www.xicor.com Characteristics subject to change without notice. 10 of 25 X9251 Figure 2. Two-Byte Instruction Sequence CS SCK SI 1 0 0 ID3 ID2 ID1 ID0 0 0 0 1 0 A1 A0 Internal Address Device ID I3 I2 I1 RB RA P1 I0 Instruction Opcode P0 Register DCP/WCR Address Address Figure 3. Three-Byte Instruction Sequence SPI Interface; Write Case CS SCK SI 0 1 0 1 ID3 ID2 ID1 ID0 0 0 0 0 A1 A0 I3 I2 I0 Instruction Opcode Internal Address Device ID I1 RB RA P1 P0 D7 D6 D5 D4 D3 D2 D1 D0 Data for WCR[7:0] or DR[7:0] Register DCP/WCR Address Address Figure 4. Three-Byte Instruction Sequence SPI Interface, Read Case CS SCK SI 0 1 0 1 ID3 ID2 ID1 ID0 Device ID 0 0 0 0 X A1 A0 Internal Address I3 I2 I1 I0 Instruction Opcode RB RA P1 P0 X X X X X X X Don't Care Register DCP/WCR Address Address S0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register Bit [7:0] REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 11 of 25 X9251 Figure 5. Three-Byte Instruction Sequence (Read Status Register) CS SCK SI 0 1 0 1 ID3 ID2 ID1 ID0 0 0 0 0 1 A1 A0 I3 Internal Address Device ID 0 1 1 I1 I0 I2 Instruction Opcode 0 0 0 0 0 0 RB RA P1 P0 0 WIP Register Pot/WCR Address Address Status Bit Figure 6. Increment/Decrement Instruction Sequence CS SCK SI 0 1 0 1 ID3 ID2 ID1 ID0 Device ID 0 0 0 0 A1 A0 I2 Internal Address I3 I1 I0 Instruction Opcode RB RA P1 P0 Register Pot/WCR Address Address I N C 1 I N C 2 I N C n D E C 1 D E C n Figure 7. Increment/Decrement Timing Spec tWRID SCK SI RW VOLTAGE OUT INC/DEC CMD ISSUED REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 12 of 25 X9251 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Device Type Identifier CS Falling Edge 0 1 0 1 Device Addresses Instruction Opcode 0 0 A1 A0 1 0 0 1 WCR Addresses 0 0 0 Wiper Position (Sent by X9251 on SO) W C 0 R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 CS W Rising C Edge R 0 W C R 1 Write Wiper Counter Register (WCR) Device Type Identifier CS Falling Edge 0 1 0 1 Device Addresses Instruction Opcode 0 0 A1 A0 1 0 1 WCR Addresses 0 0 0 0 W C 0 R 7 Data Byte (Sent by Host on SI) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS W Rising C Edge R 0 Read Data Register (DR) Device Type Device Instruction DR and WCR Data Byte CS CS Identifier Addresses Opcode Addresses (Sent by X9271 on SO) Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0 D D D D D D D D Edge 7 6 5 4 3 2 1 0 Device Type Identifier Device Addresses Instruction Opcode DR and WCR Addresses Data Byte (Sent by Host on SI) CS CS Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D D D D D D D D Edge 7 6 5 4 3 2 1 0 HIGH-VOLTAGE WRITE CYCLE Write Data Register (DR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) Device Type CS Identifier Falling Edge 0 1 0 1 Notes: (1) (2) (2) (3) Device Addresses 0 Instruction Opcode DR Addresses CS Rising 0 A1 A0 0 0 0 1 RB RA 0 0 Edge "A1 ~ A0": stands for the device addresses sent by the master. WPx refers to wiper position data in the Counter Register "I": stands for the increment operation, SI held HIGH during active SCK phase (high). "D": stands for the decrement operation, SI held LOW during active SCK phase (high). REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 13 of 25 X9251 Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Device Type Device Instruction DR CS CS Identifier Addresses Opcode Addresses Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 0 0 RB RA 0 0 Edge HIGH-VOLTAGE WRITE CYCLE Transfer Wiper Counter Register (WCR) to Data Register (DR) Device Type Device Instruction DR and WCR CS Identifier Addresses Opcode Addresses Falling Edge 0 1 0 1 0 0 A1 A0 1 1 1 0 RB RA 0 0 CS Rising Edge HIGH-VOLTAGE WRITE CYCLE Transfer Data Register (DR) to Wiper Counter Register (WCR) Device Type Device Instruction DR and WCR CS Identifier Addresses Opcode Addresses Falling Edge 0 1 0 1 0 0 A1 A0 1 1 0 1 RB RA 0 0 CS Rising Edge Increment/Decrement Wiper Counter Register (WCR) Device Type Device Instruction WCR Increment/Decrement CS CS Identifier Addresses Opcode Addresses (Sent by Master on SI) Falling Rising Edge 0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D Edge Read Status Register (SR) Device Type Device Instruction WCR Data Byte CS Identifier Addresses Opcode Addresses (Sent by X9251 on SO) Falling Edge 0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 WIP Notes: (1) (2) (2) (3) CS Rising Edge "A1 ~ A0": stands for the device addresses sent by the master. WPx refers to wiper position data in the Counter Register "I": stands for the increment operation, SI held HIGH during active SCK phase (high). "D": stands for the decrement operation, SI held LOW during active SCK phase (high). REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 14 of 25 X9251 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ....................-65C to +135C Storage temperature .........................-65C to +150C Voltage on SCK, any address input, VCC with respect to VSS.................................. -1V to +7V V = | (VH-VL) | ................................................... 5.5V Lead temperature (soldering, 10 seconds).........300C IW (10 seconds) ................................................. 6mA Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Device Supply Voltage (VCC)(4) Limits Commercial 0C +70C X9251 5V 10% Industrial -40C +85C X9251-2.7 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Parameter Symbol Limits Min. Typ. Max. Units Test Conditions RTOTAL End to End Resistance 100 k T version RTOTAL End to End Resistance 50 k U version End to End Resistance Tolerance 20 % Power Rating 50 mW IW Wiper Current 3 mA RW Wiper Resistance 300 150 VCC V VTERM Voltage on any RH or RL Pin VSS Noise V(VCC) @ VCC = 3V RTOTAL IW = V(VCC) @ VCC = 5V RTOTAL VSS = 0V 0.4 % Absolute Linearity (1) -1 +1 MI(3) Rw(n)(actual) - Rw(n)(expected)(5) Relative Linearity (2) -0.6 +0.6 MI(3) Rw(n + 1) - [Rw(n) + MI](5) 300 Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient CH/CL/CW IW = dBV/ Hz Ref: 1V -120 Resolution 25C, each pot Potentiometer Capacitances -20 ppm/C +20 10/10/25 ppm/C pF See Macro model Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power up VCC > VH, VL, and VW. (5) n = 0, 1, 2, ...,255; m =0, 1, 2, ..., 254. REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 15 of 25 X9251 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions 400 A fSCK = 2.5 MHz, SO = Open, VCC=6V Other Inputs = VSS 5 mA fSCK = 2.5MHz, SO = Open, VCC=6V Other Inputs = VSS ICC1 VCC supply current (active) ICC2 VCC supply current (non-volatile write) ISB VCC current (standby) 3 A SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V ILI Input leakage current 10 A VIN = VSS to VCC ILO Output leakage current 10 A VOUT = VSS to VCC VIH Input HIGH voltage VCC x 0.7 VCC + 1 V VIL Input LOW voltage -1 VCC x 0.3 V VOL Output LOW voltage 0.4 V IOL = 3mA VOH Output HIGH voltage VCC - 0.8 V IOH = -1mA, VCC +3V VOH Output HIGH voltage VCC - 0.4 V IOH = -0.4mA, VCC +3V 1 ENDURANCE AND DATA RETENTION Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years CAPACITANCE Symbol (6) CIN/OUT (6) COUT (6) CIN Test Max. Units Test Conditions Input / Output capacitance (SI) 8 pF VOUT = 0V Output capacitance (SO) 8 pF VOUT = 0V Input capacitance (A0, A1, CS, WP, HOLD, and SCK) 6 pF VIN = 0V POWER-UP TIMING Symbol tr VCC(6) Parameter VCC Power-up rate Min. Max. Units 0.2 50 V/ms (7) Power-up to initiation of read operation 1 ms (7) Power-up to initiation of write operation 50 ms tPUR tPUW A.C. TEST CONDITIONS Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 16 of 25 X9251 EQUIVALENT A.C. LOAD CIRCUIT VCC SPICE Macromodel 2k RTOTAL RH SO pin RL CW CL 2k 10pF CL 10pF 25pF 10pF RW AC TIMING Symbol Parameter Min. Max. Units 2 MHz fSCK SPI clock frequency tCYC SPI clock cycle rime 500 ns tWH SPI clock high rime 200 ns tWL SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 s tFI SI, SCK, HOLD and CS input fall time 2 s tDIS SO output disable time 250 ns tV SO output valid time 200 ns tHO SO output hold time tRO SO output rise time 100 ns tFO SO output fall time 100 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs tCS CS deselect time 2 s tWPASU WP, A0 setup time 0 ns tWPAH WP, A0 hold time 0 ns REV 1.3.3 2/10/04 0 0 www.xicor.com ns 10 Characteristics subject to change without notice. ns 17 of 25 X9251 HIGH-VOLTAGE WRITE CYCLE TIMING Symbol Parameter tWR High-voltage write cycle time (store instructions) Typ. Max. Units 5 10 ms XDCP TIMING Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 s tWRL Wiper response time after instruction issued (all load instructions) 5 10 s SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don't Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance . REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 18 of 25 X9251 TIMING DIAGRAMS Input Timing tCS CS SCK tSU tH ... tWH tWL ... MSB SI tLAG tCYC tLEAD tRI tFI LSB High Impedance SO Output Timing CS SCK ... tV tDIS ... MSB SO SI tHO LSB ADDR Hold Timing CS tHSU tHH SCK ... tRO tFO SO tHZ tLZ SI tHOLD HOLD REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 19 of 25 X9251 XDCP Timing (for All Load Instructions) CS SCK ... tWRL ... MSB SI LSB VWx SO High Impedance Write Protect and Device Address Pins Timing (Any Instruction) CS tWPASU tWPAH WP A0 A1 REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 20 of 25 X9251 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers +VR VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS Voltage Regulator + VO - VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysterisis R2 VS VS - + VO 100K - VO + } } TL072 R1 R2 10K 10K +12V REV 1.3.3 2/10/04 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 10K -12V www.xicor.com Characteristics subject to change without notice. 21 of 25 X9251 Application Circuits (continued) Attenuator Filter C VS + R2 R1 VS VO - - R VO + R3 R4 R2 R1 = R2 = R3 = R4 = 10k R1 GO = 1 + R2/R1 fc = 1/(2RC) VO = G VS -1/2 G +1/2 R1 R2 } } Inverting Amplifier Equivalent L-R Circuit VS R2 C1 - VS VO + + - R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 - + R1 - } RA + } RB frequency R1, R2, C amplitude RA, RB REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 22 of 25 X9251 PACKAGING INFORMATION 24-Bump Chip Scale Package (CSP B24) Package Outline Drawing 9251TRR YWW I LOT # a k f d A4 A3 A2 A1 A4 A3 A2 A1 A4 A3 A2 A1 A4 A3 A2 A1 A4 A3 A2 A1 A4 A3 A2 A1 b m l e j Bottom View (Bumped Side) Top View (Marking Side) Side View e e Side View Ball Matrix 4 3 2 1 A RL1 A1 CS RW0 B RW1 SI WP RL0 C VSS RH1 RH0 VCC D NC RH2 RH3 NC E RW2 HOLD SO RL3 F RL2 SCK A0 RW3 Millimeters Inches Symbol Min Nom. Max Package Width A 2.755 2.785 2.815 Package Length B 4.507 4.537 4.567 Package Height C 0.644 0.677 0.710 Body Thickness D 0.444 0.457 0.470 Ball Height E 0.200 0.220 0.240 Ball Diameter F 0.300 0.320 0.340 Ball Pitch - Width J 0.5 Ball Pitch - Length K 0.5 Ball to Edge Spacing - Width L 0.618 0.643 0.668 Ball to Edge Spacing - Length M 1.056 1.081 1.106 REV 1.3.3 2/10/04 www.xicor.com Min Nom. Characteristics subject to change without notice. Max 23 of 25 X9251 PACKAGING INFORMATION 24-Lead Plastic, TSSOP, Package Code V24 .026 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .303 (7.70) .311 (7.90) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.06) .005 (.15) .010 (.25) Gage Plane 0-8 (4.16) (7.72) Seating Plane .020 (.50) .030 (.75) (1.78) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) ALL MEASUREMENTS ARE TYPICAL See Detail "A" NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 24 of 25 X9251 PACKAGING INFORMATION 24-Lead Plastic, SOIC, Package Code S24 0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45 0.020 (0.50) 0.050" Typical 0 - 8 0.009 (0.22) 0.013 (0.33) 0.420" 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" Typical 24 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) LIMITED WARRANTY (c)Xicor, Inc. 2004 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.3.3 2/10/04 www.xicor.com Characteristics subject to change without notice. 25 of 25