IDT70V05S35PFGI - Integrated Device Technology

MARCH 2000

DSC 2941/6

IDT70V05S/L

HIGH-SPEED 3.3V

8K x 8 DUAL-PORT

STATIC RAM

Features

◆◆

◆True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

◆◆

◆High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

◆◆

◆Low-power operation

– IDT70V05S

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V05L

Active: 380mW (typ.)

Standby: 660

W (typ.)

◆◆

◆IDT70V05 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

◆◆

◆M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

◆◆

◆Interrupt Flag

◆◆

◆On-chip port arbitration logic

◆◆

◆Full on-chip hardware support of semaphore signaling

between ports

◆◆

◆Fully asynchronous operation from either port

◆◆

◆TTL-compatible, single 3.3V (±0.3V) power supply

◆◆

◆Available in 68-pin PGA and PLCC, and a 64-pin TQFP

◆◆

◆Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/WL

CEL

OEL

BUSYL

A12L

A0L

2941 drw 01

I/O0L-I/O

CEL

OEL

R/WL

SEML

INTLM/S

BUSYR

I/O0R-I/O7R

A12R

A0R

SEMR

INTR

CER

OER

(2)

(1,2) (1,2)

(2)

R/WR

CER

OER

R/WR

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Description

The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The

IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port

SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bit-

or-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM

approach in 16-bit or wider memory system applications results in full-

speed, error-free operation without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by CE permits the on-chip circuitry of each port to enter

a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 400mW of power.

The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC

and a 64-pin thin quad flatpack (TQFP).

Pin Configurations(1,2,3)

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. J68-1 package body is approximately .95 in x .95 in x .17 in.

PN64 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate oriention of the actual part-marking

2941 drw 02

INDEX

9 8 7 6 5 4 3 2 1 68676665

27 28 29 30 31 32 33 34 35 36 37 38 39

VCC

I/O1R

I/O2R

I/O3R

I/O4R

INTL

GND

A4L

A3L

A2L

A1L

A0L

A3R

A0R

A1R

A2R

I/O2L A5L

R/W

M/S

26 40 41 42 43

64 63 62 61

I/O3L

GND

I/O0R

VCC

A4R

BUSYL

GND

BUSYR

INTR

12R

I/O

N/C

GND

R/W

SEM

N/C

I/O

IDT70V05J

J68-1(4)

68-Pin PLCC

Top View(5)

I/O4L

I/O5L

I/O6L

I/O7L

I/O5R

I/O6R

N/C

12L

11R

N/C

10R

11L

10L

N/C

INDEX

70V05PF

PN-64(4)

64-Pin TQFP

Top View(5)

I/O2L

VCC

GND

A4R

BUSYL

BUSYR

INTR

INTL

GND

M/S

A5L

I/O1L

SEM

VCC

N/C

SEM

A12R

GND

I/O3L

I/O4L

I/O5L

I/O6L

I/O7L

I/O0R

I/O1R

I/O2R

VCC

I/O3R

I/O4R

I/O5R

I/O6R

I/O7R

A11R

A10R

A9R

A8R

A7R

A6R

A5R

A3R

A2R

A1R

A0R

A0L

A1L

A2L

A3L

A4L

A6L

A7L

A8L

A9L

A10L

A11L

A12L

I/O0L

2941 drw 03

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Pin Names

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.18 in x 1.18 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate oriention of the actual part-marking.

Pin Configurations(1,2,3) (con't.)

2941 drw 04

51 50 48 46 44 42 40 38 36

1357911 13 15

IDT70V05G

G68-1(4)

68-Pin PGA

Top View(5)

ABCDEFGHJKL

47 45 43 41 34

246810121416

18 19

49 39 37

A5L

INTL

N/C

SEMLCEL

VCC

OELR/WL

I/O0L N/C

GND GND

I/O0R

VCC N/C

OERR/WR

SEMRCER

GND BUSYR

BUSYLM/SINTR

N/C

GND

A1R

N/C

INDEX

A4L A2L A0L A3R

A2R A4R A5R

A7R A6R

A9R A8R

A11R A10R

A12R

A0R

A7L A6L A3L A1L

A9L A8L

A11L A10L

A12L

VCC I/O2R I/O3R I/O5R I/O6R

I/O1R I/O4R I/O7R

I/O1L I/O2L I/O4L I/O7L

I/O3L I/O5L I/O6L

Left Port Right Port Names

CELCERChip Enable

R/WLR/WRRead/Write Enabl e

OELOEROutp ut Enabl e

A0L - A12L A0R - A12R Address

I/O0L - I/O7L I/O0R - I/O7R Data Input/Outp ut

SEMLSEMRSemaphore Enable

INTLINTRInte rrupt Fl ag

BUSYLBUSYRBusy Flag

M/SMaster or Slave Select

VCC Power

GND Ground

2941 t b l 01

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Truth Table: Non-Contention Read/Write Control

Truth Table II: Semaphore Read/Write Control(1)

NOTE:

1. A0L — A12L≠ A0R — A12R

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from I/O0 -I/O 7. These eight semaphores are addressed by A0-A2.

Inputs(1) Outputs

Mode

CE R/WOE SEM I/O0-7

H X X H Hig h-Z Des ele cted : P owe r-Down

LLXHDATA

IN Wri te to Me m ory

LHLHDATA

OUT Read Me mory

X X H X High-Z Outputs Disabled

2941 tbl 02

Inputs(1) Outputs

Mode

CE R/WOE SEM I/O0-7

HHLLDATA

OUT Read Data in Semaphore Flag

H↑XLDATA

IN Write I/O0 into Semaphore Flag

LXXL ____ Not Allo we d

2941 tbl 03

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)

Recommended DC Operating

Conditions

Maximum Operating Temperature

and Supply Voltage(1)

Absolute Maximum Ratings(1)

Capacitance (TA = +25°C, f = 1.0MHz)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 0.3V.

NOTE:

1. This is the parameter TA.

NOTES:

1. VIL> -1.5V for pulse width less than 10ns.

2. VTERM must not exceed VCC +0.3V.

Symbol Rating Commercial

& I nd ustria l Unit

VTERM(2) Terminal Vo ltage

with Re s p e ct

to GND

-0.5 to +4.6 V

TBIAS Temperature

Under Bias -55 to +125 oC

TSTG Storage

Temperature -55 to +125 oC

IOUT DC Outp ut

Current 50 mA

2941 tbl 04

Grade Ambient

Temperature GND Vcc

Commercial 0OC to +70OC0V3.3V

+ 0.3V

Industrial -40OC to +85OC0V3.3V

+ 0.3V

2941 tbl 05

Symbol Parameter Min. Typ. Max. Unit

VCC Supp ly Vo ltage 3. 0 3. 3 3. 6 V

GND Ground 0 0 0 V

VIH In p ut Hi g h Vo ltag e 2. 0 ____ VCC+0.3(2) V

VIL Inp ut Lo w Vo ltag e -0.5(1) ____ 0.8 V

2941 tbl 06

Symbol Parameter(1) Conditions Max. Unit

CIN Inp ut Cap ac i tance VIN = 3dV 9 pF

COUT Outp ut Cap acitanc e VOUT = 3dV 10 pF

2941 tbl 07

Symbol Parameter Test Conditions

70V05S 70V05L

UnitMin. Max. Min. Max.

|ILI| Input Le ak ag e Curre nt(1) VCC = 3.6V, VIN = 0V to VCC ___ 10 ___ 5µA

|ILO| Outp ut Le ak age Curre nt VOUT = 0V to VCC ___ 10 ___ 5µA

VOL Outp ut Lo w Vo ltag e IOL = +4mA ___ 0.4 ___ 0.4 V

VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V

2941 t bl 0 8

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV references the interpolated capacitznce when the input and output signals

switch from 0V to 3V or from 3V to 0V.

NOTE:

1. At VCC < 2.0V input leakages are undefined.

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)

NOTES:

1. “X” in part number indicates power rating (S or L)

2. VCC = 3.3V, TA = +25°C.

3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of

GND to 3V.

4. f = 0 means no address or control lines change.

70V05X15

Com'l Only 70V05X20

Com'l

& I nd

70V05X25

Com'l

& I nd

Symbol Parameter Test Condition Version Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit

ICC Dy n am i c O p er ati ng

Current

(Both Ports Active)

CE = VIL, Outp uts Ope n

SEM = VIH

f = fMAX(3)

COM'L S

L150

140 215

185 140

130 200

175 130

125 190

165 mA

IND S

L____

____

____ 140

130 225

195 130

125 210

180 mA

ISB1 Standby Current

(Bo th Po rts - TTL

Lev el Inputs)

CER = CEL = VIH

SEMR = SEML = VIH

f = fMAX(3)

COM'L S

L25

20 35

30 20

15 30

25 16

13 30

25 mA

IND S

L____

____

____ 20

15 45

40 16

13 45

40 mA

ISB2 Standby Current

(One Po rt - TTL

Lev el Inputs)

CEL or CER = VIH

Ac tive P ort Outp uts Ope n,

f=fMAX(3)

COM'L S

L85

80 120

110 80

75 110

100 75

72 110

95 mA

IND S

L____

____

____ 80

75 130

115 75

72 125

110 mA

ISB3 Full Standb y Curre nt

(Bo th Po rts -

CMOS Le ve l Inp uts )

Both Po rts CEL and

CER > VCC - 0.2V,

VIN > VCC - 0.2V or

VIN < 0.2V, f = 0(4)

SEMR = SEML > VCC - 0.2V

COM'L S

L1.0

0.2 5

2.5 1.0

0.2 5

2.5 1.0

0.2 5

2.5 mA

IND S

L____

____

____ 1.0

0.2 15

51.0

0.2 15

5mA

ISB4 Full Standb y Curre nt

(One Po rt -

CMOS Le ve l Inp uts )

One Port CEL or

CER > VCC - 0.2V

SEMR = SEML > VCC - 0.2V

VIN > VCC - 0.2V or VIN < 0.2V

Ac tive P ort Outp uts Ope n,

f = fMAX(3)

COM'L S

L85

80 125

105 80

75 115

100 75

70 105

90 mA

IND S

L____

____

____ 80

75 130

115 75

70 120

105 mA

2 941 tb l 09a

70V05X35

Com'l

& I nd

70V05X55

Com'l

& I nd

Symbol Parameter Test Condition Version Typ.(2) Max. Typ.(2) Max. Unit

ICC Dy nam ic Op e rating

Current

(Bo th Po rts Active )

CE = VIL, Outp uts Ope n

SEM = VIH

f = fMAX(3)

COM'L S

L120

115 180

155 120

115 180

155 mA

IND S

L120

115 200

170 120

115 200

170 mA

ISB1 Standby Current

(Bo th Po rts - TTL

Le v el Inp uts )

CER = CEL = VIH

SEMR = SEML = VIH

f = fMAX(3)

COM'L S

L13

11 25

20 13

11 25

20 mA

IND S

L13

11 40

35 13

11 40

35 mA

ISB2 Standby Current

(One Po rt - TTL

Le v el Inp uts )

CEL or CER = VIH

A cti ve Po rt Outputs Op e n,

f=fMAX(3)

COM'L S

L70

65 100

90 70

65 100

90 mA

IND S

L70

65 120

105 70

65 120

105 mA

ISB3 Full Stand by Current

(Bo th Po rts -

CM OS L e vel In p uts )

Both Ports CEL and

CER > VCC - 0. 2V,

VIN > VCC - 0. 2V o r

VIN < 0.2V, f = 0(4)

SEMR = SEML > VCC - 0 .2V

COM'L S

L1.0

0.2 5

2.5 1.0

0.2 5

2.5 mA

IND S

L1.0

0.2 15

51.0

0.2 15

5mA

ISB4 Full Stand by Current

(One Po rt -

CM OS L e vel In p uts )

One P o rt CEL or

CER > VCC - 0. 2V

SEMR = SEML > VCC - 0 .2V

VIN > VCC - 0 . 2V or V IN < 0.2V

A cti ve Po rt Outputs Op e n,

f = fMAX(3)

COM'L S

L65

60 100

85 65

60 100

85 mA

IND S

L65

60 115

100 65

60 115

100 mA

2941 t bl 0 9b

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

AC Test Conditions

Timing of Power-Up Power-Down

Figure 1. AC Output Test Load Figure 2. Output Test Load

*Including scope and jig.

(For tLZ, tHZ, tWZ, tOW)

2941 drw 06

tPU

ICC

ISB

tPD

50% 50% ,

Input Pulse Levels

Inp ut Ris e/ Fal l Time s

Inp ut Timi ng Re fe re nc e Le v els

Outp ut Refe re nce Le v e ls

Output Load

GND to 3.0V

3ns Max .

1.5V

Fi g ure s 1 and 2

2941 tbl 10 2941 drw 05

590Ω

30pF

435Ω

3.3V

DATAOUT

BUSY

INT

590Ω

5pF*

435Ω

3.3V

DATAOUT

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is determined by device characterization but is not production tested.

3. To access SRAM, CE = VIL, SEM = VIH.

4. 'X' in part number indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

70V05X15

Com'l Only 70V05X20

Com'l

& Ind

70V05X25

Com'l

& Ind

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

tRC Read Cyc le Time 15 ____ 20 ____ 25 ____ ns

tAA Add ress Access Time ____ 15 ____ 20 ____ 25 ns

tACE Chip Enable Access Time(3) ____ 15 ____ 20 ____ 25 ns

tAOE Output Enable Acc ess Time (3) ____ 10 ____ 12 ____ 13 ns

tOH Output Hold from Address Change 3 ____ 3____ 3____ ns

tLZ Output Lo w-Z Time(1,2) 3____ 3____ 3____ ns

tHZ Output High-Z Tim e(1,2) ____ 10 ____ 12 ____ 15 ns

tPU Chip E nab le to P owe r Up Ti me (1,2) 0____ 0____ 0____ ns

tPD Chi p Dis able to Po wer Do wn Ti me(1,2) ____ 15 ____ 20 ____ 25 ns

tSOP Semaphore Flag Update Pulse (OE or SEM)10

____ 10 ____ 10 ____ ns

tSAA Semaphore Address Access(3) ____ 15 ____ 20 ____ 25 ns

2941 tbl 11a

70V05X35

Com'l

& Ind

70V05X55

Com'l

& Ind

UnitSymbol Parameter Min. Max. Min. Max.

READ CYCLE

tRC Read Cyc le Time 35 ____ 55 ____ ns

tAA Add ress Access Time ____ 35 ____ 55 ns

tACE Chip Enable Access Time(3) ____ 35 ____ 55 ns

tAOE Output Enable Acc ess Time (3) ____ 20 ____ 30 ns

tOH Output Hold from Address Change 3 ____ 3____ ns

tLZ Output Lo w-Z Time(1,2) 3____ 3____ ns

tHZ Output High-Z Tim e(1,2) ____ 15 ____ 25 ns

tPU Chip E nab le to P owe r Up Ti me (1,2) 0____ 0____ ns

tPD Chi p Dis able to Po wer Do wn Ti me(1,2) ____ 35 ____ 50 ns

tSOP Semaphore Flag Update Pulse (OE or SEM)15

____ 15 ____ ns

tSAA Semaphore Address Access(3) ____ 35 ____ 55 ns

2941 tbl 11b

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles(5)

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no

relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = V IH.

tRC

R/W

ADDR

tAA

2941 drw 07

(4)

tACE(4)

tAOE(4)

(1)

tLZ tOH

(2)

tHZ

(3,4)

tBDD

DATAOUT

BUSYOUT

VALID DATA(4)

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is determined by device characterization but is not production tested.

3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and

temperature, the actual tDH will always be smaller than the actual tOW.

5. “X” in part number indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(5)

Symbol Parameter

70V05X15

Com'l Only 70V05X20

Com'l

& Ind

70V05X25

Com'l

& Ind

UnitMin. Max. Min. Max. Min. Max.

WRITE CYCLE

tWC Wri te Cy c l e Tim e 15 ____ 20 ____ 25 ____ ns

tEW Chip Enable to End -o f-Write (3) 12 ____ 15 ____ 20 ____ ns

tAW Address Valid to End-o f-Write 12 ____ 15 ____ 20 ____ ns

tAS Ad dress Set-up Time (3) 0____ 0____ 0____ ns

tWP Write Pulse Width 12 ____ 15 ____ 20 ____ ns

tWR Write Re cove ry Time 0 ____ 0____ 0____ ns

tDW Da ta Vali d to E nd -o f-W rite 10 ____ 15 ____ 15 ____ ns

tHZ Outp ut Hig h-Z Time (1,2) ____ 10 ____ 12 ____ 15 ns

tDH Da ta Hold Ti me (4) 0____ 0____ 0____ ns

tWZ Write Enabl e to Output in High-Z(1,2) ____ 10 ____ 12 ____ 15 ns

tOW Output Active from End-of-Write(1,2,4) 0____ 0____ 0____ ns

tSWRD SEM Fl ag Write to Re ad Ti me 5____ 5____ 5____ ns

tSPS SEM Fl ag Co nte ntio n Wi ndo w 5____ 5____ 5____ ns

2 941 tb l 12a

Symbol Parameter

70V05X35

Com'l

& Ind

70V05X55

Com'l

& Ind

UnitMin. Max. Min. Max.

WRI TE CYCLE

tWC Write Cycle Time 35 ____ 55 ____ ns

tEW Chip Enable to End-of-Write(3) 30 ____ 45 ____ ns

tAW Ad dres s Valid to End -of-Write 30 ____ 45 ____ ns

tAS Ad dres s Se t-up Time (3) 0____ 0____ ns

tWP Write Pulse Width 25 ____ 40 ____ ns

tWR Wr ite Re c o v e ry Ti me 0 ____ 0____ ns

tDW Data Valid to End-of-Write 15 ____ 30 ____ ns

tHZ Output Hig h-Z Ti me(1,2) ____ 15 ____ 25 ns

tDH Da ta Ho l d Tim e (4) 0____ 0____ ns

tWZ Write Enabl e to Output in High-Z(1,2) ____ 15 ____ 25 ns

tOW Outp ut Ac ti v e from E nd -o f -Wri te (1,2,4) 0____ 0____ ns

tSWRD SEM Flag Write to Read Time 5____ 5____ ns

tSPS SEM Flag Conte ntion Window 5____ 5____ ns

2941 tbl 12b

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE, or R/W.

7. Timing depends on which enable signal is de-asserted first, CE, or R/W.

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the

bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

9. To access RAM, CE = VIL and SEM = VIN. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)

2941 drw 09

tWC

tAS tWR

tDW tDH

ADDRESS

DATAIN

CE or SEM

R/W

tAW

tEW (3)(2)(6)

(9)

R/W

tWC

tHZ

tAW

tWR

tAS tWP

DATAOUT

(2)

tWZ

tDW tDH

tOW

ADDRESS

DATAIN

(6)

(4) (4)

(3)

2941 drw 08

(7)

or SEM (9)

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

NOTE:

1. CE = VIH for the duration of the above timing (both write and read cycle).

2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention(1,3,4)

SEM"A"

2941drw 11

tSPS

MATCH

R/W"A"

MATCH

A0"A"-A2"A"

SIDE "A"

(2)

SEM"B"

R/W"B"

A0"B"-A2"B"

SIDE "B"

(2)

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

2. “A” may be either left or right port. “B” is the opposite port from “A”.

3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.

4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

SEM

2941 drw 10

tAW tEW

tSOP

DATA0

VALID ADDRESS

tSAA

R/W

tWR

tOH

tACE

VALID ADDRESS

DATAIN VALID DATA OUT

tDW

tWP tDH

tAS

tSWRD tAOE

tSOP

Read Cycle

Write Cycle

A0-A2

VALID(2)

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. Port-to-port delay through SRAM cells from writing port to reading port, refer to “Timing Waveform of Read With BUSY (M/S = VIH)” or “Timing Waveform of Write With Port-

To-Port Delay (M/S = VIL)”.

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited during contention.

5. To ensure that a write cycle is completed after contention.

6. 'X' is part number indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(6)

70V05X15

Co m' l On y 70V05X20

Com'l

& Ind

70V05X25

Com'l

& Ind

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

BUSY TIMING (M/S = VIH)

tBAA BUSY Access Time from Add ress Match ____ 15 ____ 20 ____ 20 ns

tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 20 ns

tBAC BUSY Access Time from Chip Enable LOW ____ 15 ____ 20 ____ 20 ns

tBDC BUSY Dis able Time from Chip Enable HIGH ____ 15 ____ 17 ____ 17 ns

tAPS Arbitratio n Priority Set-up Time (2) 5____ 5____ 5____ ns

tBDD BUSY Di s ab l e to Va li d Data(3) ____ 18 ____ 30 ____ 30 ns

tWH Wri te Hold Afte r BUSY(5) 12 ____ 15 ____ 17 ____ ns

BUSY TIMING (M/S = VIL)

tWB BUSY Input to Wr ite(4) 0____ 0____ 0____ ns

tWH Wri te Hold Afte r BUSY(5) 12 ____ 15 ____ 17 ____ ns

PORT-TO-PORT DELAY TIM ING

tWDD Wr i te Pu ls e to Data De l ay (1) ____ 30 ____ 45 ____ 50 ns

tDDD Wri te Da ta Va li d to Re ad Data De l ay(1) ____ 25 ____ 35 ____ 35 ns

2 941 tb l 13 a

70V05X35

Com'l

& Ind

70V05X55

Com'l

& Ind

Symbol Parameter Min. Max. Min. Max. Unit

BUSY TIMING (M/ S = VIH)

tBAA BUSY Access Time fro m Add ress Match ____ 20 ____ 45 ns

tBDA BUSY Di s ab le Tim e from A d d res s No t M atc he d ____ 20 ____ 40 ns

tBAC BUSY Acce ss Time fro m Chip Enable LOW ____ 20 ____ 40 ns

tBDC BUSY Dis able Time fro m Chip Enab le HIGH ____ 20 ____ 35 ns

tAPS Arb i trati o n P rio rity Se t-up Time(2) 5____ 5____ ns

tBDD BUSY Di s ab l e to Vali d Data (3) ____ 35 ____ 40 ns

tWH Write Hold A fte r BUSY(5) 25 ____ 25 ____ ns

BUSY TIMING (M/ S = VIL)

tWB BUSY Inp u t to Wr ite (4) 0____ 0____ ns

tWH Write Hold A fte r BUSY(5) 25 ____ 25 ____ ns

P ORT -T O-P ORT DE LAY TI M ING

tWDD Write P ulse to Data Delay(1) ____ 60 ____ 80 ns

tDDD Write Data Valid to Read Data Delay (1) ____ 45 ____ 65 ns

2941 tbl 13b

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

2941 drw 12

tDW

tAPS

ADDR"A"

tWC

DATAOUT "B"

MATCH

tWP

R/W"A"

DATAIN "A"

ADDR"B"

tDH

VALID

(1)

MATCH

BUSY"B"

tBDA

VALID

tBDD

tDDD(3)

tWDD

tBAA

Timing Waveform of Write with Port-to-Port Read with BUSY(2,4,5)

(M/S=VIH)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (SLAVE) then BUSY is input. For this example, BUSY“A” = VIH and BUSY“B” input is shown above.

5. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the port opposite from Port “A”.

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with BUSY

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing(1) (M/S = VIH)

Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)

NOTES:

1. tWH must be met for both BUSY input (slave) and output (master).

2. BUSY is asserted on port “B” Blocking R/W“B”, until BUSY“B” goes HIGH.

3. tWB is only for the slave version.

2941 drw 13

R/W"A"

BUSY"B"

tWP

tWB

R/W"B"

tWH(1)

(2)

(3)

2941 drw 14

ADDR"A"

and "B" ADDRESSES MATCH

CE"A"

CE"B"

BUSY"B"

tAPS

tBAC tBDC

(2)

2941 drw 15

ADDR"A" ADDRESS "N"

ADDR"B"

BUSY"B"

tAPS

tBAA tBDA

(2)

MATCHING ADDRESS "N"

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1)

NOTES:

1. 'X' in part number indicates power rating (S or L).

70V05X15

Com'l Only 70V05X20

Com'l

& Ind

70V05X25

Com'l

& Ind

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTE RRUP T TIMING

tAS Address Set-up Time 0 ____ 0____ 0____ ns

tWR Write Reco very Time 0 ____ 0____ 0____ ns

tINS Inte rrup t Set Time ____ 15 ____ 20 ____ 20 ns

tINR Inte rrup t Res et Time ____ 15 ____ 20 ____ 20 ns

2941 tbl 14 a

70V05X35

Com'l

& Ind

70V05X55

Com'l

& Ind

Symbol Parameter Min. Max. Min. Max. Unit

INTE RRUP T TIMING

tAS Address Set-up Time 0 ____ 0____ ns

tWR Write Reco very Time 0 ____ 0____ ns

tINS Inte rrup t Set Time ____ 25 ____ 40 ns

tINR Inte rrup t Res et Time ____ 25 ____ 40 ns

2941 t bl 1 4b

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

2941 drw 17

ADDR"B" INTERRUPT CLEAR ADDRESS

CE"B"

OE"B"

tAS

tRC

(3)

tINR(3)

INT"B"

(2)

Waveform of Interrupt Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

2941 drw 16

ADDR"A" INTERRUPT SET ADDRESS

CE"A"

R/W"A"

tAS

tWC

tWR

(3) (4)

tINS(3)

INT"B"

(2)

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Truth Table IV  Address BUSY

Arbitration

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push

pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.

2. VIL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and

enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when

BUSYR outputs are driving low regardless of actual logic level on the pin.

Truth Table V  Example of Semaphore Procurement Sequence(1,2,3)

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Truth Table III  Interrupt Flag(1)

NOTES:

1. Assumes BUSYL = BUSYR = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

Left Port Right Port

FunctionR/WLCE

LOELA12L-A0L INTLR/WRCEROERA12R-A0R INTR

LLX1FFFXXXX X L

(2) Set Right INTR Flag

XXXXXXLL1FFF H

(3) Re set Rig ht INTR Flag

XXX X L

(3) L L X 1FFE X Se t Left INTL Flag

XLL1FFE H

(2) X X X X X Re s et Le ft INTL Flag

2941tbl 15

Inputs Outputs

Function

CELCERA12L-A0L

A12R-A0R BUSYL(1) BUSYR(1)

XXNO MATCHHHNormal

HXMATCHHHNormal

XHMATCHHHNormal

L L MATCH (2) (2) Write Inhib it(3)

2941 tbl 16

Functions D0 - D7 Left D0 - D7 Right Status

No Action 1 1 Se maphore free

Left Port Writes "0" to Semaphore 0 1 Left po rt has semaphore token

Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore 1 0 Right p ort obtains semap hore token

Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Le ft Po rt Write s "1" to Se map ho re 1 1 Se map ho re free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left po rt has semaphore token

Le ft Po rt Write s "1" to Se map ho re 1 1 Se map ho re free

2941 tbl 17

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Functional Description

The IDT70V05 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT70V05 has an automatic power down

feature controlled by CE. The CE controls on-chip power down circuitry

that permits the respective port to go into a standby mode when not

selected (CE HIGH). When a port is enabled, access to the entire

memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt

flag (INTL) is set when the right port writes to memory location 1FFE

(HEX). The left port clears the interrupt by reading address location

1FFE. Likewise, the right port interrupt flag (INTR) is set when the left

port writes to memory location 1FFF (HEX) and to clear the interrupt

flag (INTR), the right port must read the memory location 1FFF. The

message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt

function is not used, address locations 1FFE and 1FFF are not used

as mail boxes, but as part of the random access memory. Refer to

Truth Table III for the interrupt operation.

Busy Logic

Busy Logic provides a hardware indication that both ports of the

SRAM have accessed the same location at the same time. It also

allows one of the two accesses to proceed and signals the other side

that the SRAM is “busy”. The BUSY pin can then be used to stall the

access until the operation on the other side is completed. If a write

operation has been attempted from the side that receives a BUSY

indication, the write signal is gated internally to prevent the write from

proceeding.

The use of BUSY logic is not required or desirable for all applica-

tions. In some cases it may be useful to logically OR the BUSY outputs

together and use any BUSY indication as an interrupt source to flag the

event of an illegal or illogical operation. If the write inhibit function of

BUSY logic is not desirable, the BUSY logic can be disabled by placing

the part in slave mode with the M/S pin. Once in slave mode the BUSY

pin operates solely as a write inhibit input pin. Normal operation can be

programmed by tying the BUSY pins HIGH. If desired, unintended

write operations can be prevented to a port by tying the BUSY pin for

that port LOW.

The BUSY outputs on the IDT 70V05 SRAM in master mode, are

push-pull type outputs and do not require pull up resistors to

operate. If these SRAMs are being expanded in depth, then the

BUSY indication for the resulting array requires the use of an external

AND gate.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT70V05 SRAM array in width while using

BUSY logic, one master part is used to decide which side of the RAM

array will receive a BUSY indication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master, use the BUSY signal as a write inhibit signal. Thus on the

IDT70V05 SRAM the BUSY pin is an output if the part is used as a

master (M/S pin = VIH), and the BUSY pin is an input if the part used

as a slave (M/S pin = VIL) as shown in Figure 3.

If two or more master parts were used when expanding in width, a

split decision could result with one master indicating BUSY on one side

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for the

other part of the word.

The BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actual write pulse can be initiated with the R/W signal. Failure to

observe this timing can result in a glitched internal write inhibit signal

and corrupted data in the slave.

Semaphores

The IDT70V05 is a fast Dual-Port 8K x 8 CMOS Static RAM with

an additional 8 address locations dedicated to binary semaphore flags.

These flags allow either processor on the left or right side of the Dual-

Port SRAM to claim a privilege over the other processor for functions

defined by the system designer’s software. As an example, the

semaphore can be used by one processor to inhibit the other from

accessing a portion of the Dual-Port SRAM or any other shared

resource.

The Dual-Port SRAM features a fast access time, and both ports are

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs.

2941 drw 18

MASTER

Dual Port

SRAM

BUSY (L) BUSY (R)

MASTER

Dual Port

SRAM

BUSY (L) BUSY (R)

SLAVE

Dual Port

SRAM

BUSY (L) BUSY (R)

SLAVE

Dual Port

SRAM

BUSY (L) BUSY (R)

DECODER

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

completely independent of each other. This means that the activity on the

left port in no way slows the access time of the right port. Both ports are

identical in function to standard CMOS Static RAM and can be read from,

or accessed, at the same time with the only possible conflict arising from

the simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphore location. Semaphores are protected against such ambiguous

situations and may be used by the system program to avoid any conflicts

in the non-semaphore portion of the Dual-Port SRAM. These devices

have an automatic power-down feature controlled by CE, the Dual-Port

SRAM enable, and SEM, the semaphore enable. The CE and SEM pins

control on-chip power down circuitry that permits the respective port to go

into standby mode when not selected. This is the condition which is shown

in Truth Table II where CE and SEM are both HIGH.

Systems which can best use the IDT70V05 contain multiple processors

or controllers and are typically very high-speed systems which are

software controlled or software intensive. These systems can benefit from

a performance increase offered by the IDT70V05's hardware sema-

phores, which provide a lockout mechanism without requiring complex

programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70V05 does not use its semaphore

flags to control any resources through hardware, thus allowing the

system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port SRAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignment method called “Token Passing Allocation.” In this method,

the state of a semaphore latch is used as a token indicating that shared

resource is in use. If the left processor wants to use this resource, it

requests the token by setting the latch. This processor then verifies its

success in setting the latch by reading it. If it was successful, it

proceeds to assume control over the shared resource. If it was not

successful in setting the latch, it determines that the right side

processor has set the latch first, has the token and is using the shared

resource. The left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of

the token via the set and test sequence. Once the right side has

relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active low. A token is requested by writing

a zero into a semaphore latch and is released when the same side

writes a one to that latch.

The eight semaphore flags reside within the IDT70V05 in a

separate memory space from the Dual-Port SRAM. This address

space is accessed by placing a LOW input on the SEM pin (which acts

as a chip select for the semaphore flags) and using the other control

pins (Address, OE, and R/W) as they would be used in accessing a

standard Static RAM. Each of the flags has a unique address which can

be accessed by either side through address pins A0 – A2. When accessing

the semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a LOW level

is written into an unused semaphore location, that flag will be set to a zero

on that side and a one on the other side (see Truth Table V). That

semaphore can now only be modified by the side showing the zero. When

a one is written into the same location from the same side, the flag will be

set to a one for both sides (unless a semaphore request from the other side

is pending) and then can be written to by both sides. The fact that the side

which is able to write a zero into a semaphore subsequently locks out writes

from the other side is what makes semaphore flags useful in interprocessor

communications. (A thorough discussion on the use of this feature follows

shortly.) A zero written into the same location from the other side will be

stored in the semaphore request latch for that side until the semaphore is

freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing

a zero reads as all zeros. The read value is latched into one side’s output

signals go active. This serves to disallow the semaphore from changing

state in the middle of a read cycle due to a write cycle from the other side.

Because of this latch, a repeated read of a semaphore in a test loop must

cause either signal (SEM or OE) to go inactive or the output will never

change.

A sequence WRITE/READ must be used by the semaphore in

order to guarantee that no system level contention will occur. A

processor requests access to shared resources by attempting to write

a zero into a semaphore location. If the semaphore is already in use,

the semaphore request latch will contain a zero, yet the semaphore

flag will appear as one, a fact which the processor will verify by the

subsequent read (see Truth Table V). As an example, assume a

processor writes a zero to the left port at a free semaphore location. On

a subsequent read, the processor will verify that it has written success-

fully to that location and will assume control over the resource in

question. Meanwhile, if a processor on the right side attempts to write

a zero to the same semaphore flag it will fail, as will be verified by the

fact that a one will be read from that semaphore on the right side during

subsequent read. Had a sequence of READ/WRITE been used

instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be

followed by either repeated reads or by writing a one into the same

location. The reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the semaphore flag will force its side of the

semaphore flag LOW and the other side HIGH. This condition will

continue until a one is written to the same semaphore request latch.

Should the other side’s semaphore request latch have been written to

a zero in the meantime, the semaphore flag will flip over to the other

side as soon as a one is written into the first side’s request latch. The

second side’s flag will now stay LOW until its semaphore request latch

is written to a one. From this it is easy to understand that, if a

semaphore is requested and the processor which requested it no longer

needs the resource, the entire system can hang up until a one is written

into that semaphore request latch.

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

2941 drw 19

WRITE D0D

QWRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

LPORT RPORT

SEMAPHORE

READ SEMAPHORE

READ

The critical case of semaphore timing is when both sides request a

single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If

simultaneous requests are made, the logic guarantees that only one

side receives the token. If one side is earlier than the other in making

the request, the first side to make the request will receive the token. If

both requests arrive at the same time, the assignment will be arbitrarily

made to one port or the other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is

secure. As with any powerful programming technique, if semaphores

are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be

handled via the initialization program at power-up. Since any sema-

phore request flag which contains a zero must be reset to a one, all

semaphores on both sides should have a one written into them at

initialization from both sides to assure that they will be free when

needed.

Using SemaphoresSome Examples

Perhaps the simplest application of semaphores is their applica-

tion as resource markers for the IDT70V05’s Dual-Port SRAM. Say the

8K x 8 SRAM was to be divided into two 4K x 8 blocks which were to be

dedicated at any one time to servicing either the left or right port.

Semaphore 0 could be used to indicate the side which would control

the lower section of memory, and Semaphore 1 could be defined as the

indicator for the upper section of memory.

To take a resource, in this example the lower 4K of Dual-Port

SRAM, the processor on the left port could write and then read a

zero in to Semaphore 0. If this task were successfully completed

(a zero was read back rather than a one), the left processor would

assume control of the lower 4K. Meanwhile the right processor was

attempting to gain control of the resource after the left processor, it

would read back a one in response to the zero it had attempted to

write into Semaphore 0. At this point, the software could choose to try

and gain control of the second 4K section by writing, then reading a zero

into Semaphore 1. If it succeeded in gaining control, it would lock out

the left side.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could undo

its semaphore request and perform other tasks until it was able to write, then

read a zero into Semaphore 1. If the right processor performs a similar task

with Semaphore 0, this protocol would allow the two processors to swap

4K blocks of Dual-Port SRAM with each other.

The blocks do not have to be any particular size and can even be

variable, depending upon the complexity of the software using the

semaphore flags. All eight semaphores could be used to divide the

Dual-Port SRAM or other shared resources into eight parts. Semaphores

can even be assigned different meanings on different sides rather than

being given a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like disk

interfaces where the CPU must be locked out of a section of memory

during a transfer and the I/O device cannot tolerate any wait states.

With the use of semaphores, once the two devices has determined

which memory area was “off-limits” to the CPU, both the CPU and the

I/O devices could access their assigned portions of memory continu-

ously without any wait states.

Semaphores are also useful in applications where no memory

“WAIT” state is available on one or both sides. Once a semaphore

handshake has been performed, both processors can access their

assigned SRAM segments at full speed.

Another application is in the area of complex data structures. In this

case, block arbitration is very important. For this application one

processor may be responsible for building and updating a data

structure. The other processor then reads and interprets that data

structure. If the interpreting processor reads an incomplete data

structure, a major error condition may exist. Therefore, some sort of

arbitration must be used between the two different processors. The

building processor arbitrates for the block, locks it and then is able to

go in and update the data structure. When the update is completed, the

data structure block is released. This allows the interpreting processor

to come back and read the complete data structure, thereby guaran-

teeing a consistent data structure.

Figure 4. IDT70V05 Semaphore Logic

6.42

IDT70V05S/L

High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Ordering Information

2941 drw 20

Power

999

Speed

Package

Process/

Temperature

Range

Blank

ICommercial (0°Cto+70

°C)

Industrial (-40°Cto+85

°C)

64-pin TQFP (PN64-1)

68-pin PGA (G68-1)

68-pin PLCC (J68-1)

LStandard Power

Low Power

XXXXX

Device

Type

64K (8K x 8) 3.3V Dual-Port RAM

70V05

IDT

Speed in nanoseconds

Commercial Only

Commercial & Industrial

Datasheet Document History

3/11/99: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Page 2 and 3 Added additional notes to pin configurations

6/9/99: Changed drawing format

11/10/99: Replaced IDT logo

3/10/00: Added 15 & 20ns speed grades

Upgraded DC parameters

Added Industrial Temperature information

Changed ±200mV to 0mV in notes

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613

Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com

www.idt.com

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