CMOS CLOCKED FIFO WITH
BUS-MATCHING AND
BYTE SWAPPING 64 x 36
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3145/1
IDT723613
MARCH 2002
IDT and the IDT logo are registered trademarks of Integrated Device Technology Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©
FEATURES:
••
••
•Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of data on
a single clock edge)
••
••
•64 x 36 storage capacity FIFO buffering data from Port A to
Port B
••
••
•Mailbox bypass registers in each direction
••
••
•Dynamic Port B bus sizing of 36 bits (long word), 18-bits (word),
and 9 bits (byte)
••
••
•Selection of Big- or Little-Endian format for word and byte bus
sizes
••
••
•Three modes of byte-order swapping on Port B
••
••
•Programmable Almost-Full and Almost-Empty flags
••
••
•Microprocessor interface control logic
••
••
•FF, AF flags synchronized by CLKA
••
••
•EF, AE flags synchronized by CLKB
••
••
•Passive parity checking on each Port
••
••
•Parity Generation can be selected for each Port
••
••
•Supports clock frequencies up to 67 MHz
••
••
•Fast access times of 10 ns
••
••
•Available in 132-pin quad flatpack (PQFP) or space-saving
120-pin thin quad flatpack (TQFP)
••
••
•Industrial temperature range (–40 °°
°°
°C to +85°°
°°
°C) is available
DESCRIPTION:
The IDT723613 is a monolithic, high-speed, low-power, CMOS synchro-
nous (clocked) FIFO memory which supports clock frequencies up to 67 MHz
and has read-access times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO
buffers data from port A to port B. The FIFO has flags to indicate empty and full
conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty
(AE), to indicate when a selected number of words is stored in memory. FIFO
data on port B can be output in 36-bit, 18-bit, and 9-bit formats with a choice of
big- or Little-Endian configurations. Three modes of byte-order swapping are
possible with any bus-size selection. Communication between each port can
bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored. Parity is checked passively
FUNCTIONAL BLOCK DIAGRAM
Mail 2
Register
Mail 1
Register
Input
Register
Output
Register
64 x 36
Write
Pointer Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Device
Control
RST
PEFA
MBF2
Port-B
Control
Logic
MBF1
EF
AE
36
B
0
- B
35
FF
AF
FS
0
FS
1
3145 drw01
Programmable
Flag Offset
Registers
A
0
- A
35
Parity
Gen/Check
Parity
Generation
FIFO
ODD/
EVEN
PGA
Parity
Gen/Check
PGB
PEFB
36
RAM ARRAY
64 x 36
Bus-Matching and
Byte Swapping
Output
Register
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
Port-B
Control
Logic
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
DESCRIPTION (CONTINUED)
PIN CONFIGURATIONS
another and can be asynchronous or coincident. The enables for each port are
arranged to provide a simple interface between microprocessors and/or buses
with synchronous interfaces.
The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage
synchronized to the port clock (CLKA) that writes data into its array. The Empty
Flag (EF) and Almost-Empty (AE) flag of the FIFO are two-stage synchronized
to the port clock (CLKB) that reads data from its array.
The IDT723613 is characterized for operation from 0°C to 70°C.
on each port and may be ignored if not desired. Parity generation can be
selected for data read from each port. Two or more devices may be used in
parallel to create wider data paths.
The IDT723613 is a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a continuous (free-running) port clock by
enable signals. The continuous clocks for each port are independent of one
NOTE:
1. NC = No internal connection.
TQFP (PN120-1, ORDER CODE: PF)
TOP VIEW
3145 drw02
A
23
A
22
A
21
GND
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
GND
A
9
A
8
A
7
V
CC
A
6
A
5
A
4
A
3
GND
A
2
A
1
A
0
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
22
B
21
GND
B
20
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
B
9
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
B
2
B
1
B
0
EF
AE
NC
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AF
FF
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
MBF2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
BE
SW1
SW0
SIZ1
MBF1
SIZ0
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60 91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92 B
23
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
34
A
35
B
35
GND
B
34
B
33
B
32
B
30
B
31
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
A
32
A
33
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
GND
AE
EF
B
0
B
1
B
2
GND
B
3
B
4
B
5
B
6
V
CC
B
7
B
8
B
9
GND
B
10
B
11
V
CC
B
12
B
13
B
14
GND
B
15
B
16
B
17
B
18
B
19
B
20
GND
B
21
B
22
B
23
GND
NC
NC
A
0
A
1
A
2
GND
A
3
A
4
A
5
A
6
V
CC
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
13
A
14
GND
A
15
A
16
A
17
A
18
A
19
A
20
GND
A
21
A
22
A
23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3145 drw03
117
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
V
CC
V
CC
A
24
A
25
A
26
A
27
GND
A
28
A
29
V
CC
A
30
A
31
A
32
GND
A
33
A
34
A
35
GND
B
35
B
34
B
33
GND
B
32
B
31
B
30
V
CC
B
29
B
28
B
27
GND
B
26
B
25
B
24
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83 NC
AF
FF
CSA
ENA
CLKA
W/RA
V
CC
PGA
FS
0
ODD/EVEN
FS
1
PEFA
MBF2
RST
BE
GND
SW1
SW0
SIZ1
MBF1
GND
PEFB
V
CC
W/RB
CLKB
ENB
CSB
NC
GND
MBA
SIZ0
PGB
*
NOTES:
1. NC = No internal connection.
2. Uses Yamaichi socket IC51-1324-828.
PQFP(2) (PQ132-1, ORDER CODE: PQF)
TOP VIEW
* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PIN CONFIGURATIONS (CONTINUED)
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Symbol Name I/O Description
A0-A35 Port A Data I/O 36-bit bidirectional data port for side A.
AE Almost-Empty Flag O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when Port B the number of 36-bit
Port B words in the FIFO is less than or equal to the value in the offset register, X.
AF Almost-Full Flag O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty location
Port A in the FIFO is less than or equal to the value in the offset register, X.
B0-B35 Port B Data I/O 36-bit bidirectional data port for side B
BE Big-Endian Select I Selects the bytes on port B used during byte or word FIFO reads. A LOW on BE selects the most significant
bytes on B0-B35 for use, and a HIGH selects the least significant bytes.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or
coincident to CLKA. Port-B byte swapping and data port sizing operations are also synchronous to the
LOW-to-HIGH transition of CLKB. EF and AE are synchronized to the LOW-to-HIGH transition of CLKB.
CSA Port A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The
A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EF Empty Flag O EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, the FIFO is empty, and
Port B reads from its memory are disabled. Data can be read from the FIFO to its output register when EF is
HIGH. EF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition
of CLKB after data is loaded into empty FIFO memory.
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FF Full Flag O FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW, the FIFO is full, and writes
Port A to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after reset.
FS1, FS0Flag Offset Selects I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which loads one of four preset
values into the Almost-Full flag and Almost-Empty flag offsets.
MBA Port A Mailbox Select I A high level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35
outputs are active, mail2 register data is output.
MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of
CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the
device is reset.
MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to
the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition
of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset.
ODD/ Odd/Even Parity Select I Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD
EVEN EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is
enabled for a read operation.
PEFA Port A Parity Error Flag O When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as A0-A8, A9-A17,
(Port A) A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35
inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore,
if a mail2 read with parity generation is set up by having CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH
and PGA HIGH, the PEFA flag is forced HIGH regardless of the state of the A0-A35 inputs.
PEFB Port B Parity Error Flag O When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as B0-B8,
(PortB) B9-B17, B18-B26, and B27-B35, with the most significant bit of each byte serving as the parity bit. A byte is
valid when it is used by the bus size selected for port B. The type of parity checked is determined by the
state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are shared by the mail1
register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity
generation is set up by having CSB LOW, ENB HIGH, W/RB LOW, SIZ1 and SIZ0 HIGH and PGB
HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs.
PIN DESCRIPTION
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Symbol Name I/O Description
PGA Port A Parity Generation I Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity
generated is selected by the state of the ODD/EVEN input. Bytes are organized at A0-A8, A9-A17,
A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte.
PGB Port B Parity I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and
B27-B35. The generated parity bits are output in the most significant bit of each byte.
RST Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF
flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select
Almost-Full flag and Almost-Empty flag offset.
SIZ0, Port B Bus Size Selects I A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following LOW-to
SIZ1 (Port B) HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be
long word, word, or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit
write or read.
SW0, Port B Byte Swap Selects I At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by
SW1 (Port B) SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte order
swapping is possible with any bus-size selection.
W/RA Port A Write/Read Select I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
Select transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
W/RB Port B Write/Read Select I A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
PIN DESCRIPTION (CONTINUED)
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
IDT723613
Commercial & Industrial(1)
TA = 15, 20 ns
Parameter Test Conditions Min. Typ.(2) Max. Unit
VOH VCC = 4.5V, IOH = –4 mA 2.4 — — V
VOL VCC = 4.5V, IOL = 8 mA — — 0.5 V
IIVCC = 5.5V, VI = VCC or 0 — — ±50 µA
IOZ VCC = 5.5V, VO = VCC or 0 — — ±50 µA
ICC(3) VCC = 5.5V, IO = 0 mA, VI = VCC or GND — — 1 mA
CiVI = 0 f = 1 MHz — 4 — pF
CoVO = 0, f = 1 MHz — 8 — pF
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
NOTES:
1. Industrial temperature range product for 20ns is available as a standard device. All other speed grades are available by special order.
2. All typical values are at VCC = 5V, TA = 25°C.
3. For additional ICC information, see the following page.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5. 5 V
VIH High-Level Input Voltage 2 — V
VIL Low-Level Input Voltage — 0.8 V
IOH High-Level Output Current — –4 mA
IOL Low-Level Output Current — 8 mA
TAOperating Free-Air Temperature 0 7 0 °C
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE
RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol Rating Commercial Unit
VCC Supply Voltage Range –0.5 to 7 V
VI(2) Input Voltage Range –0.5 to VCC+0.5 V
VO(2) Output Voltage Range –0.5 to VCC+0.5 V
IIK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA
IOK Output Clamp Current, (VO < 0 or VO > VCC) ±50 mA
IOUT Continuous Output Current, (VO = 0 to VCC) ±50 mA
ICC Continuous Current Through VCC or G N D ±500 mA
TSTG Storage Temperature Range –65 to 150 °C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
CALCULATING POWER DISSIPATION
The ICCf current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723613 with CLKA and CLKB set to
fS. All date inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to
normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with
the equation below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723613 may be calculated by:
PT = VCC x ICC(f) + Σ[CL x (VOH – VOL)2 x fo)
where: CL= output capacitive load
fo= switching frequency of an output
VOH = output high-level voltage
VOL = output high-level voltage
When no reads or writes are occurring on the IDT723613, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by: PT = VCC x fS x 0.29mA/MHz
010203040506070
0
50
100
150
200
250
300
350
400
f
S
Clock Frequency MHz
I
CC
(f)
S
upply Current mA
80
3145 drw04
f
data
= 1/2 f
S
T
A
= 25°C
C
L
= 0 pF
V
CC
= 5.5V
V
CC
= 5V
V
CC
= 4.5V
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
Commercial Com’l & Ind’l(1)
IDT723613L15 IDT723613L20
Symbol Parameter Min. Max. Min. Max. Unit
fSClock Frequency, CLKA or CLKB – 66.7 – 50 MHz
tCLK Clock Cycle Time, CLKA or CLKB 15 – 20 – ns
tCLKH Pulse Duration, CLKA and CLKB HIGH 6 – 8 – ns
tCLKL Pulse Duration, CLKA and CLKB LOW 6 – 8 – ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑4– 5–ns
tENS Setup Time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB,W/RB, and ENB before 5 – 5 – ns
CLKB↑
tSZS Setup Time, SIZ0, SIZ1,and BE before CLKB↑4– 5–ns
tSWS Setup Time, SW0 and SW1 before CLKB↑5– 7–ns
tPGS Setup Time, ODD/EVEN and PGB before CLKB↑(2) 4– 5–ns
tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑(3) 5– 6–ns
tFSS Setup Time, FS0 and FS1 before RST HIGH 5 – 6 – ns
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑1– 1–ns
tENH Hold Time, CSA W/RA, ENA and MBA after CLKA↑; CSB, W/RB, and ENB after CLKB↑1– 1–ns
tSZH Hold Time, SIZ0, SIZ1, and BE after CLKB↑2– 2–ns
tSWH Hold Time, SW0 and SW1 after CLKB↑0– 0–ns
tPGH Hold Time, ODD/EVEN and PGB after CLKB↑(2) 0– 0–ns
tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑(3) 5– 6–ns
tFSH Hold Time, FS0 and FS1 after RST HIGH 4 – 4 – ns
tSKEW1(4) Skew Time, between CLKA↑ and CLKB↑ for EF and FF 8– 8–ns
tSKEW2(4) Skew Time, between CLKA↑ and CLKB↑ for AE and AF 14 – 16 – ns
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a clock edge that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
Commercial Com’l & Ind’l(1)
IDT723613L15 IDT723613L20
Symbol Parameter Min. Max. Min. Max. Unit
tAAccess Time, CLKA↑ to A0-A35 and CLKB↑to B0-B35 210 2 12ns
tWFF Propagation Delay Time, CLKA↑ to FF 210 2 12ns
tREF Propagation Delay Time, CLKB↑ to EF 210 2 12ns
tPAE Propagation Delay Time, CLKB↑ to AE 210 2 12ns
tPAF Propagation Delay Time, CLKA ↑ to AF 210 2 12ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to MBF2 19 112ns
LOW or MBF1 HIGH
tPMR Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3) 311 3 12ns
tPPE(4) Propagation delay time, CLKB↑ to PEFB 211 2 12ns
tMDV Propagation Delay Time, SIZ1, SIZ0 to B0-B35 valid 1 11 1 11.5 ns
tPDPE Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 3 10 3 11 n s
tPOPE Propagation Delay Time, ODD/EVEN to PEFA and PEFB 311 3 12ns
tPOPB(5) Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35)2 12 2 13 ns
tPEPE Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, 1 11 1 12 ns
SIZ1, SIZ0, or PGB to PEFB
tPEPB(5) Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, A26, A35); 3 12 3 13 ns
CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35)
tRSF Propagation Delay Time, RST to AE, EF LOW and AF, MBF1, MBF2 HIGH 1 15 1 20 ns
tEN Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH to 2 10 2 12 ns
B0-B35 active
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH or W/RB1 8 1 9ns
LOW to B0-B35 at high impedance
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1 and SIZ0 are HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active.
4. Only applies when a new port-B bus size is implemented by the rising CLKB edge.
5. Only applies when reading data from a mail register.
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
FUNCTIONAL DESCRIPTION
RESET (RST)
The IDT723613 is reset by taking the Reset (RST) input LOW for at least
four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH
transitions. The Reset input can switch asynchronously to the clocks. A
device reset initializes the internal read and write pointers of the FIFO and
forces the Full Flag (FF) LOW, the Empty Flag (EF) LOW, the Almost-Empty
flag (AE) LOW, and the Almost-Full flag (AF) HIGH. A reset also forces the
Mailbox Flags (MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two
LOW-to-HIGH transitions of CLKA. The device must be reset after power
up before data is written to its memory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Empty Offset register (X) with the value selected by the Flag Select
(FS0, FS1) inputs. The values that can be loaded into the register are shown
in Table 1.
FIFO WRITE/READ OPERATION
The state of the port A data (A0-A35) outputs is controlled by the port-A
Chip Select (CSA) and the port-A Write/Read select (W/RA). The A 0-A35
outputs are in the high-impedance state when either CSA or W/RA is HIGH. The
A0-A35 outputs are active when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and FFA is HIGH (see Table 2).
The state of the port B data (B0-B35) outputs is controlled by the port B Chip
Select (CSB) and the port B Write/Read select (W/RB). The B0-B35 outputs are
in the high-impedance state when either CSB or W/RB is HIGH. The B0-B35
outputs are active when both CSB and W/RB are LOW. Data is read from the
CSA W/RA ENA MBA CLKA A0-A35 Outputs Port Function
H X X X X In high-impedance state None
L H L X X In high-impedance state None
LHHL↑In high-impedance state FIFO write
LHHH↑In high impedance state Mail1 write
L L L L X Active, mail2 register None
LLHL↑Active, mail2 register None
L L L H X Active, mail2 register None
LLHH↑Active, mail2 register Mail2 read (set MBF2 HIGH)
TABLE 2 PORT A ENABLE FUNCTION TABLE
Almost-Full and
FS1 FS0 RST Almost-Empty Flag
Offset Register (X)
HH↑16
HL↑12
LH↑8
LL↑4
TABLE 1 FLAG PROGRAMMING
FIFO to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB
is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1
is LOW (see Table 3).
The setup and hold-time constraints to the port clocks for the port Chip Selects
(CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write
and read operations and are not related to high-impedance control of the data
outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and
Write/Read select can change states during the setup and hold time window of
the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO flag is synchronized to its port clock through two flip-flop stages.
This is done to improve the flags’ reliability by reducing the probability of
metastable events on their outputs when CLKA and CLKB operate asyn-
chronously to one another. FF and AF are synchronized to CLKA. EF and
AE are synchronized to CLKB. Table 4 shows the relationship of each port
flag to the level of FIFO fill.
EMPTY FLAG (EF)
The FIFO Empty Flag is synchronized to the port clock that reads data
from its array (CLKB). When the EF is HIGH, new data can be read to the
FIFO output register. When the EF is LOW, the FIFO is empty and
attempted FIFO reads are ignored. When reading the FIFO with a byte or
word size on port B, EF is set LOW when the fourth byte or second word of
the last long word is read.
The FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls the EF monitors a
write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is empty, empty+1, or empty+2. A word written to the FIFO
can be read to the FIFO output register in a minimum of three port B clock
(CLKB) cycles. Therefore, an EF is LOW if a word in memory is the next data
to be sent to the FIFO output register and two CLKB cycles have not elapsed
since the time the word was written. The EF of the FIFO is set HIGH by the
second LOW-to-HIGH transition of CLKB, and the new data word can be
read to the FIFO output register in the following cycle.
A LOW-to-HIGH transition on CLKB begins the first synchronization cycle
of a write if the clock transition occurs at time tSKEW1 or greater after the write.
Otherwise, the subsequent CLKB cycle can be the first synchronization
cycle (see Figure 10).
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Number of 36-Bit Synchronized Synchronized
Words in the FIFO(1) to CLKB to CLKA
EF AE AF F F
0LLHH
1 to X H L H H
(X + 1) to [64 – (X + 1)] H H H H
(64 – X) to 63 H H L H
64 H H L L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.
TABLE 3 PORT B ENABLE FUNCTION TABLE
CSB W/RB ENB SIZ1, SIZ0 CLKB B0-B35 Outputs Port Function
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H One, both LOW ↑In high-impedance state None
L H H Both HIGH ↑In high-impedance state Mail2 write
L L L One, both LOW X Active, FIFO output register None
L L H One, both LOW ↑Active, FIFO output register FIFO read
L L L Both HIGH X Active, mail1 register None
L L H Both HIGH ↑Active mail1 register Mail1 read (set MBF1 HIGH)
TABLE 4 FIFO FLAG OPERATION
FULL FLAG (FF)
The FIFO Full Flag is synchronized to the port clock that writes data to its array
(CLKA). When the FF is HIGH, a SRAM location is free to receive new data.
No memory locations are free when the FF is LOW and attempted writes to the
FIFO are ignored.
Each time a word is written to the FIFO, its write-pointer is incremented.
The state machine that controls the FF monitors a write-pointer and read-
pointer comparator that indicates when the FIFO SRAM status is full, full-1,
or full-2. From the time a word is read from the FIFO, its previous memory
location is ready to be written in a minimum of three CLKA cycles. Therefore,
a FF is LOW if less than two CLKA cycles have elapsed since the next
memory write location has been read. The second LOW-to-HIGH transition
on the FF synchronizing clock after the read sets the FF HIGH and data can
be written in the following clock cycle.
A LOW-to-HIGH transition on CLKA begins the first synchronization cycle
of a read if the clock transition occurs at time tSKEW1 or greater after the read.
Otherwise, the subsequent clock cycle can be the first synchronization cycle
(see Figure 11).
ALMOST-EMPTY FLAG (AE)
The FIFO Almost-Empty flag is synchronized to the port clock that reads
data from its array (CLKB). The state machine that controls the AE flag
monitors a write-pointer and read-pointer comparator that indicates when
the FIFO SRAM status is almost-empty, almost-empty+1, or almost-empty+2.
The almost-empty state is defined by the value of the Almost-Full and
Almost-Empty Offset register (X). This register is loaded with one of four
preset values during a device reset (see reset above). The AE flag is LOW
when the FIFO contains X or less long words in memory and is HIGH when
the FIFO contains (X+1) or more long words.
Two LOW-to-HIGH transitions on the port B Clock (CLKB) are required after
a FIFO write for the AE flag to reflect the new level of fill. Therefore, the AE flag
of a FIFO containing (X+1) or more long words remains LOW if two CLKB cycles
have not elapsed since the write that filled the memory to the (X+1) level. The
AE flag is set HIGH by the second CLKB LOW-to-HIGH transition after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH transition of CLKB
begins the first synchronization cycle if it occurs at time tSKEW2 or greater after
the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent CLKB
cycle can be the first synchronization cycle (see Figure 12).
ALMOST FULL FLAG (AF)
The FIFO Almost-Full flag is synchronized to the port clock that writes data
to its array (CLKA). The state machine that controls an AF flag monitors a
write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is almost -full, almost- full-1, or almost-full-2. The almost-full
state is defined by the value of the Almost-Full and Almost-Empty Offset
register (X). This register is loaded with one of four preset values during a
device reset (see reset above). The AF flag is LOW when the FIFO contains
(64-X) or more long words in memory and is HIGH when the FIFO contains
[64-(X+1)] or less long words.
Two LOW-to-HIGH transitions on the port A Clock (CLKA) are required
after a FIFO read for the AF flag to reflect the new level of fill. Therefore, the
AF flag of a FIFO containing [64-(X+1)] or less words remains LOW if two
CLKA cycles have not elapsed since the read that reduced the number of
long words in memory to [64-(X+1)]. The AF flag is set HIGH by the second
CLKA LOW-to-HIGH transition after the FIFO read that reduces the number
of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA
begins the first synchronization cycle if it occurs at time tSKEW2 or greater after
the read that reduces the number of long words in memory to [64-(X+1)].
Otherwise, the subsequent CLKA cycle can be the first synchronization
cycle (see Figure 13).
MAILBOX REGISTERS
Two 36-bit bypass registers (mail1, mail2) are on the IDT723613 to pass
command and control information between port A and port B without putting
it in queue. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the
mail1 register when a port A write is selected by CSA, W/RA, and ENA (with
MBA HIGH). A LOW-to-HIGH transition on CLKB writes B0-B35 data to the
mail2 register when a port B write is selected by CSB, W/RB, and ENB (and
both SIZ0 and SIZ1 are HIGH). Writing data to a mail register sets its
corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail
register are ignored while its mail flag is LOW.
When the port B data (B0-B35) outputs are active, the data on the bus comes
from the FIFO output register when either one or both SIZ1 and SIZ0 are LOW
and from the mail1 register when both SIZ1 and SIZ0 are HIGH. The Mail1
Register Flag (MBF1) is set HIGH by a rising CLKB edge when a port B read
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
is selected by CSB, W/RB, and ENB, (and both SIZ1 and SIZ0 HIGH). The
Mail2 Register Flag (MBF2) is set HIGH by a rising CLKA edge when a port
A read is selected by CSA, W/RA, and ENA (with MBA HIGH). The data in a
mail register remains intact after it is read and changes only when new data is
written to the register.
DYNAMIC BUS SIZING
The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-
bit byte format for data read from the FIFO. Word- and byte-size bus
selections can utilize the most significant bytes of the bus (Big-Endian) or
least significant bytes of the bus (Little-Endian). Port B bus-size can be
changed dynamically and synchronous to CLKB to communicate with
peripherals of various bus widths.
The levels applied to the port B bus-size select (SIZ0, SIZ1) inputs and the
Big-Endian select (BE) input are stored on each CLKB LOW-to-HIGH
transition. The stored port B bus-size selection is implemented by the next
rising edge on CLKB according to Figure 2.
Only 36-bit long-word data is written to or read from the FIFO memory on
the IDT723613. Bus-matching operations are done after data is read from
the FIFO RAM. Port B bus sizing does not apply to mail register operations.
BUS-MATCHING FIFO READS
Data is read from the FIFO RAM in 36-bit long-word increments. If a long-
word bus-size is implemented, the entire long word immediately shifts to the
FIFO output register upon a read. If byte or word size is implemented on port
B, only the first one or two bytes appear on the selected portion of the FIFO
output register, with the rest of the long word stored in auxiliary registers. In
this case, subsequent FIFO reads with the same bus-size implementation
output the rest of the long word to the FIFO output register in the order
shown by Figure 2.
Each FIFO read with a new bus-size implementation automatically un-
loads data from the FIFO RAM to its output register and auxiliary registers.
Therefore, implementing a new port B bus-size and performing a FIFO read
before all bytes or words stored in the auxiliary registers have been read
results in a loss of the unread data in these registers.
When reading data from FIFO in byte or word format, the unused B0-B35
outputs remain inactive but static, with the unused FIFO output register bits
holding the last data value to decrease power consumption.
BYTE SWAPPING
The byte-order arrangement of data read from the FIFO can be changed
synchronous to the rising edge of CLKB. Byte-order swapping is not
available for mail register data. Four modes of byte-order swapping (includ-
ing no swap) can be done with any data port size selection. The order of the
bytes are rearranged within the long word, but the bit order within the bytes
remains constant.
Byte arrangement is chosen by the port B Swap select (SW0, SW1) inputs
on a CLKB rising edge that reads a new long word from the FIFO. The byte
order chosen on the first byte or first word of a new long word read from the
FIFO is maintained until the entire long word is transferred, regardless of the
SW0 and SW1 states during subsequent reads. Figure 4 is an example of
the byte-order swapping available for long word reads. Performing a byte
swap and bus-size simultaneously for a FIFO read first rearranges the bytes
as shown in Figure 4, then outputs the bytes as shown in Figure 2.
PORT-B MAIL REGISTER ACCESS
In addition to selecting port B bus sizes for FIFO reads, the port B bus Size
select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and
SIZ1 are HIGH, the mail1 register is accessed for a port B long-word read and
the mail2 register is accessed for a port B long-word write. The mail register is
accessed immediately and any bus-sizing operation that can be underway is
unaffected by the mail register access. After the mail register access is complete,
the previous FIFO access can resume in the next CLKB cycle. The logic diagram
in Figure 3 shows the previous bus-size selection is preserved when the mail
registers are accessed from port B. A port B bus-size is implemented on each
rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and BE_Q.
PARITY CHECKING
The port A data inputs (A0-A35) and port B data inputs (B0-B35) each have
four parity trees to check the parity of incoming (or outgoing) data. A parity
failure on one or more bytes of the port A data bus is reported by a low level
on the port A Parity Error Flag (PEFA). A parity failure on one or more bytes
of the port B data inputs that are valid for the bus-size implementation is
reported by a low level on the port B Parity Error Flag (PEFB). Odd or Even
parity checking can be selected, and the Parity Error Flags can be ignored
if this feature is not desired.
Parity status is checked on each input bus according to the level of the
Odd/Even parity (ODD/EVEN) select input. A parity error on one or more
valid bytes of a port is reported by a LOW level on the corresponding port
Parity Error Flag (PEFA, PEFB) output. Port A bytes are arranged as A0-A8,
A9-A17, A18-A26, and A27-A35, and port B bytes are arranged as B0-B8, B9-
B17, B18-B26, and B27-B35, and its valid bytes are those used in a port B bus
size implementation. When Odd/Even parity is selected, a port Parity Error
Flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even number
of LOW levels applied to its bits.
The four parity trees used to check the A0-A35 inputs are shared by the
mail2 register when parity generation is selected for port-A reads (PGA = HIGH).
When a port A read from the mail2 register with parity generation is selected with
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A
Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the
A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are
shared by the mail1 register when parity generation is selected for port B reads
(PGB = HIGH). When a port B read from the mail1 register with parity generation
is selected with CSB LOW, ENB HIGH, W/RB LOW, both SIZ0 and SIZ1 HIGH,
and PGB HIGH, the port B Parity Error Flag (PEFB) is held HIGH regardless
of the levels applied to the B0-B35 inputs.
PARITY GENERATION
A HIGH level on the port A Parity Generate select (PGA) or port B Parity
Generate select (PGB) enables the IDT723613 to generate parity bits for
port reads from a FIFO or mailbox register. Port A bytes are arranged as A0-
A8, A9-A17, A18-A26, and A 27-A35, with the most significant bit of each byte
used as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26,
and B27-B35, with the most significant bit of each byte used as the parity bit.
A write to a FIFO or mail register stores the levels applied to all nine inputs
of a byte regardless of the state of the Parity Generate select (PGA, PGB)
inputs. When data is read from a port with parity generation selected, the
lower eight bits of each byte are used to generate a parity bit according to the
level on the ODD/EVEN select. The generated parity bits are substituted for
the levels originally written to the most significant bits of each byte as the word
is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM
and before the data is written to the output register. Therefore, the port A Parity
Generate select (PGA) and Odd/Even parity select (ODD/EVEN) have setup
and hold time constraints to the port A Clock (CLKA) and the port B Parity
Generate select (PGB) and ODD/EVEN select have setup and hold time
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Figure 2. Dynamic Bus Sizing
A
B
B8B0
1st: Read from FIFO
2nd: Read from FIFO
C
D
B8B0
3rd: Read from FIFO
4th: Read from FIFO
BE SIZ1 SIZ0 B8B0
B8B0
3145 fig01
B35B27 B26B18 B17B9
B35B27 B26B18 B17B9
B35B27 B26B18 B17B9
B35B27 B26B18 B17B9
A8A0
B8B0
A
A
A
C
B
B
B
D
C
C
C
A
D
D
D
B
B8B0
B8B0
B8B0
(a) LONG WORD SIZE
(b) WORD SIZE BIG-ENDIAN
(c) WORD SIZE LITTLE-ENDIAN
Write to FIFO
Read from FIFO
1st: Read from FIFO
2nd: Read from FIFO
1st: Read from FIFO
2nd: Read from FIFO
BE SIZ1 SIZ0
BE
BE SIZ1 SIZ0
BYTE ORDER ON PORT A:
B8B0
A35A27 A26A18 A17A9
B35 B27 B26 B18 B17B9
B35B27 B26B18 B17B9
B35B27 B26B18 B17B9
B35B27 B26B18 B17B9
B35B27 B26B18 B17B9
A
B
B8B0
(d) BYTE SIZE LITTLE-ENDIAN
1st: Read from FIFO
2nd: Read from FIFO
C
D
B8B0
3rd: Read from FIFO
4th: Read from FIFO
B8B0
A8A0
B35B27 B26B18 B17B9
B35B27 B26B18 B17B9
A35A27 A26A18 A17A9
B35B27 B26B18 B17B9
(d) BYTE SIZE BIG-ENDIAN
SIZ1 SIZ0
LL H
XL L
HLH
LHL
BE SIZ1 SIZ0
HH L
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Figure 3. Logic Diagram for SIZ0, SIZ1, and BE Register
MUX
G1
1
1
D Q SIZ0 Q
SIZ1 Q
BE Q
•
SIZ0
SIZ1
BE
CLKB
3145 fig02
••
••
constraints to the port B Clock (CLKB). These timing constraints only apply
for a rising clock edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port B
bus (B0-B35) to check parity and the circuit used to generate parity for the mail2
data is shared by the port A bus (A0-A35) to check parity. The shared parity
trees of a port are used to generate parity bits for the data in a mail register when
the port Chip Select (CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH, and
Write/Read select (W/RA, W/RB) input is LOW, the mail register is selected (MBA
HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity
Generate select (PGA, PGB) is HIGH. Generating parity for mail register data
does not change the contents of the register.
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Figure 4. Byte Swapping for FIFO Reads (Long-Word Size Example)
A8A0
A
A
A
D
A
C
A
B
B
B
C
B
D
B
C
C
C
B
C
A
C
D
D
D
A
D
B
D
A8A0
A8A0
B8B0
(a) NO SWAP
(b) BYTE SWAP
(c) WORD SWAP
L L
SW1 SW0
SW1 SW0
SW1 SW0
SW1 SW0
L L
L H
H L
H H
(d) BYTE-WORD SWAP 3145 fig03
A35A27 A26A18 A17A9
B35B27 B26B18 B17B9 B8B0
A35A27 A26A18 A17A9
B35B27 B26B18 B17B9 B8B0
A35A27 A26A18 A17A9
B35B27 B26B18 B17B9
A35A27 A26A18 A17A9 A8A0
BADC
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
CLKA
RST
FF
AE
AF
MBF1,
MBF2
CLKB
EF
FS1,FS0
3145 drw05
t
RSTS
t
RSTH
t
FSH
t
FSS
0,1
t
WFF
t
REF
t
RSF
t
WFF
t
PAE
t
PAF
Figure 5. Device Reset Loading the X Register with the Value of Eight
Figure 6. FIFO Write Cycle Timing
CLKA
FFA
ENA
MBA
CSA
W/RA
PEFA
A0 - A35
ODD/
EVEN
t
ENH
t
ENH
t
ENH
t
ENH
t
ENH
t
ENH
3145 drw06
t
DH
W1 W2 No Operation
Valid
Valid
t
PDPE
t
PDPE
HIGH
(1) (1)
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENS
t
ENS
t
ENS
t
DS
t
ENS
t
ENS
NOTE:
1. Written to the FIFO.
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
FIFO Data Write Swap Mode FIFO Data Read
A35-A27 A26-A18 A17-A9A8-A0SW1 SW0 B35-B27 B26-B18 B17-B9B8-B0
ABCD LL ABCD
ABCD LH DCBA
ABCD HL CDAB
ABCD HH BADC
CLKB
ENB
SW1,
SW0
EF
W/RB
PGB,
BE
ODD/
EVEN
HIGH
3145 drw07
CSB
SIZ1,
SIZ0 NOT (1,1)
(1)
t
PGH
t
PGS
t
SZH
t
SZH
t
ENH
(0,0)
t
SWS
B0-B35
NOT (1,1)
(1)
Previous Data W1
(2)
t
DIS
t
ENS
t
ENH
t
SWH
t
ENS
No Operation
(0,0)
t
EN
t
A
t
A
W2
(2)
t
SZS
t
SZS
NOTES:
1 . SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Data read from FIFO1.
DATA SWAP TABLE FOR FIFO LONG-WORD READS
Figure 7. FIFO Long-Word Read Cycle Timing
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
FIFO Data Write Swap Mode Read
No. Big-Endian Little-Endian
A35-A27 A26-A18 A17-A9A8-A0SW1 SW0 B35-B27 B26-B18 B17-B9B8-B0
1A B CD
ABCDLL2CDAB
1D C BA
ABCDLH2BADC
1C D AB
ABCDHL2ABCD
1B A DC
ABCDHH2DCBA
CLKB
ENB
SW1,
SW0
EF
W/RB
PGB,
BE
ODD/
EVEN
HIGH
3145 drw08
CSB
SIZ1,
SIZ0 NOT (1,1)(1)
t
PGH
t
PGS
t
SZH
t
SZH
(0,1)
t
SWS
B0-B17
NOT (1,1)(1)
Previous Data
t
ENS
t
ENH
t
SWH
No Operation
Previous DataB18-B35
Little
Endian
Big
Endian
Read 1
Read 1
Read 2
Read 2
(0,1)
(2)
(2)
t
SZS
t
SZS
t
EN
t
A
t
A
t
A
t
A
t
DIS
t
DIS
NOTES:
1 . SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused word B0-B17 or B18-B35 holds last FIFO1 output register data for word-size reads.
FIFO Data Read
DATA SWAP TABLE FOR FIFO WORD READS
Figure 8. FIFO Word Read-Cycle Timing
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
FIFO Data Read
FIFO Data Write Swap Mode Read Big- Little-
No. Endian Endian
A35-A27 A26-A18 A17-A9A8-A0SW1 SW0 B35-B27 B8-B0
1A D
2B C
AB CDLL3CB
4D A
1D A
2C B
AB CDLH3BC
4A D
1C B
2D A
AB CDHL3AD
4B C
1B C
2A D
AB CDHH3DA
4C B
EF
CSB
W/RB
SIZ1,
SIZ0
ENB
CLKB
3145 drw09
HIGH
SW1,
SW0
BE
PGB,
ODD/
EVEN
B0-B8
B27-B35 Read 4Read 1 Read 2
Read 4
Read 1 Read 3
Read 3Previous Data
Previous Data Read 2
(1,0) (1,0) (1,0) Not (1,1)
(1)
No Operation
t
DIS
t
DIS
t
EN
t
PGH
t
PGS Not (1,1)
(1)
Not (1,1)
(1)
Not (1,1)(1)
(1,0)
t
ENS
t
ENH
t
SWS
t
SWH
t
SZH
t
SZH
t
SZS
t
SZS
t
A
t
A
t
A
t
A
t
A
t
A
t
A
t
A
NOTES:
1 . SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused bytes hold last FIFO output register data for byte-size reads.
DATA SWAP TABLE FOR FIFO BYTE READS
Figure 9. FIFO Byte Read-Cycle Timing
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
CSA
WRA
MBA
FF
A0 - A35
CLKB
EF
CSB
W/RB
SIZ1,
SIZ0
ENA
ENB
B0 -B35
CLKA
12
3145 drw10
t
ENS
t
ENS
t
ENH
t
ENH
t
DS
t
DH
t
ENS
t
ENH
W1
FIFO Empty
LOW
HIGH
LOW
LOW
LOW
W1
HIGH
t
CLK
t
CLKH
t
CLKL
t
SKEW1(1)
t
CLKH
t
CLK
t
CLKL
t
REF
t
REF
t
A
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA
edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EF is set LOW by the last word or byte read from the
FIFO, respectively.
Figure 10.
EF
Flag Timing and First Data Read when the FIFO is Empty
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
CSB
EF
W/RB
SIZ1,
SIZ0
ENB
B0 -B35
CLKB
FF
CLKA
CSA
WRA
A0 - A35
MBA
ENA
3145 drw11
12
t
ENS
t
ENH
t
ENS
t
ENS
t
DS
t
ENH
t
ENH
t
DH
To FIFO
Previous Word in FIFO Output Register Next Word From FIFO
LOW
LOW
LOW
HIGH
LOW
HIGH
FIFO Full
t
CLK
t
CLKH
t
CLKL
t
A
t
SKEW1(1)
t
CLKH
t
CLKL
t
CLK
t
WFF
t
WFF
Figure 11.
FF
Flag Timing and First Available Write when the FIFO is Full
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKA cycle later than shown.
2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads
the last word or byte of the long word, respectively.
AE
CLKA
ENA
CLKB
ENB
3145 drw12
2
1
t
ENS
t
ENH
t
ENS
t
ENH
X Long Words in FIFO (X+1) Long Words in FIFO
t
SKEW2(1)
t
PAE
t
PAE
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2 . FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, MBB = LOW).
3. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced to the last word or byte of the long
word, respectively.
Figure 12. Timing for
AE
when the FIFO is Almost-Empty
22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
4661 drw14
CLKA
ENA
A0 - A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
SIZ1, SIZ0
ENB
B0 - B35
W/RB
W1
t
ENS
t
ENH
t
DH
t
EN
t
ENH
W1 (Remains valid in Mail1 Register after read)
FIFO Output Register
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
DS
t
PMF
t
PMF
t
ENS
t
PMR
t
MDV
t
DIS
NOTE:
1. Port-B parity generation off (PGB = LOW).
Figure 14. Timing for Mail1 Register and
MBF1
Flag
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
2 . FIFO write (CSA = L0W, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, MBB = LOW).
3. Port-B size of long word is selected for FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of the
long word, respectively.
Figure 13. Timing for
AF
when the FIFO is Almost Full
AF
CLKA
ENA
CLKB
ENB
3145 drw13
12
t
ENS
t
ENH
t
ENS
t
ENH
[64-(X+1)] Long Words in FIFO (64-X) Long Words in FIFO
t
SKEW2(1)
t
PAF
t
PAF
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
3145 drw15
CLKB
ENB
B0 - B35
SIZ1,
SIZ0
CSB
W/RB
CLKA
MBF2
CSA
MBA
ENA
A0 - A35
W/RA
W1
t
ENS
t
ENH
t
DH
t
ENH
t
EN
W1 (Remains valid in Mail2 Register after read)
t
SZS
t
SZH
t
ENS
t
ENH
t
ENS
t
ENH
t
DS
t
PMF
t
PMF
t
ENS
t
PMR
t
DIS
NOTE:
1. Port-A parity generation off (PGA = LOW). Figure 15. Timing for Mail2 Register and
MBF2
Flag
ODD/
EVEN
PEFA
PGA
MBA
W/RA
3145 drw16
Valid Valid Valid Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
NOTE:
1. CSA = LOW and ENA = HIGH. Figure 16. ODD/
EVEN
, W/
R
A, MBA, and PGA to
PEFA
Timing
Figure 17. ODD/
EVEN
, W/
R
B
,
SIZ1, SIZ0, and PGB to
PEFB
Timing
ODD/
EVEN
PEFB
PGB
SIZ1,
SIZ0
W/RB
3145 drw17
Valid Valid Valid Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
NOTE:
1. CSB = LOW and ENB = HIGH.
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Figure 19. Parity Generation Timing when Reading from the Mail1 Register
ODD/
EVEN
A8, A17,
A26, A35
PGA
MBA
W/RA
CSA
3145 drw18
Mail2 Data Generated Parity Generated Parity Mail2 Data
LOW
t
EN
t
PEPB
t
POPB
t
PEPB
NOTE:
1 . ENA = HIGH. Figure 18. Parity Generation Timing when Reading from the Mail2 Register
ODD/
EVEN
B8, B17,
B26, B35
PGB
SIZ1,
SIZ0
W/RB
CSB
3145 drw19
Mail1
Data
Generated Parity Generated Parity Mail1 Data
LOW
t
EN
t
MDV
t
PEPB
t
POPB
t
PEPB
NOTE:
1 . ENB = HIGH.
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
PARAMETER MEASUREMENT INFORMATION
3145 drw20
From Output
Under Test
30 pF
1.1kΩ
5V
680Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3 V
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
3 V
1.5 V 1.5 V
1.5 V
1.5 V
≈
OH
OV
GND
OH
OL
1.5 V 1.5 V
1.5 V 1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
tPLZ
tPHZ
tPZL
tPZH
(1)
tSthtW
tPD tPD
≈
Figure 20. Load Circuit and Voltage Waveforms
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 e-mail: FIFOhelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674
www.idt.com
26
ORDERING INFORMATION
723613
3145 drw21
64 x 36 SyncFIFO
XXXXXXIDT Device Type XXX X X
Power Speed Package
Clock Cycle Time (t
CLK
)
Speed in NanosecondsCom’l & Ind’l
Process/
Temperature
Range
BLANK
I
(1)
PF
PQF
15
20
L
Commercial (0°C to +70°C)
Industrial (40°C to +85°C)
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Commercial Only
Low Power
NOTE:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
DATASHEET DOCUMENT HISTORY
03/05/2002 pgs. 1, 6, 8, 9, 24 and 26.
