September 2013Doc ID 10879 Rev 31/28
1
VND830SP-E
Double channel high-side driver
Features
■ECOPACK®: lead free and RoHS compliant
■Automotive Grade: compliance with AEC
guidelines
■Very low standby current
■CMOS compatible input
■On-state open-load detection
■Off-state open-load detection
■Thermal shutdown protection and diagnosis
■Undervoltage shutdown
■Overvoltage clamp
■Output stuck to VCC detection
■Load current limitation
■Reverse battery protection
■Electrostatic discharge protection
Description
The VND830SP-E is a monolithic device made by
using STMicroelectronics™ VIPower™ M0-3
technology, intended for driving any kind of load
with one side connected to ground.
Active VCC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table).
Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload. The device detects
open-load condition both is on-state and off-state.
Output shorted to VCC is detected in the off-state.
Device automatically turns-off in case of ground
pin disconnection.
Type RDS(on) IOUT VCC
VND830SP-E 60 mΩ(1)
1. Per each channel.
6A
(1) 36 V
1
10
PowerSO-10
Table 1. Device summary
Package
Order codes
Tube Tape and reel
PowerSO-10 VND830SP-E VND830SPTR-E
www.st.com
VND830SP-E Contents
Doc ID 10879 Rev 3 2/28
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 18
3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 18
3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 19
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 PowerSO-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 PowerSO-10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3 PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VND830SP-E List of tables
Doc ID 10879 Rev 3 3/28
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 8. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 9. Switching (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 11. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 13. Electrical transient requirements on VCC pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 14. Electrical transient requirements on VCC pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 15. Electrical transient requirements on VCC pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VND830SP-E List of figures
Doc ID 10879 Rev 3 4/28
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 16. Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 24. PowerSO-10 maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . 17
Figure 25. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 27. PowerSO-10 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 21
Figure 29. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10 . . . . . . . . . . . . . . . . . . . . 22
Figure 31. PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. PowerSO-10 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 33. PowerSO-10 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 34. PowerSO-10 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VND830SP-E Block diagram and pin description
Doc ID 10879 Rev 3 5/28
1 Block diagram and pin description
Figure 1. Block diagram
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Status N.C. Output Input
Floating X X X X
To ground — X — Through 10 KΩ
resistor
OVERTEMP. 1
Vcc
GND
INPUT1 OUTPUT1
OVERVOLTAGE
LOGIC
DRIVER 1
STATUS1
Vcc
CLAMP
UNDERVOLTAGE
CLAMP 1
OPEN-LOAD ON 1
CURRENT LIMITER 1
OPEN-LOAD OFF 1
OUTPUT2
DRIVER 2
CLAMP 2
OPEN-LOAD ON 2
OPEN-LOAD OFF 2
OVERTEMP. 2
INPUT2
STATUS2
CURRENT LIMITER 2
1
2
3
4
5
6
7
8
9
10
11
OUTPUT 1
OUTPUT 1
N.C.
OUTPUT 2
OUTPUT 2
GROUND
INPUT 1
STATUS 1
STATUS 2
INPUT 2
V
CC
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 6/28
2 Electrical specifications
2.1 Absolute maximum ratings
Stressing the device above the rating listed in Ta b l e 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
document.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
-VCC Reverse DC supply voltage -0.3 V
-IGND DC reverse ground pin current -200 mA
IOUT DC output current Internally limited A
-IOUT Reverse DC output current -6 A
IIN DC input current +/-10 mA
ISTAT DC status current +/-10 mA
VESD
Electrostatic discharge (Human Body Model: R = 1.5 KΩ;
C=100pF)
–INPUT
–STATUS
–OUTPUT
–V
CC
4000
4000
5000
5000
V
V
V
V
EMAX
Maximum switching energy
(L = 1.8 mH; RL=0Ω; Vbat =13.5V; T
jstart = 150 °C;
IL=9A)
100 mJ
Ptot Power dissipation TC=25°C 73.5 W
TjJunction operating temperature Internally limited °C
TcCase operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 7/28
2.2 Thermal data
2.3 Electrical characteristics
Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless
otherwise stated.
(Per each channel)
Figure 3. Current and voltage conventions
1. VFn = VCCn - VOUTn during reverse battery condition.
Table 4. Thermal data (per island)
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case 1.7 °C/W
Rthj-amb Thermal resistance junction-ambient 51.7(1) 37(2) °C/W
1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick). Horizontal mounting and
no artificial air flow.
2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 µm thick). Horizontal mounting and no
artificial air flow.
Table 5. Power output
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC(1) Operating supply voltage 5.5 13 36 V
VUSD(1) Undervoltage shutdown 3 4 5.5 V
VOV(1) Overvoltage shutdown 36 V
RON On-state resistance IOUT = 2 A; Tj = 25 °C 60 mΩ
IOUT = 2 A; VCC > 8 V 120 mΩ
I
S
I
GND
OUTPUT 2
V
CC
GND
STATUS 2
INPUT 2 I
OUT2
I
IN2
I
STAT2
V
STAT2
V
IN2
V
CC
V
OUT2
OUTPUT 1
I
OUT1
V
OUT1
INPUT 1
I
IN1
STATUS 1
I
STAT1
V
IN1
V
STAT1
V
F1 (1)
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 8/28
IS(1) Supply current
Off-state; VCC = 13 V;
VIN = VOUT = 0 V 12 40 µA
Off-state; VCC = 13 V;
VIN = VOUT = 0 V; Tj = 25°C 12 25 µA
On-state; VCC = 13 V 5 7 mA
IL(off1) Off-state output current VIN = VOUT = 0 V; VCC =36V;
Tj=125°C 050µA
IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V -75 0 µA
IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C 5µA
IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V;
Tj=25°C 3µA
1. Per device.
Table 6. Protections(1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature 135 °C
Thyst Thermal hysteresis 7 15 °C
tSDL
Status delay in overload
conditions Tj > TTSD 20 µs
Ilim Current limitation VCC = 13 V 6 9 15 A
5.5 V < VCC < 36 V 15 A
Vdemag
Turn-off output clamp
voltage IOUT = 2 A; L = 6 mH VCC -41 V
CC -48 V
CC -55 V
Table 7. VCC - output diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
VFForward on voltage -IOUT =1.3A; T
j=150°C — — 0.6 V
Table 8. Status pin
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSTAT Status low output voltage ISTAT = 1.6 mA 0.5 V
ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 µA
CSTAT Status pin input capacitance Normal operation; VSTAT = 5 V 100 pF
Table 5. Power output (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 9/28
VSCL Status clamp voltage ISTAT = 1 mA 6 6.8 8 V
ISTAT = -1 mA -0.7 V
Table 9. Switching (VCC = 13 V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time RL = 6.5 Ω from VIN rising
edge to VOUT = 1.3 V —30—µs
td(off) Turn-off delay time RL = 6.5 Ω from VIN falling
edge to VOUT = 11.7 V —30—µs
dVOUT/dt(on) Turn-on voltage slope RL = 6.5 Ω from VOUT = 1.3 V
to VOUT = 10.4 V —See
Figure 21 —V/µs
dVOUT/dt(off) Turn-off voltage slope RL = 6.5 Ω from VOUT = 11.7 V
to VOUT = 1.3 V —See
Figure 22 —V/µs
Table 10. Open-load detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
IOL
Open-load on-state detection
threshold VIN = 5 V 50 100 200 mA
tDOL(on)
Open-load on-state detection
delay IOUT = 0 A 200 µs
VOL
Open-load off-state voltage
detection threshold VIN = 0 V 1.5 2.5 3.5 V
tDOL(off)
Open-load detection delay at
turn-off 1000 µs
Table 11. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level 1.25 V
IIL Low level input current VIN = 1.25 V 1 µA
VIH Input high level 3.25 V
IIH High level input current VIN = 3.25 V 10 µA
VI(hyst) Input hysteresis voltage 0.5 V
VICL Input clamp voltage IIN = 1 mA 6 6.8 8 V
IIN = -1 mA -0.7 V
Table 8. Status pin (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 10/28
Figure 4. Status timings
Table 12. Truth table
Conditions Input Output Sense
Normal operation L
H
L
H
H
H
Current limitation
L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Overtemperature L
H
L
L
H
L
Undervoltage L
H
L
L
X
X
Overvoltage L
H
L
L
H
H
Output voltage > VOL
L
H
H
H
L
H
Output current < IOL
L
H
L
H
H
L
V
INn
V
STATn
t
DOL(off)
OPEN LOAD STATUS TIMING (with external pull-up)
V
INn
V
STATn
OVER TEMP STATUS TIMING
t
SDL
t
SDL
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
T
j
> T
TSD
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 11/28
Figure 5. Switching time waveforms
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 12/28
Table 15. Electrical transient requirements on VCC pin (part 3)
Table 13. Electrical transient requirements on VCC pin (part 1)
ISO T/R
7637/1
test pulse
Test levels
I II III IV Delays and impedance
1 -25 V -50 V -75 V -100 V 2ms, 10Ω
2 +25 V +50 V +75 V +100 V 0.2 ms, 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs, 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs, 50 Ω
4 -4 V -5 V -6 V -7 V 100 ms, 0.01 Ω
5 +26.5V +46.5V +66.5V +86.5V 400ms, 2Ω
Table 14. Electrical transient requirements on VCC pin (part 2)
ISO T/R
7637/1
test pulse
Test levels results
I II III IV
1 CCCC
2 CCCC
3a CCCC
3b CCCC
4 CCCC
5CEEE
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
EOne or more functions of the device is not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 13/28
Figure 6. Waveforms
OPEN-LOAD without external pull-up
STATUSn
INPUTn
NORMAL OPERATION
UNDERVOLTAGE
VCC
VUSD
VUSDhyst
INPUTn
OVERVOLTAGE
VCC
VCC > VOV
STATUSn
INPUTn
STATUSn
STATUSn
INPUTn
STATUSn
INPUTn
OPEN-LOAD with external pull-up
undefined
OVERTEMPERATURE
INPUTn
STATUSn
TTSD
TR
Tj
OUTPUT VOLTAGEn
VCC<VOV
OUTPUT VOLTAGEn
OUTPUT VOLTAGEn
OUTPUT VOLTAGEn
OUTPUT VOLTAGEn
OUTPUT CURRENTn
VOUT > VOL
VOL
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 14/28
2.4 Electrical characteristics curves
Figure 7. Off-state output current Figure 8. High level input current
Figure 9. Input clamp voltage Figure 10. Status leakage current
Figure 11. Status low output voltage Figure 12. Status clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
IL(off1) (uA)
Off state
Vcc=36V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iih (uA)
Vin=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vicl (V)
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.01
0.02
0.03
0.04
0.05
Ilstat (uA)
Vstat=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Vstat (V)
Istat=1.6mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vscl (V)
Istat=1mA
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 15/28
Figure 13. On-state resistance vs Tcase Figure 14. On-state resistance vs VCC
Figure 15. Open-load on-state detection
threshold
Figure 16. Open-load off-state detection
threshold
Figure 17. Input high level Figure 18. Input low level
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
20
40
60
80
100
120
140
160
Ron (mOhm)
Iout=2A
Vcc=8V; 13V & 36V
5 10152025303540
Vcc (V)
0
10
20
30
40
50
60
70
80
90
100
110
120
Ron (mOhm)
Iout=5A
Tc= - 40°C
Tc=25°C
Tc=150°C
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
50
60
70
80
90
100
110
120
130
140
150
Iol (mA)
Vcc=13V
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vol (V)
Vin=0V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C )
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vil (V)
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 16/28
Figure 19. Input hysteresis voltage Figure 20. Overvoltage shutdown
Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope
Figure 23. ILIM vs Tcase
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Vhyst (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
30
32
34
36
38
40
42
44
46
48
50
Vov (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
100
200
300
400
500
600
700
800
dVout/dt(on) (V/ms)
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
200
250
300
350
400
450
500
550
600
dVout/dt(off) (V/ms)
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
2
4
6
8
10
12
14
16
18
20
Ilim (A)
Vcc=13V
VND830SP-E Electrical specifications
Doc ID 10879 Rev 3 17/28
2.5 Maximum demagnetization energy
Figure 24. PowerSO-10 maximum turn-off current versus load inductance
V
IN
, I
L
t
Demagnetization Demagnetization Demagnetization
A = single pulse at TJstart = 150 °C
B= repetitive pulse at TJstart = 100 °C
C= repetitive pulse at TJstart = 125 °C
1
10
100
0,1 1 10 100
L( mH)
ILM AX (A)
A
B
C
Conditions:
VCC= 13.5 V
Note:
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature
specified above for curves B and C.
VND830SP-E Application schematic
Doc ID 10879 Rev 3 18/28
3 Application schematic
Figure 25. Application schematic
3.1 GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1 Solution 1: a resistor in the ground line (RGND only)
This can be used with any type of load.
The following show how to dimension the RGND resistor:
1. RGND ≤ 600 mV / IS(on)max
2. RGND ≥ (-VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC < 0 during reverse battery situations) is:
PD = (-VCC)2/ RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
V
CC
OUTPUT2
D
ld
+5V
R
prot
OUTPUT1
STATUS1
INPUT1
+5V
STATUS2
INPUT2
GND
+5V
μ
CR
prot
R
prot
R
prot
D
GND
R
GND
V
GND
VND830SP-E Application schematic
Doc ID 10879 Rev 3 19/28
Please note that, if the microprocessor ground is not shared by the device ground, then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high-side drivers sharing the same RGND.
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.
3.1.2 Solution 2: a diode (DGND) in the ground line
A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device will be driving
an inductive load. This small signal diode can be safely shared amongst several different
HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in
the input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift will not vary if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.
3.2 Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC maximum DC rating. The same applies if the device is subject to transients on the VCC
line that are greater than those shown in the ISO T/R 7637/1 table.
3.3 MCU I/O protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the microcontroller I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:
-VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC - VIH - VGND) / IIHmax
Example
For the following conditions:
VCCpeak = -100 V
Ilatchup ≥ 20 mA
VOHμC ≥ 4.5 V
5kΩ ≤ Rprot ≤ 65 kΩ.
Recommended values are:
Rprot = 10 kΩ
VND830SP-E Application schematic
Doc ID 10879 Rev 3 20/28
3.4 Open-load detection in off-state
Off-state open load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1. no false open load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT = (VPU / (RL + RPU))RL < VOlmin.
2. no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2).
Because IS(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-
up resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
Figure 26. Open-load detection in off-state
VND830SP-E Package and PCB thermal data
Doc ID 10879 Rev 3 21/28
4 Package and PCB thermal data
4.1 PowerSO-10 thermal data
Figure 27. PowerSO-10 PC board
Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB
thickness = 2 mm, Cu thickness = 35 µm, Copper areas: from minimum pad lay-out to
8cm
2).
Figure 28. Rthj-amb vs PCB copper area in open box free air condition
VND830SP-E Package and PCB thermal data
Doc ID 10879 Rev 3 22/28
Figure 29. Thermal impedance junction ambient single pulse
Equation 1: pulse calculation formula
Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10
ZTHδRTH δZTHtp 1δ–()+⋅=
where
δtpT⁄=
T_amb
Pd1
C1
R4
C3 C4
R3R1 R6R5R2
C5 C6C2
Pd2
R2
C1 C2
R1
Tj_1
Tj_2
VND830SP-E Package and PCB thermal data
Doc ID 10879 Rev 3 23/28
Table 16. Thermal parameters
Area / island (cm2) Footprint 6
R1 (°C/W) 0.15
R2 (°C/W) 0.8
R3 (°C/W) 0.7
R4 (°C/W) 0.8
R5 (°C/W) 12
R6 (°C/W) 37 22
C1 (W.s/°C) 0.0006
C2 (W.s/°C) 2.1E-03
C3 (W.s/°C) 0.013
C4 (W.s/°C) 0.3
C5 (W.s/°C) 0.75
C6 (W.s/°C) 3 5
VND830SP-E Package and packing information
Doc ID 10879 Rev 3 24/28
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2 PowerSO-10 package information
Figure 31. PowerSO-10 package dimensions
DETAIL "A"
PLANE
SEATING
α
L
A1
F
A1
h
A
D
D1
= =
= =
E4
0.10 A
E
C
A
B
B
DETAIL "A"
SEATING
PLANE
E2
10
1
eB
HE
0.25
VND830SP-E Package and packing information
Doc ID 10879 Rev 3 25/28
Table 17. PowerSO-10 mechanical data
DIM.
mm.
Min. Typ. Max.
A 3.35 3.65
A(1)
1. Muar only POA P013P.
3.4 3.6
A1 0 0.10
B 0.40 0.60
B(1) 0.37 0.53
C 0.35 0.55
C(1) 0.23 0.32
D 9.40 9.60
D1 7.40 7.60
E 9.30 9.50
E2 7.20 7.60
E2(1) 7.30 7.50
E4 5.90 6.10
E4(1) 5.90 6.30
e1.27
F 1.25 1.35
F(1) 1.20 1.40
H 13.80 14.40
H(1) 13.85 14.35
h0.50
L 1.20 1.80
L(1) 0.80 1.10
α0° 8°
α(1) 2° 8°
VND830SP-E Package and packing information
Doc ID 10879 Rev 3 26/28
5.3 PowerSO-10 packing information
Figure 34. PowerSO-10 tape and reel shipment (suffix “TR”)
Figure 32. PowerSO-10 suggested
pad layout
Figure 33. PowerSO-10 tube shipment
(no suffix)
B
A
C
All dimensions are in mm.
Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1)
Casablanca 50 1000 532 10.4 16.4 0.8
Muar 50 1000 532 4.9 17.2 0.8
C
A
B
MUARCASABLANCA
Base Q.ty 600
Bulk Q.ty 600
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 24
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Reel dimensions
DocID10879 Rev 3 28/28
VND830SP-E
28
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