LM48823TLBD - National Semiconductor

July 16, 2008

LM48823

Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C

Volume Control and Reset

General Description

The LM48823 is a single supply, mono, ceramic speaker driv-

er with an integrated charge-pump, designed for portable

devices, such as cell phones, where board space is at a pre-

mium. The LM48823 charge pump allows the device to deliver

5.4VRMS from a single 4.2V supply.

The LM48823 features high power supply rejection ratio

(PSRR), 93dB at 217Hz, allowing the device to operate in

noisy environments without additional power supply condi-

tioning. Flexible power supply requirements allow operation

from 2.0V to 4.5V. The LM48823 features an active low reset

input that reverts the device to its default state. Additionally,

the LM48823 features a 32-step I2C volume control. The low

power Shutdown mode reduces supply current consumption

to 0.01µA.

The LM48823’s superior click and pop suppression elimi-

nates audible transients on power-up/down and during shut-

down. The LM48823 is available in an ultra-small 16-bump

micro SMD package (2mmx2mm).

Key Specifications

■ Output Voltage at VDD = 4.2V,

RL = 2.2µF + 15Ω THD+N ≤ 1% 5.4VRMS (typ)

■ Quiescent Power Supply Current

at 4.2V 3.3mA (typ)

■ PSRR at 217Hz 93dB (typ)

■ Shutdown current 0.01μA (typ)

Features

■Integrated Charge Pump

■Bridge-tied Load Output

■High PSRR

■I2C Volume and Mode Control

■Reset Input

■Advanced Click-and-Pop Suppression

■Low Supply Current

■Minimum external components

■Micro-power shutdown

■Available in space-saving 16-bump µSMD package

Applications

■Cell phones

■Smart phones

■Portable media devices

■Notebook PCs

Boomer® is a registered trademark of National Semiconductor Corporation.

Tru-GND is a trademark of National Semiconductor Corporation.

LM48823 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset

Typical Application

300684e1

FIGURE 1. Typical Audio Amplifier Application Circuit

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LM48823

Connection Diagrams

TL Package

2mm x 2mm x 0.8mm

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Top View

See NS Package Number TLA1611A

16–Bump micro SMD Marking

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Top View

XY – Date Code

TT – Lot Traceability

G – Boomer Family

K6 – LM48823TL

Ordering Information

Order Number Package Package DWG # Transport Media MSL Level Green Status

LM48823TL 16–Bump micro SMD TLA1611A 250 units on tape and reel 1 NOPB

LM48823TLX 16–Bump micro SMD TLA1611A 3000 units on tape and reel 1 NOPB

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LM48823

TABLE 1. Bump Descriptions

Pin Designator Pin Name Pin Function

A1 SVDD Signal Power Supply

A2 SGND Signal Ground

A3 BYPASS Amplifier Reference Bypass

A4 INA Amplifier Inverting input A

B1 OUTA Amplifier Inverting output A

B2 OUTB Amplifier Non-Inverting Output B

B3 RESET

Active Low Reset Input. Connect to VDD for normal

operation. Toggle between VDD and GND to reset the

device.

B4 INB Amplifier Non-Inverting Input B

C1 VSS Charge Pump Output

C2 SCL I2C Serial Clock Input

C3 SDA I2C Serial Data Input

C4 I2CVDD I2C Supply Voltage

D1 C1N Charge Pump Flying Capacitor Negative Terminal

D2 PGND Power Ground

D3 C1P Charge Pump Flying Capacitor Positive Terminal

D4 PVDD Power Supply

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LM48823

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (Note 1) 5.25V

Storage Temperature −65°C to +150°C

Input Voltage −0.3V to VDD +0.3V

Power Dissipation (Note 3) Internally Limited

ESD Rating (Note 4) 8kV

ESD Rating (Note 5) 250V

Junction Temperature 150°C

Thermal Resistance

θJA (typ) - (TLA1611A) 63.2°C/W

Operating Ratings

Temperature Range

TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C

Supply Voltage

PVDD and SVDD 2.0V ≤ VDD ≤ 4.5V

I2CVDD 1.8V ≤ I2CVDD ≤ 4.5V

Audio Amplifier Electrical Characteristics VDD = 4.2V (Notes 1, 2)

The following specifications apply for AV = 6dB, RL = 2.2μF+15Ω, C1 = C2 = 2.2μF, f = 1kHz, unless otherwise specified. Limits

apply for TA = 25°C.

Symbol Parameter Conditions

LM48823 Units

(Limits)

Typical

(Note 6)

Limits

(Note 7)

IDD

Quiescent Power Supply

Current

VIN = 0V, RL = ∞3.3 4.3 mA (max)

ISD Shutdown Current Shutdown Enabled 0.01 1 µA (max)

VOS

Differential Output Offset

Voltage VIN = 0V 0.5 3 mV (max)

VIH Logic High Input Threshold RESET 1.4 V (min)

VIL RESET 0.4 V (max)

AVGain Minimum Gain Setting –70 dB

Maximum Gain Setting 24 dB

RIN Input Resistance

Maximum Gain Setting 9 7

kΩ (min)

kΩ (max)

Minimum Gain Setting 80 64

kΩ (min)

kΩ (max)

VOOutput Voltage

RL = 2.2μF+15Ω, THD+N = 1%

f = 1kHz

f = 5kHz

5.4

3.1

VRMS

THD+N Total Harmonic Distortion +

Noise

VO = 4VRMS 0.015 %

PSRR Power Supply Rejection Ratio

VRIPPLE = 200mVP-P Sine, Inputs AC GND, CIN = 1μF, input referred

f = 217Hz

f = 1kHz

82 dB (min)

SNR Signal-to-Noise-Ratio POUT = 40mW, RL = 16Ω

f = 1kHz 119 dB

∈OS Output Noise AV = 4dB, Input Referred, A-weighted Filter 5.5 μV

TWU Wake-Up Time 200 μs

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LM48823

I2C Interface Characteristics VDD = 3.0V (Notes 1, 2)

The following specifications apply for AV = 6dB, RL = 2.2μF+15Ω, C1 = C2 = 2.2μF, f = 1kHz, unless otherwise specified. Limits

apply for TA = 25°C.

Symbol Parameter Conditions

LM48823 Units

(Limits)

Typical

(Note 6)

Limits (Note 7)

t1SCL period 2.5 μs (min)

t2SDA Setup Time 100 ns (min)

t3SDA Stable Time 0 ns (min)

t4Start Condition Time 100 ns (min)

t5Stop Condition Time 100 ns (min)

VIH Logic High Input Threshold 0.7 x I2CVDD V (min)

VIL Logic Low Input Threshold 0.3 x I2CVDD V (max)

Note 1: :. “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.

Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum

allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.

Note 4: Human body model, applicable std. JESD22-A114C.

Note 5: Machine model, applicable std. JESD22-A115-A.

Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product

characterization and are not guaranteed.

Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.

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LM48823

Typical Performance Characteristics

THD+N vs Frequency

VDD = 3.6V

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THD+N vs Frequency

VDD = 4.2V

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THD+N vs Output Voltage

AV = 6dB, ZL = 1μF+15Ω, f = 1kHz

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THD+N vs Output Voltage

AV = 6dB, ZL = 2.2μF+15Ω, f = 1kHz

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Output Voltage vs Frequency

VDD = 4.2V, ZL = 1μF+15Ω,THD+N = 1%

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Output Voltage vs Frequency

VDD = 4.2V, ZL = 2.2μF+15Ω,THD+N = 1%

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LM48823

Power Consumption vs Output Voltage

VDD = 3.6V, ZL = 1μF+15Ω

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Power Consumption vs Output Voltage

VDD = 3.6V, ZL = 2.2μF+15Ω

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Power Consumption vs Output Voltage

VDD = 4.2V, ZL = 1μF+15Ω

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Power Consumption vs Output Voltage

VDD = 4.2V, ZL = 2.2μF+15Ω

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Output Voltage vs Supply Voltage

ZL = 1μF+15Ω, THD+N = 1%

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Output Voltage vs Supply Voltage

ZL = 2.2μF+15Ω, THD+N = 1%

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LM48823

PSRR vs Frequency

VDD = 4.2V, VRIPPLE = 200mVP-P

ZL = 1μF+15Ω, Input referred

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Supply Current vs Supply Voltage

No Load

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Shutdown Current vs Supply Voltage

No Load

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LM48823

Application Information

I2C COMPATIBLE INTERFACE

The LM48823 is controlled through an I2C compatible serial

interface that consists of a serial data line (SDA) and a serial

clock (SCL). The clock line is uni-directional. The data line is

bi-directional (open drain). The LM48823 and the master can

communicate at clock rates up to 400kHz. Figure 2 shows the

I2C interface timing diagram. Data on the SDA line must be

stable during the HIGH period of SCL. The LM48823 is a

transmit/receive slave-only device, reliant upon the master to

generate the SCL signal. Each transmission sequence is

framed by a START condition and a STOP condition (Figure

3). Each data word, device address and data, transmitted

over the bus is 8 bits long and is always followed by an ac-

knowledge pulse (Figure 4). The LM48823 device address is

1110110.

I2C BUS FORMAT

The I2C bus format is shown in Figure 4. The START signal,

the transition of SDA from HIGH to LOW while SCL is HIGH,

is generated, alerting all devices on the bus that a device ad-

dress is being written to the bus.

The 7-bit device address is written to the bus, most significant

bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the

master is writing to the slave device, R/W = 1 indicates the

master wants to read data from the slave device. Set R/W =

0; the LM48823 is a WRITE-ONLY device and will not re-

spond to the R/W = 1. The data is latched in on the rising edge

of the clock. Each address bit must be stable while SCL is

HIGH. After the last address bit is transmitted, the master de-

vice releases SDA, during which time, an acknowledge clock

pulse is generated by the slave device. If the LM48823 re-

ceives the correct address, the device pulls the SDA line low,

generating an acknowledge bit (ACK).

Once the master device registers the ACK bit, the 8-bit reg-

ister data word is sent. Each data bit should be stable while

SCL is HIGH. After the 8-bit register data word is sent, the

LM48823 sends another ACK bit. Following the acknowl-

edgement of the register data word, the master issues a

STOP bit, allowing SDA to go high while SCL is high.

30068467

FIGURE 2. I2C Timing Diagram

300684g8

FIGURE 3. Start and Stop Diagram

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LM48823

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FIGURE 4. Example Write Sequence

TABLE 2. Device Address

B7 B6 B5 B4 B3 B2 B1 B0 R/W

Chip Address 1 1 1 0 1 1 0 0

TABLE 3. Mode Control Registers

Mode Control VOL4 VOL3 VOL2 VOL1 VOL0 0 ENABLE_A ENABLE_B

GENERAL AMPLIFIER FUNCTION

The LM48823 is a ceramic speaker driver that utilizes National’s inverting charge pump technology to deliver over 15VP-P to a

2.2µF ceramic speaker while operating from a single 4.2V supply. The LM48823 features a unique input stage that converts two

single-ended audio signals into a mono BTL output. This stereo to mono conversion is useful in applications where a stereo audio

source is driving a single ceramic speaker, such as a ringer on a cellular phone. Connect INA and INB as shown in Figure 5 for

the stereo-to-mono conversion. When the LM48823 is used with a single-ended mono audio source, connect both INA and INB to

the audio source as shown in Figure 6.

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FIGURE 5. Stereo to Mono Conversion Connection Example

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FIGURE 6. Mono Audio Source Connection Example

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LM48823

VOLUME CONTROL

TABLE 4. Volume Control

Volume Step VOL4 VOL3 VOL2 VOL1 VOL0 Gain (dB)

1 0 0 0 0 0 –70

2 0 0 0 0 1 –56

3 0 0 0 1 0 –46

4 0 0 0 1 1 –38

5 0 0 1 0 0 –32

6 0 0 1 0 1 –28

7 0 0 1 1 0 –24

8 0 0 1 1 1 –21

9 0 1 0 0 0 –18

10 0 1 0 0 1 –15

11 0 1 0 1 0 –12

12 0 1 0 1 1 –10

13 0 1 1 0 0 –8

14 0 1 1 0 1 –6

15 0 1 1 1 0 –4

16 0 1 1 1 1 –2

17 1 0 0 0 0 0

18 1 0 0 0 1 2

19 1 0 0 1 0 4

20 1 0 0 1 1 6

21 1 0 1 0 0 8

22 1 0 1 0 1 10

23 1 0 1 1 0 12

24 1 0 1 1 1 16

25 1 1 0 0 0 14

26 1 1 0 0 1 15

27 1 1 0 1 0 16

28 1 1 0 1 1 17

29 1 1 1 0 0 18

30 1 1 1 0 1 22

31 1 1 1 1 0 23

32 1 1 1 1 1 24

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LM48823

SHUTDOWN FUNCTION

The LM48823 features a low-power shutdown mode that dis-

ables the device, lowering the quiescent current to 0.01µA.

Set bits B1 (ENABLE_A) and B2 (ENABLE_B) to 0 to disable

the amplifiers and charge pump. Set both ENABLE_A and

ENABLE_B to 1 for normal operation. Shutdown mode does

not clear the I2C register. When re-enabled, the device returns

to its previous volume setting. To clear the I2C register, either

remove power from the device, or toggle RESET (see RE-

SET section).

RESET

The LM48823 features an active low reset input. Driving RE-

SET low clears the I2C register. Volume control is set to 00000

(-70dB) and both ENABLE_A and ENABLE_B are set to 0,

disabling the device. While RESET is low, the LM48823 ig-

nores any I2C data. After the device is reset, and RESET is

driven high, the LM48823 remains in shutdown mode with the

volume set to -70dB. Re-enable the device by writing to the

I2C register.

PROPER SELECTION OF EXTERNAL COMPONENTS

Power Supply Bypassing/Filtering

Proper power supply bypassing is critical for low noise per-

formance and high PSRR. Place the supply bypass capaci-

tors as close to the device as possible. Place a 1µF ceramic

capacitor from VDD to GND. Additional bulk capacitance may

be added as required.

Bypass Capacitor Selection

The BYPASS capacitor, CBYPASS, improves PSRR, noise re-

jection and output offset. For best results, use a capacitor of

identical value to the input coupling capacitors

Charge Pump Capacitor Selection

Use low ESR ceramic capacitors (less than 100mΩ) for opti-

mum performance.

Charge Pump Flying Capacitor (C1)

The flying capacitor (C1) affects the load regulation and out-

put impedance of the charge pump. A C1 value that is too low

results in a loss of current drive, leading to a loss of amplifier

headroom. A higher valued C1 improves load regulation and

lowers charge pump output impedance to an extent. Above

2.2µF, the RDS(ON) of the charge pump switches and the ESR

of C1 and C2 dominate the output impedance. A lower value

capacitor can be used in systems with low maximum output

power requirements.

Charge Pump Hold Capacitor (C2)

The value and ESR of the hold capacitor (C2) directly affects

the ripple on CPVSS. Increasing the value of C2 reduces out-

put ripple. Decreasing the ESR of C2 reduces both output

ripple and charge pump output impedance. A lower value ca-

pacitor can be used in systems with low maximum output

power requirements.

Input Capacitor Selection

Input capacitors block the DC component of the audio signal,

eliminating any conflict between the DC component of the

audio source and the bias voltage of the LM48823. The input

capacitors create a high-pass filter with the input resistors

RIN. The -3dB point of the high pass filter is found using Equa-

tion (1) below.

f = 1 / 2πRINCIN (Hz) (1)

Where the value of RIN is given in the Electrical Characteris-

tics Table.

High pass filtering the audio signal helps protect the speakers.

When the LM48823 is using a single-ended source, power

supply noise on the ground is seen as an input signal. Setting

the high-pass filter point above the power supply noise fre-

quencies, 217Hz in a GSM phone, for example, filters out the

noise such that it is not amplified and heard on the output.

Capacitors with a tolerance of 10% or better are recommend-

ed for impedance matching and improved CMRR and PSRR.

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LM48823

PCB Layout Guidelines

Minimize trace impedance of the power, ground and all output

traces for optimum performance. Voltage loss due to trace

resistance between the LM48823 and the load results in de-

creased output power and efficiency. Trace resistance be-

tween the power supply and ground has the same effect as a

poorly regulated supply, increased ripple and reduced peak

output power. Use wide traces for power supply inputs and

amplifier outputs to minimize losses due to trace resistance,

as well as route heat away from the device. Proper grounding

improves audio performance, minimizes crosstalk between

channels and prevents switching noise from interfering with

the audio signal. Use of power and ground planes is recom-

mended.

Place all digital components and route digital signal traces as

far as possible from analog components and traces. Do not

run digital and analog traces in parallel on the same PCB lay-

er. If digital and analog signal lines must cross either over or

under each other, ensure that they cross in a perpendicular

fashion.

LM48823TL Demoboard Bill of Materials

Designator Quantity Description

C1, C2 2 2.2µF ±10% 10V X5R Ceramic Capacitor (603) Panasonic

ECJ-1VB1A225K Murata GRM033R6OJ104KE19D

C3 – C5 3 1µF ±10% 10V Tantalum Capacitor (402) AVX TACK105M010QTA

C6 1 4.7µF ±10% 6.3V X5R Ceramic Capacitor (603) Panasonic

ECJ-1VB0J475K Murata GRM188R6OJ475KE19D

C7, C8 2 0.1µF ±10% 6.3V X5R Ceramic Capacitor (201) Panasonic ECJ-

ZEB0J104K Murata GRM188R61A225KE34D

JU1 – JU5 5 2 Pin Header

JU6, JU7 3 2 Pin Header

J1 1 5-Pin I2C Header

LM4823TL 1 LM48823TL (16-Bump microSMD)

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LM48823

Demo Board Schematic

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FIGURE 7. LM48823 Demo Board Schematic

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LM48823

PC Board Layout

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FIGURE 8: Top Silkscreen Layer

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FIGURE 9: Top Layer

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FIGURE 10: Layer 2

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FIGURE 11: Layer 3

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FIGURE 12: Bottom Layer

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FIGURE 13: Bottom Silkscreen

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LM48823

Revision History

Rev Date Description

1.0 06/27/08 Initial release.

1.01 07/15/08 Edited the Ordering Information table.

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LM48823

Physical Dimensions inches (millimeters) unless otherwise noted

16-Bump micro SMD

Order Number LM48823TL

NS Package Number TLA1611A

X1 = 1.970± 0.03 X2 = 1.970 ± 0.03 X3 = 0.6 ± 0.075

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LM48823

Notes

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LM48823

Notes

LM48823 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset

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