PRELIMINARY
128K x 8 Stat ic RAM
CY7C1019
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05055 Rev. ** Revised August 31, 2001
019
Features
• High speed
—tAA = 10 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
Functional Description
The CY7C1019 is a high-performance CMOS static RAM or-
ganize d as 131,07 2 words by 8 bits. Easy me mory exp ansio n
is provided b y an a ctive L OW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. This device has
an automatic power-down feature that significantly reduces
power consumption when de sel ected.
Writing to the device is accomplished by taking chip enable
(CE) and wri te enable (WE ) inputs LO W . D ata on the e ight I/O
pins (I/O0 through I/O7) is then written into the location speci-
fied on the address pins (A0 through A16).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write
enable (WE) HIGH. Under these conditions, the contents of
the memo ry l ocatio n spec ified by the add ress pi ns will a ppear
on the I/O pins.
The eight inp ut/o utp ut pin s (I/O0 thro ug h I/ O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019 is available in standard 400-mil-wide SOJs.
14
15
Logic Block Diagram Pin Configuration
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512 x 256 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A
11
A
13
A
12
A
A
10
CE
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15 17
18
A7
A1
A2
A3
CE
I/O0
I/O1
VCC
A13
A16
A15
OE
I/O7
I/O6
A12
A11
A10
A9
I/O2
A0
A4
A5
A6
I/O4
VCC
I/O5
A8
I/O3
WE
VSS
A14
1019–1
1019–2
VSS
Selection Guide
7C1019–10 7C1019–12 7C1019–15
Maximum Access Time (ns) 10 12 15
Maximum Operating Current (mA) 240 220 200
L210 190 175
Maximum Standby Current (mA) 10 10 10
L 1 1 1
Shaded ar eas contain ad vance inform ation.
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. ** Page 2 of 8
Maximum Ratings
(Above w hi ch the useful life m ay be impaired. For us er g uid e-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z Sta te[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Test Conditions
7C1019-10 7C1019-12 7C1019-15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Volt age VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Loa d Cur r ent GND < VI < VCC –1+1 –1+1–1+1µA
IOZ Output Leakage
Current GND < VI < VCC,
Output Disabled –5+5 –5+5–5+5µA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
240 220 200 mA
L210 190 175
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
40 40 40 mA
L20 20 20
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3 V,
or VIN < 0.3V, f=0
10 10 10 mA
L111
Shaded ar eas contain ad vance inform ation.
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capa cit anc e TA = 25°C, f = 1 MHz,
VCC = 5.0V 6pF
COUT Output Capacitance 8 pF
Notes:
1. VIL (min.) = –2.0V for puls e durat ions of less than 20 ns.
2. TA is the “instant on” ca se temperature .
3. Tested initially and after any design or process changes that may affect these parameters.
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. ** Page 3 of 8
AC Test Loads and W aveforms
1019–31019–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AN D
SCOPE
(a) (b)
≤ 3ns ≤3ns
OUTPUT
R1 480ΩR1 480Ω
R2
255ΩR2
255Ω
167Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
Switching Characteristics[4] Ov er the Op eratin g Range
7C1019-10 7C1019-12 7C1019-15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 10 12 15 ns
tAA Address to Data Valid 10 12 15 ns
tOHA Data Hold from Address Change 333ns
tACE CE LOW to Data Valid 10 12 15 ns
tDOE OE LOW to Data Valid 567ns
tLZOE OE LOW to Low Z 000ns
tHZOE OE HIGH to High Z[5, 6] 567ns
tLZCE CE LOW to Low Z[6] 333ns
tHZCE CE HIGH to High Z[5 , 6 ] 567ns
tPU CE LOW to Power-Up 000ns
tPD CE HIGH to Power-Down 10 12 15 ns
WRI T E CYCLE[7,8]
tWC Write Cycle Time 10 12 15 ns
tSCE CE LO W to Write End 8910ns
tAW Address Set-Up to W rit e End 7810ns
tHA Address Hold from Write End 000ns
tSA Address Set-Up to W rit e Start 000ns
tPWE WE Pulse Width 7810ns
tSD Data Set-Up to Write End 568ns
tHD Data Hold from Write End 000ns
tLZWE WE HIGH to Low Z[6] 333ns
tHZWE WE LOW to High Z[5, 6] 567ns
Shaded areas contain advance information.
Note:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capac itance.
5. tHZOE, tHZCE, and tHZWE are speci fied wi th a load cap acita nce of 5 pF as in pa rt (b) of AC Test Loa ds. T r ansiti on is mea sured ±500 m V from s teady- state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less tha n tLZOE, and t HZWE is less than tLZWE for any given devic e.
7. The internal write time of the memory is defined by the overlap of CE LO W and WE LO W. C E and WE mus t be LOW to ini tiate a w rite, and the tr ansition of any of these
signal s can te rminat e the write. The in put data set-up and ho ld timi ng sh ould b e refe renced to the l eading edge of the s ignal t hat te rminates the wri te.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. ** Page 4 of 8
Data Retention Characteristics Ov er the Operating Range (L Version Only)
Parameter Description Conditions Min. Max Unit
VDR VCC for Data Retention No input may exceed VCC + 0.5V
VCC = VDR = 3.0V,
CE1 > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0 V
ICCDR Data Retention Current 300 µA
tCDR[3] Chip Deselect to Data Retention Time 0 ns
tROperation Recovery Time tRC ns
Data Retention Waveform
1019–5
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
Switching Waveform s
Read Cycle No. 1[9, 10]
Read Cycle No. 2 (OE Controlled)[10, 11]
Notes:
9. Device is continuously selected. OE, CE = VIL.
10. WE is HIGH f or read cycle .
11. Address valid prior to or coincident with CE transit ion LOW.
PREVIOUS DATA VALID DATA VALI D
tRC
tAA
tOHA
1019–6
ADDRESS
DATA OUT
1019–7
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. ** Page 5 of 8
Write Cycle No. 1 (CE Controlled)[12, 13]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
Notes:
12. Data I/O is high impedance if OE = VIH.
13. If CE goe s HIGH simulta neously wit h WE going HIGH, the o utput remains i n a h igh-imped ance stat e.
14. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveform s (continued)
1019–8
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
ADDRESS
WE
DATA I/O
1019–9
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 14
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. ** Page 6 of 8
Write Cycle No. 3 (WE Controlled, OE LOW)[13]
Switching Waveform s (continued)
1019–10
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 14
Truth Table
CE OE WE I/O0–I/O7Mode Power
H X X High Z Power-Down Standby (ISB)
X X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
10 CY7C1019-10VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019L-10VC V33 32-Lead 400-Mil Molded SOJ
12 CY7C1019-12VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019L-12VC V33 32-Lead 400-Mil Molded SOJ
15 CY7C1019-15VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019L-15VC V33 32-Lead 400-Mil Molded SOJ
Shaded area contains advance information.
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. ** Page 7 of 8
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expe cted to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
32-Lead (400-Mil) Molded SOJ V33
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. ** Page 8 of 8
Document Title: 7C1019 128K x 8 Static RAM
Document Number: 38-05055
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 107246 09/10/01 SZV Change from Spec number: 38-00440 to 38-05055
