CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. ** Page 3 of 8
AC Test Loads and W aveforms
1019–31019–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AN D
SCOPE
(a) (b)
≤ 3ns ≤3ns
OUTPUT
R1 480ΩR1 480Ω
R2
255ΩR2
255Ω
167Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
Switching Characteristics[4] Ov er the Op eratin g Range
7C1019-10 7C1019-12 7C1019-15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 10 12 15 ns
tAA Address to Data Valid 10 12 15 ns
tOHA Data Hold from Address Change 333ns
tACE CE LOW to Data Valid 10 12 15 ns
tDOE OE LOW to Data Valid 567ns
tLZOE OE LOW to Low Z 000ns
tHZOE OE HIGH to High Z[5, 6] 567ns
tLZCE CE LOW to Low Z[6] 333ns
tHZCE CE HIGH to High Z[5 , 6 ] 567ns
tPU CE LOW to Power-Up 000ns
tPD CE HIGH to Power-Down 10 12 15 ns
WRI T E CYCLE[7,8]
tWC Write Cycle Time 10 12 15 ns
tSCE CE LO W to Write End 8910ns
tAW Address Set-Up to W rit e End 7810ns
tHA Address Hold from Write End 000ns
tSA Address Set-Up to W rit e Start 000ns
tPWE WE Pulse Width 7810ns
tSD Data Set-Up to Write End 568ns
tHD Data Hold from Write End 000ns
tLZWE WE HIGH to Low Z[6] 333ns
tHZWE WE LOW to High Z[5, 6] 567ns
Shaded areas contain advance information.
Note:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capac itance.
5. tHZOE, tHZCE, and tHZWE are speci fied wi th a load cap acita nce of 5 pF as in pa rt (b) of AC Test Loa ds. T r ansiti on is mea sured ±500 m V from s teady- state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less tha n tLZOE, and t HZWE is less than tLZWE for any given devic e.
7. The internal write time of the memory is defined by the overlap of CE LO W and WE LO W. C E and WE mus t be LOW to ini tiate a w rite, and the tr ansition of any of these
signal s can te rminat e the write. The in put data set-up and ho ld timi ng sh ould b e refe renced to the l eading edge of the s ignal t hat te rminates the wri te.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.