019 PRELIMINARY CY7C1019 128K x 8 Static RAM Features Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). * High speed -- tAA = 10 ns * CMOS for optimum speed/power * Center power/ground pinout * Automatic power-down when deselected * Easy memory expansion with CE and OE options Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). Functional Description The CY7C1019 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The CY7C1019 is available in standard 400-mil-wide SOJs. Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 I/O0 CE I/O0 I/O1 VCC VSS INPUT BUFFER I/O1 I/O2 I/O3 WE A4 A5 A6 A7 I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 512 x 256 x 8 ARRAY I/O3 I/O4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 COLUMN DECODER OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 I/O6 POWER DOWN I/O7 WE 1019-1 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 OE A16 A15 A14 A13 1019-2 I/O5 CE 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Selection Guide 7C1019-10 7C1019-12 7C1019-15 Maximum Access Time (ns) 10 12 15 Maximum Operating Current (mA) 240 220 200 210 190 175 10 10 10 1 1 1 L Maximum Standby Current (mA) L Shaded areas contain advance information. Cypress Semiconductor Corporation Document #: 38-05055 Rev. ** * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised August 31, 2001 PRELIMINARY CY7C1019 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ................................. -65C to +150C Operating Range Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V Commercial Ambient Temperature[2] VCC 0C to +70C 5V 10% DC Input Voltage[1] ................................-0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range 7C1019-10 Parameter Test Conditions Description Min. Max. Min. Max. Min. Max. Unit 0.4 V Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL Input LOW Voltage[1] -0.3 0.8 -0.3 0.8 -0.3 0.8 V IIX Input Load Current GND < VI < VCC -1 +1 -1 +1 -1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled -5 +5 -5 +5 -5 +5 A ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC mA Automatic CE Power-Down Current --TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX L Automatic CE Power-Down Current --CMOS Inputs Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 L ISB2 2.4 7C1019-15 VOH ISB1 2.4 7C1019-12 0.4 L 2.4 0.4 V 240 220 200 210 190 175 40 40 40 20 20 20 10 10 10 1 1 1 mA mA Shaded areas contain advance information. Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. Unit 6 pF 8 pF Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05055 Rev. ** Page 2 of 8 PRELIMINARY CY7C1019 AC Test Loads and Waveforms R1 480 R1 480 5V ALL INPUT PULSES 5V OUTPUT 3.0V 90% OUTPUT 30 pF R2 255 INCLUDING JIG AND SCOPE (a) R2 255 5 pF INCLUDING JIG AND SCOPE (b) 90% 10% GND 10% 3ns 3 ns 1019-3 1019-4 THEVENIN EQUIVALENT 167 1.73V OUTPUT Equivalent to: Switching Characteristics[4] Over the Operating Range 7C1019-10 Parameter Description Min. Max. 7C1019-12 Min. Max. 7C1019-15 Min. Max. Unit READ CYCLE tRC Read Cycle Time 10 tAA Address to Data Valid tOHA Data Hold from Address Change 12 10 3 15 12 3 ns 15 3 ns ns tACE CE LOW to Data Valid 10 12 15 ns tDOE OE LOW to Data Valid 5 6 7 ns tLZOE OE LOW to Low Z tHZOE 0 [5, 6] OE HIGH to High Z [6] tLZCE CE LOW to Low Z tHZCE CE HIGH to High Z[5, 6] tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 0 5 3 0 6 3 5 0 7 3 6 0 10 ns ns 7 0 12 ns ns ns 15 ns [7,8] WRITE CYCLE tWC Write Cycle Time 10 12 15 ns tSCE CE LOW to Write End 8 9 10 ns tAW Address Set-Up to Write End 7 8 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 7 8 10 ns tSD Data Set-Up to Write End 5 6 8 ns tHD Data Hold from Write End 0 0 0 ns tLZWE WE HIGH to Low Z[6] 3 3 3 ns tHZWE WE LOW to High Z [5, 6] 5 6 7 ns Shaded areas contain advance information. Note: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05055 Rev. ** Page 3 of 8 PRELIMINARY CY7C1019 Data Retention Characteristics Over the Operating Range (L Version Only) Parameter ICCDR tCDR Description Conditions VCC for Data Retention VDR Data Retention Current [3] Chip Deselect to Data Retention Time tR Min. No input may exceed VCC + 0.5V VCC = VDR = 3.0V, CE1 > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Max 2.0 V 300 Operation Recovery Time Unit A 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC 3.0V VDR > 2V tCDR tR CE 1019-5 Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1019-6 Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB 1019-7 Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05055 Rev. ** Page 4 of 8 PRELIMINARY CY7C1019 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[12, 13] tWC ADDRESS tSCE CE tSA tSCE tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID 1019-8 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 14 tHZOE 1019-9 Notes: 12. Data I/O is high impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05055 Rev. ** Page 5 of 8 PRELIMINARY CY7C1019 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[13] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 14 DATA I/O tHD DATA VALID tLZWE tHZWE 1019-10 Truth Table CE OE WE I/O0-I/O7 Mode Power H X X High Z Power-Down Standby (ISB) X X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 12 15 Ordering Code CY7C1019-10VC CY7C1019L-10VC CY7C1019-12VC CY7C1019L-12VC CY7C1019-15VC CY7C1019L-15VC Package Name V33 V33 V33 V33 V33 V33 Package Type 32-Lead 400-Mil Molded SOJ 32-Lead 400-Mil Molded SOJ 32-Lead 400-Mil Molded SOJ 32-Lead 400-Mil Molded SOJ 32-Lead 400-Mil Molded SOJ 32-Lead 400-Mil Molded SOJ Operating Range Commercial Commercial Commercial Shaded area contains advance information. Document #: 38-05055 Rev. ** Page 6 of 8 PRELIMINARY CY7C1019 Package Diagram 32-Lead (400-Mil) Molded SOJ V33 Document #: 38-05055 Rev. ** Page 7 of 8 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1019 Document Title: 7C1019 128K x 8 Static RAM Document Number: 38-05055 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107246 09/10/01 SZV Change from Spec number: 38-00440 to 38-05055 Document #: 38-05055 Rev. ** Page 8 of 8