Data Sheet No. PD60269 IRS2003(S)PbF HALF-BRIDGE DRIVER Features * Floating channel designed for bootstrap operation * Fully operational to +200 V * Tolerant to negative transient voltage, dV/dt immune * Gate drive supply range from 10 V to 20 V * Undervoltage lockout * 3.3 V, 5 V, and 15 V logic compatible * Cross-conduction prevention logic * Matched propagation delay for both channels * Internal set deadtime * High-side output in phase with HIN input * Low-side output out of phase with input * RoHS compliant Product Summary VOFFSET 200 V max. IO+/- 130 mA/270 mA VOUT 10 V - 20 V ton/off (typ.) 680 ns/150 ns Deadtime (typ.) 520 ns Packages Description The IRS2003 is a high voltage, high speed power MOSFET and IGBT drivers with dependent high- and low-side referenced output channels. Proprietary HVIC 8-Lead SOIC 8-Lead PDIP and latch immune CMOS technologies enable ruggeIRS2003S IRS2003 dized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver crossconduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 200 V. Typical Connection (Refer to Lead Assignments for correct configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IRS2003(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. VB High-side floating absolute voltage -0.3 225 VS High-side floating supply offset voltage VB - 25 VB + 0.3 VHO High-side floating output voltage VS - 0.3 VB + 0.3 VCC Low-side and logic fixed supply voltage -0.3 25 VLO Low-side output voltage -0.3 VCC + 0.3 Logic input voltage (HIN & ) -0.3 VCC + 0.3 -- 50 VIN dVs/dt PD RthJA Allowable offset supply voltage transient Package power dissipation @ TA +25 C Thermal resistance, junction to ambient (8 Lead PDIP) -- 1.0 (8 Lead SOIC) -- 0.625 (8 Lead PDIP) -- 125 (8 Lead SOIC) -- 200 TJ Junction temperature -- 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) -- 300 Units V V/ns W C/W C Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential. Symbol Definition VB High-side floating supply absolute voltage VS High-side floating supply offset voltage Min. Max. VS + 10 VS + 20 Note 1 200 VHO High-side floating output voltage VS VB VCC Low-side and logic fixed supply voltage 10 20 VLO Low-side output voltage 0 VCC VIN Logic input voltage (HIN & ) 0 VCC TA Ambient temperature -40 125 Units V C Note 1: Logic operational for VS of -5 V to +200 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip DT97-3 for more details). www.irf.com 2 IRS2003(S)PbF Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15 V, CL = 1000 pF and TA = 25 C unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay -- 680 820 VS = 0 V toff Turn-off propagation delay -- 150 220 VS = 200 V tr Turn-on rise time -- 70 170 tf Turn-off fall time -- 35 90 400 520 650 -- -- 60 DT Deadtime, LS turn-off to HS turn-on & HS turn-on to LS turn-off MT Delay matching, HS & LS turn-on/off ns Static Electrical Characteristics VBIAS (VCC, VBS) = 15 V and TA = 25 C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Definition Min. Typ. Max. Units Test Conditions VIH Logic "1" (HIN) & Logic "0" ( ) input voltage 2.5 -- -- VIL Logic "0" (HIN) & Logic "1" ( ) input voltage -- -- 0.8 VOH High level output voltage, VBIAS - VO -- 0.05 0.2 VOL Low level output voltage, VO -- 0.02 0.1 VCC = 10 V to 20 V V IO = 2 mA ILK Offset supply leakage current -- -- 50 IQBS Quiescent VBS supply current -- 30 55 VB = VS = 200 V IQCC Quiescent VCC supply current -- 150 270 IIN+ Logic "1" input bias current -- 3 10 HIN = 5 V, = 0 V IIN- Logic "0" input bias current -- -- 5 HIN = 0 V, = 5 V VCCUV+ VCC supply undervoltage positive going threshold 8 8.9 9.8 VCCUV- VCC supply undervoltage negative going threshold 7.4 8.2 9 IO+ Output high short circuit pulsed current 130 290 -- A V mA IO- www.irf.com Output low short circuit pulsed current VIN = 0 V or 5 V 270 600 -- VO = 0 V, VIN = VIH PW 10 s VO = 15 V, VIN = VIL PW 10 s 3 IRS2003(S)PbF Functional Block Diagram VB HV LEVEL SHIFT Q HO R PULSE FILTER S VS IHN PULSE GEN UV DETECT DEAD TIME & SHOOT-THROUGH PREVENTION VCC VCC LO LIN COM Lead Definitions Symbol Description HIN Logic input for high-side gate driver output (HO), in phase VB Logic input for low-side gate driver output (LO), out of phase HO High-side gate drive output VS High-side floating supply return VCC Low-side and logic fixed supply LO Low-side gate drive output COM Low-side return High-side floating supply Lead Assignments 1 VCC VB 8 1 VCC VB 8 2 HIN HO 7 2 HIN HO 7 3 LIN VS 6 3 LIN VS 6 COM LO 5 4 COM LO 5 4 www.irf.com 8 Lead PDIP 8 Lead SOIC IRS2003PbF IRS2003SPbF 4 IRS2003(S)PbF Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions Figure 3. Deadtime Waveform Definitions www.irf.com 5 1400 1400 1200 1200 Turn-On Delay Time (ns) Turn-On Delay Time (ns) IRS2003(S)PbF 1000 M a x. 800 600 Typ . 400 200 800 Typ. 600 400 200 0 0 -50 -25 0 25 50 75 Temperature (oC) 100 10 125 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 4A. Turn-On Time vs. Temperature Figure 4B. Turn-On Time vs. Supply Voltage 500 Turn-Off Delay Time (ns) 1000 Max. Turn-On Delay Time (ns) Max. 1000 800 600 Typ. 400 200 400 300 200 100 M a x. Typ. 0 0 0 2 4 6 8 10 12 14 16 18 -5 0 20 -2 5 0 25 50 75 100 125 Temperature (oC) Input Voltage (V) Figure 4C. Turn-On Time vs. Input Voltage 1000 Turn-Off Time(ns) (ns) Turn-OffDelay Delay Time Turn-Off Delay Time (ns) 500 400 300 M a x. 200 100 Figure 5A. Turn-Off Time vs. Temperature Typ . 0 800 600 Max . 400 200 Typ. 0 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 VBIAS Supply Voltage (V) Input Voltage (V) Figure 5B. Turn-Off Time vs. Supply Voltage www.irf.com Figure 5C. Turn-Off Time vs. Input Voltage 6 IRS2003(S)PbF 500 500 Turn-On Rise Time (ns) Turn-On Rise Time (ns) 500 400 300 200 Max. 100 Typ. 0 -50 -25 400 400 300 300 M ax. Max. 200 200 100 100 Typ. Typ. 00 0 25 50 75 100 125 110 0 112 2 o Temperature ( C) 116 6 118 8 220 0 VBIAS Supply Voltage (V) Figure 6A. Turn-On Rise Time vs. Temperature Figure 6B. Turn-On Rise Time vs. Voltage 200 Turn-Off Fall Time (ns) 200 Turn-Off Fall Time (ns) 114 4 150 100 Max. 50 150 Max. 100 50 Typ. Typ. 0 -50 -25 0 25 50 75 100 0 125 10 12 14 16 18 20 o Temperature ( C) Input Voltage (V) Figure 7B. Turn-Off Fall Time vs. Voltage 1400 1400 1200 1200 1000 800 Deadtime (ns) Deadtime (ns) Figure 7A. Turn-Off Fall Time vs. Temperature M a x. 600 T yp. 400 200 1000 Max. 800 600 Typ . 400 Min . M in . 200 0 0 -5 0 -2 5 0 25 50 75 100 Temperature (oC) Figure 8A. Deadtime vs. Temperature www.irf.com 125 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 8B. Deadtime vs. Voltage 7 IRS2003(S)PbF 5 Input (V)(V) InputVoltage Voltage Input Voltage (V) 5 4 3 Mi n. 2 1 -50 4 3 Mi n. 2 1 -25 0 25 50 75 100 125 10 12 Temperature (oC) 4 4 3.2 3.2 Input Voltage (V) Input Voltage (V) 18 20 Figure 9B. Logic "1" Input Voltage vs. Supply Voltage 2.4 1.6 Max. 2.4 1.6 Max. 0.8 0.8 0 -50 0 -25 0 25 50 75 100 125 10 12 Temperature (oC) Figure 10A. Logic "0"(HIN) & Logic "1" (LIN ) Input Voltage vs. Temperature High Level Output Voltage (V) 0.4 0.3 Max. 0.1 Typ. 0.0 -50 -25 0 25 50 75 100 Temperature ( oC) Figure 11A. High Level Output Voltage vs. Temperature 125 14 16 Vcc Supply Voltage (V) 18 20 Figure 10B. Logic "0"(HIN) & Logic "1" ( LIN ) Input Voltage vs. Voltage 0.5 High Level Output Voltage (V) 16 VBIAS Supply Voltage (V) Figure 9A. Logic "1" Input Voltage vs. Temperature 0.2 14 0.5 0.4 0.3 Max. 0.2 0.1 Typ. 0.0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 11B. High Level Output Voltage vs. Supply Voltage www.irf.com PDF created with pdfFactory trial version www.pdffactory.com 8 IRS2003(S)PbF 0.4 0.3 0.2 0.1 0.5 Low Level Output Voltage (V) Low Level Output Voltage (V) 0.5 Max. Typ. 0.4 0.3 0.2 Max. 0.1 Typ. 0.0 0 -50 -25 0 25 50 75 100 125 10 12 o Temperature ( C) 300 200 M a x. 0 0 25 50 75 100 125 Offset Supply Leakge Current (A) Offset Supply Leakge Current (A) 400 -2 5 20 500 400 300 200 Max. 100 0 0 200 Temperature (oC) 400 600 800 VB Boost Voltage (V) Figure 13A. Offset Supply Current vs. Temperature Figure 13B. Offset Supply Current vs. Voltage 150 150 VBS Supply Current (A) VBS Supply Current (A) 18 Figure 12B. Low Level Output Voltage vs. Supply Voltage 500 -5 0 16 V BIAS Supply Voltage (V) Figure 12A. Low Level Output Voltage vs. Temperature 100 14 120 90 60 M ax. 30 120 90 60 Max. 30 Typ. Ty p. 0 0 -5 0 -2 5 0 25 50 75 Temperature (oC) Figure 14A. VBS Supply Current vs. Temperature www.irf.com 100 125 10 12 14 16 18 20 VBS Floating Supply Voltage (V) Figure 14B. VBS Supply Current vs. Voltage 9 IRS2003(S)PbF 700 VCC Supply Current (A) VCC Supply Current (A) 700 600 500 400 Max. 300 200 100 Typ. 0 -50 600 500 400 200 100 Typ. 0 -25 0 25 50 Temperature (oC) 75 100 125 10 Figure 15A. Vcc Supply Current vs. Temperature 12 Logic "1" Input Current (A) 25 20 15 Max. 10 Max 5 Typ. 25 20 15 Max. 10 5 -25 0 25 50 75 100 Typ. 10 125 12 Logic "0" Input Bias Current (A) Max 4 3 2 1 0 0 25 50 75 100 Temperatur e ( C) FFigure ig u r e 1 7 A . LLogic o g ic ""0" 0 " IInput n p u t Bias B i a s Current C urr en t 17A. vs. Temperature www.irf.com 16 18 20 Figure 16B. Logic "1" Input Current vs. Voltage 6 -25 14 Vcc Supply Voltage (V) Figure 16A. Logic "1" Input Current vs. Temperature Logic "0" Input Bias Current (A) 20 30 Temperature (oC) -50 18 0 0 -50 5 14 16 Vcc Supply Voltage (V) Figure 15B. Vcc Supply Current vs. Voltage 30 Logic "1" Input Current (A) Max. 300 125 6 5 Max 4 3 2 1 0 10 12 14 16 18 20 Supply V oltage (V ) Figure 17B. Logic "0" Input Bias Current vs. Voltage 10 IRS2003(S)PbF 11 11 Vcc UVLO Threshold -(V) Vcc UVLO Threshold +(V) Max. 10 Typ . Typ. 9 Min. 8 7 6 -5 0 -2 5 0 25 50 75 100 10 Max. 9 Typ. Typ. 8 7 Min. 6 -50 125 -25 0 Temperature (oC) Figure 18A. Vcc Undervoltage Threshold(+) vs. Temperature 100 125 500 Output Source Current (mA) Output Source Current (mA) 75 Figure 18B. Vcc UndervoltageThreshold (-) vs. Temperature 500 400 Typ. 300 200 Min. 100 0 400 300 200 Typ. 100 Min. 0 -50 -25 0 25 50 75 100 125 10 12 o Temperature ( C) 14 16 18 20 V BIAS Supply Voltage (V) Figure 19A. Output Source Current vs. Temperature Figure 19B. Output Source Current vs. Supply Voltage 1000 800 Output Sink Current (mA) 1000 Output Sink Current (mA) 25 50 Temperature (oC) Typ. 600 400 200 Min. 800 600 400 Typ. 200 Min. 0 0 -50 -25 0 25 50 75 100 o Temperature ( C) Figure 20A. Output Sink Current vs. Temperature www.irf.com 125 10 12 14 16 18 20 S VBIAS Supply Voltage (V)( ) Figure 20B. Output Sink Current vs. Supply Voltage 11 IRS2003(S)PbF Case Outlines 01-6014 01-3003 01 (MS-001AB) 8-Lead PDIP D DIM B 5 A FOOTPRINT 8 6 7 6 5 H E 1 6X 2 3 0.25 [.010] 4 A e 6.46 [.255] 3X 1.27 [.050] e1 0.25 [.010] A1 .0688 1.35 1.75 A1 .0040 .0098 0.10 0.25 b .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 .1574 3.80 4.00 E .1497 e .050 BASIC e1 MAX 1.27 BASIC .025 BASIC 0.635 BASIC H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0 8 0 8 y 0.10 [.004] 8X L 8X c 7 C A B NOTES: 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 2. CONTROLLING DIMENSION: MILLIMETER 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA. 8-Lead SOIC www.irf.com MIN .0532 K x 45 A C 8X b 8X 1.78 [.070] MILLIMETERS MAX A 8X 0.72 [.028] INCHES MIN 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. 01-6027 01-0021 11 (MS-012AA) 12 IRS2003(S)PbF Tape & Reel 8-lead SOIC LOADED TAPE FEED DIRECTION A B H D F C N OT E : CO NTROLLING D IM ENSION IN MM E G CA R R I E R T A P E D IM E N S I O N F O R 8 S O I CN M etr ic Co d e A B C D E F G H M in 7 .9 0 3 .9 0 11 .7 0 5 .4 5 6 .3 0 5 .1 0 1 .5 0 1 .5 0 M ax 8.1 0 4.1 0 1 2. 30 5.5 5 6.5 0 5.3 0 n/ a 1.6 0 Im p er i al M in M ax 0. 31 1 0 .3 18 0. 15 3 0 .1 61 0 .4 6 0 .4 84 0. 21 4 0 .2 18 0. 24 8 0 .2 55 0. 20 0 0 .2 08 0. 05 9 n/ a 0. 05 9 0 .0 62 F D C B A E G H RE E L D IM E NS I O N S FO R 8 S O IC N Co d e A B C D E F G H www.irf.com M etr ic M in M ax 32 9. 60 3 30 .2 5 20 .9 5 2 1. 45 12 .8 0 1 3. 20 1 .9 5 2.4 5 98 .0 0 1 02 .0 0 n /a 1 8. 40 14 .5 0 1 7. 10 12 .4 0 1 4. 40 Im p er i al M in M ax 1 2 .9 76 13 .0 0 1 0. 82 4 0 .8 44 0. 50 3 0 .5 19 0. 76 7 0 .0 96 3. 85 8 4 .0 15 n /a 0 .7 24 0. 57 0 0 .6 73 0. 48 8 0 .5 66 13 IRS2003(S)PbF LEADFREE PART MARKING INFORMATION Part number Date code IRSxxxxx YWW? IR logo ?XXXX Pin 1 Identifier ? MARKING CODE P Lead Free Released Non-Lead Free Released Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 200-002 ORDER INFORMATION 8-Lead PDIP IRS2003PbF 8-Lead SOIC IRS2003SPbF 8-Lead SOIC Tape & Reel IRS2003STRPbF The SOIC-8 is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 11/27/2006 www.irf.com 14