1
©2002 Integrated Device Technology, Inc.
JANUARY 2002
DSC 3190/8
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
13L
A
0L
3190 drw 01
I/O
0L
-I/O
8L
CE
L
OE
L
R/W
L
SEM
L
INT
L
M/S
BUSY
R
A
13R
A
0R
SEM
R
INT
R
CE
R
OE
R
(2)
(1,2)
(2)
R/W
R
CE
R
OE
R
R/W
R
14
14
I/O
0R
-I/O
8R
(1,2)
Functional Block Diagram
◆IDT7016 easily expands data bus width to 18 bits or more
using the Master/Slave select when cascading more than
one device
◆M/S = V IH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
◆Busy and Interrupt Flag
◆On-chip port arbitration logic
◆Full on-chip hardware support of semaphore signaling
between ports
◆Fully asynchronous operation from either port
◆TTL-compatible, single 5V (±10%) power supply
◆Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-
pin TQFP
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Features
◆True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆High-speed access
– Commercial:12/15/20/25/35ns (max.)
– Industrial: 20ns (max.)
– Military: 20/25/35ns (max.)
◆Low-power operation
– IDT7016S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7016L
Active: 750mW (typ.)
Standby: 1mW (typ.)
HIGH-SPEED
16K X 9 DUAL-PORT
STATIC RAM
IDT7016S/L
NOTES:
1. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
2
3190 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
987 65432168676665
27 28 29 30 31 32 33 34 35 36 37 38 39
V
CC
V
CC
I/O
1R
I/O
2R
I/O
3R
I/O
4R
INT
L
GND
A
4L
A
3L
A
2L
A
1L
A
0L
A
3R
A
0R
A
1R
A
2R
I/O
2L
A
5L
11
10
M/S
23
24
25
26
40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O
3L
GND
I/O
0R
V
CC
A
4R
BUSY
L
GND
BUSY
R
INT
R
A
12R
I/O
7R
I/O
8R
GND
OE
R
R/W
R
SEM
R
CE
R
OE
L
CE
L
I/O
8L
I/O
0L
I/O
1L
IDT7016J
J68-1(4)
68-Pin PLCC
Top View(5)
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
5R
I/O
6R
N/C
A
12L
N/C
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
13R
SEM
L
R/W
L
A
13L
,
11/19/01
Description
The IDT7016 is a high-speed 16K x 9 Dual-Port Static RAM. The
IDT7016 is designed to be used as stand-alone Dual-Port RAMs or as
a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more wider
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power.
The IDT7016 is packaged in a ceramic 68-pin PGA, a 64-pin PLCC
and an 80-pinTQFP (Thin Quad Flatpack). Military grade product is
manufactured in compliance with the latest revision of MIL-PRF-38535
QML, making it ideally suited to military temperature applications demand-
ing the highest level of performance and reliability.
Pin Configurations(1,2,3)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not imply orientation of Part-marking.
Pin Names (7016)
Left P or t Ri ght Port Names
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Re ad /Write Enab le
OE
L
OE
R
Outp ut E nab le
A
0L
- A
13L
A
0R
- A
13R
Address
I/O
0L
- I/ O
8L
I/O
0R
- I/ O
8R
Data Inp ut/ Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Inte rrup t Flag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Select
V
CC
Power
GND Ground
3190 tbl 01
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
3
Pin Configurations(1,2,3)
(con't.)
INDEX
IDT7016PF
PN80-1(4)
80-Pin TQFP
Top View(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
58
57
56
55
54
53
52
51
50
49
48
47
46
59
60
45
65
66
67
68
79
78
77
76
75
74
73
72
71
70
69
80
I/O
2L
GND
GND
A
4R
BUSY
L
BUSY
R
INT
R
INT
L
GND
M/S
OE
L
NC
R/W
L
CE
L
SEM
L
V
CC
NC
OE
R
CE
R
R/W
R
SEM
R
GND
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
8R
A
12R
A
11R
A
10R
A
9R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
I/O
0L
17
18
19
20
I/O
6R
I/O
7R
NC
V
CC
23
24
36
35
34
33
32
31
30
29
28
27
26
25
40
39
38
37
A
8R
A
7R
A
6R
NC
44
43
42
41 NC
A
5L
NC
61
62
63
64
I/O
8L
I/O
1L
3190 drw 03
NC
NC
NC
NC
NC
A
5R
NC
NC
NC
21
22
A
13L
A
13R
11/19/01
3190 drw 04
51 50 48 46 44 42 40 38 36
53
55
57
59
61
63
65
67
68
66
1357911 13 15
20
22
24
26
28
30
32
35
ABCDEFGH JKL
47 45 43 41 34
21
23
25
27
29
31
33
246810121416
18 19
17
56
58
60
62
64
11
10
09
08
07
06
05
04
03
02
01
52
54
49 39 37
A
5L
INT
L
N/C
SEM
L
CE
L
V
CC
OE
L
R/W
L
I/O
0L
I/O
8L
GND GND
I/O
0R
V
CC
I/O
8R
OE
R
R/W
R
SEM
R
CE
R
GND BUSY
R
BUSY
L
M/SINT
R
N/C
GND
A
1R
INDEX
A
4L
A
2L
A
0L
A
3R
A
2R
A
4R
A
5R
A
7R
A
6R
A
9R
A
8R
A
11R
A
10R
A
12R
A
0R
A
7L
A
6L
A
3L
A
1L
A
9L
A
8L
A
11L
A
10L
A
12L
V
CC
I/O
2R
I/O
3R
I/O
5R
I/O
6R
I/O
1R
I/O
4R
I/O
7R
I/O
1L
I/O
2L
I/O
4L
I/O
7L
I/O
3L
I/O
5L
I/O
6L
A
13L
A
13R
IDT7016G
G68-1(4)
68-Pin PGA
Top View(5)
,
11/19/01
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PN80-1 package body is approximately
14mm x 14mm x 1.4mm.
G68-1 package body is approximately
1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
4
Recommended DC Operating
Conditions
Maximum Operating
Temperature and Supply Voltage(1)
Truth Table II: Semaphore Read/Write Control(1)
Absolute Maximum Ratings(1)
Truth Table I: Non-Contention Read/Write Control
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.
NOTE:
1. Condition: A0L — A13L ≠ A0R — A13R
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Inputs
(1)
Outputs
Mode
CE R/WOE SEM I/O
0-8
H X X H Hi g h-Z De s elc te d: P o we r -Down
LLXHDATA
IN
Write to Me mory
LHLHDATA
OUT
Re ad Memory
X X H X High-Z Outputs Disabled
3190 tbl 02
Inputs Outputs
Mode
CE R/WOE SEM I/O
0-8
HHLLDATA
OUT
Read Semaphore Flag Data Out (I/O
0
- I/ O
8
)
H↑XLDATA
IN
Write I/O
0
into Semaphore Flag
LXXL
____
Not Allowe d
3190 tbl 03
Symbol Rating Commercial
& Industrial Military Unit
V
TERM
(2)
Te rminal Vo l tag e
with Re sp ec t
to GND
-0. 5 to +7.0 -0.5 to +7.0 V
T
BIAS
Temperature
Unde r B ia s -55 to +125 -65 to +135 oC
T
STG
Storage
Temperature -65 to +150 -65 to +150 oC
I
OUT
DC O utp u t
Current 50 50 mA
3190 tbl 04
Grade Ambient
Temperature GND Vcc
Military -55
O
C to +125
O
C0V5.0V
+
10%
Commercial 0
O
C to + 70
O
C0V5.0V
+
10%
Industrial -40
O
C to +85
O
C0V5.0V
+
10%
3190 tbl 05
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supp ly Vol tag e 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Vo ltage 2.2
____
6.0
(2)
V
V
IL
Input Lo w Vo ltage -0.5
(1)
____
0.8 V
3190 tbl 06
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTE:
1. At Vcc < 2.0V, Input leakages are undefined.
Capacitance(1)
(TA = +25°C, f = 1.0mhz, for TQFP ONLY)
NOTES:
1. This parameter is determined by device characteristics but is not production
tested.
2 . 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V .
Output Loads and AC Test
Conditions
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, t OW)
*Including scope and jig.
3190 drw 06
893Ω
30pF
347Ω
5V
DATA
OUT
BUSY
INT
893Ω
5pF*
347Ω
5V
DATA
OUT
,
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
Outp ut Cap a ci tanc e V
OUT
= 3dV 10 pF
3190 tbl 07
Symbol Parameter Test Conditions
7016S 7016L
UnitMin. Max. Min. Max.
|I
LI
| Input Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Outp ut Le ak age Curre nt CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Outp ut Lo w Vo ltag e I
OL
= +4mA
___
0.4
___
0.4 V
V
OH
Outp ut High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
3190 t bl 0 8
Inp ut Pulse Le ve ls
Inp ut Ris e /Fal l Time s
Inp ut Timi ng Refere nc e Le ve ls
Outp ut Re fere nc e Le vels
Outp ut Lo ad
GND to 3. 0V
3ns Max.
1.5V
1.5V
Fi g ure s 1 and 2
3190 tbl 09
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)
3. At f = fMAX, address and I/Os are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5 . Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
7016X12
Com'l Only 7016X15
Com'l Only
Sym bol Parameter Test Cond ition Versio n Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynamic Op erating
Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L170
170 325
275 170
170 310
260 mA
MIL &
IND S
L
____
____
____
____
____
____
____
____
I
SB1
Standb y Current
(Bo th Po rts - TTL
Le ve l Inputs )
CE
R
= CE
L
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L25
25 70
60 25
25 60
50 mA
MIL &
IND S
L
____
____
____
____
____
____
____
____
I
SB2
Standb y Current
(O ne P o rt - TTL
Le ve l Inputs )
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L105
105 200
170 105
105 190
160 mA
MIL &
IND S
L
____
____
____
____
____
____
____
____
I
SB3
Full Standby Current
(Both Ports - All CMOS
Le ve l Inputs )
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0. 2V o r
V
IN
< 0. 2 V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0. 2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
5mA
MIL &
IND S
L
____
____
____
____
____
____
____
____
I
SB4
Full Standby Current
(One Po rt - All CMOS
Le ve l Inputs )
CE
"A"
< 0. 2V a nd
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
= SEM
L
> V
CC
- 0. 2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L S
L100
100 180
150 100
100 170
140 mA
MIL &
IND S
L
____
____
____
____
____
____
____
____
3190 tbl 10
7016X20
Com'l, I nd
& Mi litary
7016X25
Co m' l &
Military
7016X35
Com'l &
Military
Sym bol Param eter Test Cond iti on V ersion Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynamic Op erating Curre nt
(Both Ports Active) CE = V
IL
, Outp uts Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L160
160 290
240 155
155 265
220 150
150 250
210 mA
MIL &
IND S
L160
160 380
310 155
155 340
280 150
150 300
250
I
SB1
Standb y Current
(B oth P o rts - TTL
Leve l Inp uts )
CE
R
= CE
L
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L20
20 60
50 16
16 60
50 13
13 60
50 mA
MIL &
IND S
L20
20 80
65 16
16 80
65 13
13 80
65
I
SB2
Standb y Current
(O ne P ort - TTL
Leve l Inp uts )
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outp uts Disable d,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L95
95 180
150 90
90 170
140 85
85 155
130 mA
MIL &
IND S
L95
95 240
210 90
90 215
180 85
85 190
160
I
SB3
Full Standby Current
(B o th Ports - Al l CM OS
Leve l Inp uts )
Bo th Ports CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0. 2V o r
V
IN
< 0. 2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
51.0
0.2 15
5mA
MIL &
IND S
L1.0
0.2 30
10 1.0
0.2 30
10 1.0
0.2 30
10
I
SB4
Full Standby Current
(O ne P ort - A ll CMOS Le v e l
Inputs)
CE
"A"
< 0. 2V and
CE
"B"
> V
CC
- 0. 2V
(5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0. 2V o r V
IN
< 0.2V
Active Port Outp uts Disable d
f = f
MAX
(3)
COM'L S
L90
90 155
130 85
85 145
120 80
80 135
110 mA
MIL &
IND S
L90
90 230
200 85
85 200
170 80
80 175
150
3 190 tb l 1
1
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
7
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
7016X12
Com'l Only 7016X15
Co m'l On l y
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 12
____
15
____
ns
t
AA
Address Access Time
____
12
____
15 ns
t
ACE
Chip Enab le Access Time
(3)
____
12
____
15 ns
t
AOE
Outp ut Enab le Acc e ss Time
____
8
____
10 ns
t
OH
Outp ut Hold fro m Ad dre ss Chang e 3
____
3
____
ns
t
LZ
O ut p u t L o w -Z Ti m e
(1,2)
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10 ns
t
PU
Chip Enab le to Power Up Time
(2)
0
____
0
____
ns
t
PD
Chi p Dis ab le to Po wer Down Time
(2)
____
12
____
15 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
ns
t
SAA
Semaphore Address Access Time
____
12
____
15 ns
3 190 tbl 12 a
7016X20
Com'l, Ind
& Military
7016X25
Com 'l &
Military
7016X35
Co m ' l &
Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Re ad Cycle Time 20
____
25
____
35
____
ns
t
AA
Address Access Time
____
20
____
25
____
35 ns
t
ACE
Chip Enab le Access Time
(3)
____
20
____
25
____
35 ns
t
AOE
Outp ut Enab le Acc e ss Time
____
12
____
13
____
20 ns
t
OH
Outp ut Hold fro m Ad dre s s Chang e 3
____
3
____
3
____
ns
t
LZ
O ut p u t Low -Z Ti m e
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
20 ns
t
PU
Chip Enab le to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chi p Dis ab le to Po we r Down Time
(2)
____
20
____
25
____
35 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
10
____
ns
t
SAA
Semaphore Address Access Time
____
20
____
25
____
35 ns
3190 tbl 12b
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
8
t
RC
R/W
CE
ADDR
t
AA
OE
3190 drw 07
(4)
t
ACE
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up / Power-Down
CE
3190 drw 08
t
PU
I
CC
I
SB
t
PD
50% 50%
,
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
9
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4 . The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
Symbol Parameter
7016X12
Com'l Only 7016X15
Co m'l On l y
UnitMin. Max. Min. Max.
WR I T E CYCL E
t
WC
Wri te Cy c le Time 12
____
15
____
ns
t
EW
Chip Enab le to End -o f-Write
(3)
10
____
12
____
ns
t
AW
Address Valid to End-of-Write 10
____
12
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
ns
t
WP
Write Pulse Width 10
____
12
____
ns
t
WR
Write Recovery Time 2
____
2
____
ns
t
DW
Data Valid to End-of-Write 10
____
10
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10 ns
t
DH
Data Ho l d Ti m e
(4)
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
10 ns
t
OW
Outp ut Activ e from E nd -of-Write
(1,2,4)
3
____
3
____
ns
t
SWRD
SEM Flag Write to Read Time 5
____
5
____
ns
t
SPS
SEM Flag Co nte ntion Wind ow 5
____
5
____
ns
3 190 tb l 13 a
Symbol Parameter
7016X20
Com'l, Ind
& Military
7016X25
Com 'l &
Military
7016X35
Co m ' l &
Military
UnitMin. Max. Min. Max. Min. Max.
WR I T E CYCL E
t
WC
Wri te Cy c le Time 20
____
25
____
35
____
ns
t
EW
Chip Enab le to End -o f-Write
(3)
15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 15
____
20
____
25
____
ns
t
WR
Write Recovery Time 2
____
2
____
2
____
ns
t
DW
Data Valid to End-of-Write 15
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
20 ns
t
DH
Data Ho l d Ti m e
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
12
____
15
____
20 ns
t
OW
Outp ut Activ e from E nd -of-Write
(1,2,4)
3
____
3
____
3
____
ns
t
SWRD
SEM Flag Write to Read Time 5
____
5
____
5
____
ns
t
SPS
SEM Flag Co nte ntion Wind ow 5
____
5
____
5
____
ns
3190 tbl 13b
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
10
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE or SEM
(6)
(4) (4)
(3)
3190 drw 09
(7)
(9)
(7)
t
LZ
3190 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
CE or SEM
R/W
t
AW
t
EW
(3)
(2)
(6)
(9)
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
NOTES:
1. DOR = DOL =VIH, CER = CEL =VIH.
2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
Timing Waveform of Semaphore Write Condition(1,3,4)
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.
SEM
3190 drw 11
t
AW
t
SOP
I/O
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID DATA
OUT
t
DW
t
DH
t
AS
t
AOE
Read Cycle
Write Cycle
A
0
-A
2
OE
VALID
(2)
t
SWRD
t
EW
t
WP
SEM
"A"
3190 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
SIDE "B"
(2)
A
0"B"
-A
2"B"
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
7016X12
Com'l Only 7016X15
Com'l Only
Symbol Parameter Min. Max. Min. Max. Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
12
____
15 ns
t
BDA
BUSY Dis ab le Time fro m A d dre ss Not Matc he d
____
12
____
15 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
12
____
15 ns
t
BDC
BUSY Dis able Ti me from Chip Enab le Hig h
____
12
____
15 ns
t
APS
Arb itration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
15
____
18 ns
t
WH
Write Ho ld After BUSY
(5)
11
____
13
____
ns
BUSY INPUT TIMING (M/S = V
IL
)
t
WB
BUSY In p ut to W ri te
(4)
0
____
0
____
ns
t
WH
Write Ho ld After BUSY
(5)
11
____
13
____
ns
PORT-TO-PORT DELAY T IMING
t
WDD
Write Pulse to Data De lay
(1)
____
25
____
30 ns
t
DDD
Write Data Valid to Read Data De lay
(1)
____
20
____
25 ns
3 190 tbl 14 a
7016X20
Com'l, Ind
& Mi li tary
7016X25
Com 'l &
Military
7016X35
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
20
____
20
____
20 ns
t
BDA
BUSY Dis ab le Time fro m A d dre ss Not Matc he d
____
20
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
20
____
20
____
20 ns
t
BDC
BUSY Dis able Ti me from Chip Enab le Hig h
____
17
____
17
____
20 ns
t
APS
Arb itration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
30
____
30
____
35 ns
t
WH
Write Ho ld After BUSY
(5)
15
____
17
____
25
____
ns
BUSY INPUT TIMING (M/S = V
IL
)
t
WB
BUSY In p ut to W ri te
(4)
0
____
0
____
0
____
ns
t
WH
Write Ho ld After BUSY
(5)
15
____
17
____
25
____
ns
PORT-TO-PORT DELAY T IMING
t
WDD
Write Pulse to Data De lay
(1)
____
45
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data De lay
(1)
____
30
____
35
____
45 ns
3190 tbl 14b
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
13
3190 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
Timing Waveform of Write with BUSY(3)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL.
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
3190 drw 14
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
14
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
3190 drw 15
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
3190 drw 16
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
7016X12
Com'l Only 7016X15
Com'l Only
Symbol Parameter Min.Max.Min.Max.Unit
INTERRUP T TIMING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Rec ove ry Time 0
____
0
____
ns
t
INS
Inte rrupt Set Time
____
12
____
15 ns
t
INR
Inte rrupt Re se t Time
____
12
____
15 ns
3 190 tb l 15 a
7016X20
Com'l, Ind
& Military
7016X25
Com'l &
Military
7016X35
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
INTERRUP T TIMING
t
AS
Address Set-up Time 0 ____ 0____ 0____ ns
t
WR
Write Recove ry Time 0 ____ 0____ 0____ ns
t
INS
Inte rrupt Set Time ____ 20 ____ 20 ____ 25 ns
t
INR
Inte rrupt Re se t Time ____ 20 ____ 20 ____ 25 ns
3190 tbl 15b
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
15
Waveform of Interrupt Timing(1)
Truth Table III — Interrupt Flag(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2 . See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
3190 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
3190 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
Left P ort Ri ght P ort
FunctionR/W
L
CE
L
OE
L
A
13L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
13R
-A
0R
INT
R
L L X3FFFXXXX X L
(2)
S e t Ri g h t INT
R
Flag
XXXXXXLL3FFF H
(3)
Re s et R ig ht INT
R
Fl ag
XXX X L
(3)
L L X 3F FE X S e t L e ft INT
L
Flag
XLL3FFE H
(2)
X X X X X Res et L e ft INT
L
Flag
3190 tb l 16
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
16
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7016 are
push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2 . "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7016.
2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.
e. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table.
where a write is defined as the CE = R/W = VIL per Truth Table III. The
left port clears the interrupt by an address location 3FFE access when CER
=OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag
(INTR) is asserted when the left port writes to memory location 3FFF and
to clear the interrupt flag (INTR), the right port must access memory
location 3FFF. The message (9 bits) at 3FFE or 3FFF is user-defined
since it is in an addressable SRAM location. If the interrupt function is not
used, address locations 3FFE and 3FFF are not used as mail boxes but
are still part of the random access memory. Refer to Truth Table III for the
interrupt operation.
Functional Description
The IDT7016 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7016 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 3FFE
Inputs Outputs
Function
CE
L
CE
R
A
OL
-A
13L
A
OR
-A
13R
BUSY
L
(1)
BUSY
R
(1)
X X NO MATCH H H No rmal
H X MATCH H H Normal
X H MATCH H H Normal
L L MATCH (2) (2) Write Inhib it
(3)
3190 tbl 17
Functions D
0
- D
8
Left D
0
- D
8
Ri ght Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Rig ht Port Writes "0" to Se map hore 0 1 No chang e. Rig ht sid e has no write acce ss to se maphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
3190 tbl 18
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7016 RAMs.
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
Systems which can best use the IDT7016 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT7016's hardware semaphores,
which provide a lockout mechanism without requiring complex program-
ming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7016 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7016 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion Busy Logic
Master/Slave Arrays
When expanding an IDT7016 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master use the
BUSY signal as a write inhibit signal. Thus on the IDT7016 RAM the BUSY
pin is an output if the part is used as a master (M/S pin = H), and the BUSY
pin is an input if the part used as a slave (M/S pin = L) as shown in
Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/W signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted data in the
slave.
Semaphores
The IDT7016 are extremely fast Dual-Port 16Kx9 Static RAMs with
an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
3190 drw 19
MASTER
Dual Port
RAM
BUSY (L) BUSY (R)
CE
MASTER
Dual Port
RAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
CE
BUSY (L)
BUSY (R)
DECODER
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
18
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta-
neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT7016’s Dual-Port RAM. Say the 16K x 9 RAM
was to be divided into two 8K x 9 blocks which were to be dedicated at any
one time to servicing either the left or right port. Semaphore 0 could be used
to indicate the side which would control the lower section of memory, and
Semaphore 1 could be defined as the indicator for the upper section of
memory.
To take a resource, in this example the lower 8K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 8K. Meanwhile the right processor was attempting to gain control of
the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
8K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
perform another task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7016 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out
writes from the other side is what makes semaphore flags useful in
interprocessor communications. (A thorough discussion on the use of this
feature follows shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side until the
semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during
the gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
19
semaphore flags. All eight semaphores could be used to divide the Dual-
Port RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
Figure 4. IDT7016 Semaphore Logic
D
3190 drw 20
0DQ
WRITE
D
0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ
SEMAPHORE
READ
,
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
20
Ordering Information
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
3190 drw 21
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
(1)
B
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
Military (-55°Cto+125°C)
Compliant to MIL-PRF-38535 QML
PF
G
J
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
12
15
20
25
35
Commercial Only
Commercial Only
Com'l, Ind & Military
Commercial & Military
Commercial & Military
S
L
Standard Power
Low Power
XXXXX
Device
Type
IDT
Speed in Nanoseconds
7016 144K (16K x 9) Dual-Port RAM
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
1/11/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
6/3/99 Changed drawing format
Page 1 Corrected DSC number
11/10/99: Replaced IDT logo
5/19/00: Page 4 Increased storage temperature parameter
Clarified TA parameter
Page 6 DC Electrical parameters–changed wording from open to disabled
Changed ±200mV to 0mV in notes
01/10/02: Pages 2 & 3 Added date revision for pin configurations
Pages 4, 6, 7, 9 & 12 Removed Industrial temp footnote from all tables
Pages 6, 7, 9, 12 & 14 Added Industrial temp for 20ns speed to DC and AC Electrical Characteristics
Page 20 Added Industrial temp offering to 20ns ordering information
Pages 1 & 20 Replaced TM logo with ® logo
