0.1 GHz to 33 GHz,1 dB LSB, 5-Bit,
GaAs Digital Attenuator
Data Sheet
HMC939ATCPZ-EP
Rev. 0 Document Feedback
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FEATURES
Attenuation range: 1 dB LSB steps to 31 dB
Insertion loss: 6 dB typical at 33 GHz
Attenuation accuracy: ±0.5 dB
Input linearity
0.1 dB compression (P0.1dB): 24 dBm typical
3rd-order intercept (IP3): 40 dBm typical
Power handling: 27 dBm maximum
Dual-supply operation: ±5 V
CMOS-/TTL-compatible parallel control
24-lead, 4 mm × 4 mm LFCSP package
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, electronic counter measures (ECMs)
Broadband telecommunications systems
FUNCTIONAL BLOCK DIAGRAM
PACKAGE
BASE
CIN
4P
3P
2P
1P
0P
CIN
CIN
CIN
CIN
CIN
CIN
NIC
RF2
NIC
NIC
NIC
VDD
NIC
NIC = NO I NTERNAL CONNECTION
RF1
NIC
NIC
NIC
VSS
24 23 22 21 20
7
1
2
3
4
5
6
18
17
16
15
14
13
8 9 10 11 12
DRIVER
2dB 4dB 8dB 16dB
19
GND
16267-001
Figure 1.
GENERAL DESCRIPTION
The HMC939ATCPZ-EP is a 5-bit digital attenuator with a 31 dB
attenuation control range in 1 dB steps.
The HMC939ATCPZ-EP offers optimum insertion loss,
attenuation accuracy, and input linearity over the specified
frequency range from 100 MHz to 33 GHz.
The HMC939ATCPZ-EP requires dual-supply voltages,
VDD = 5 V and VSS = −5 V, a n d provides a complementary metal
oxide semiconductor (CMOS)-/transistor to transistor level
(TTL)-compatible parallel control interface by incorporating an
on-chip driver.
The HMC939ATCPZ-EP comes in a RoHS compliant, compact,
4 mm × 4 mm LFCSP package.
Additional application and technical information can be found
in the HMC939ALP4E data sheet.
HMC939ATCPZ-EP Data Sheet
Rev. 0 | Page 2 of 8
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
Power Derating Curve ..................................................................4
ESD Caution...................................................................................4
Pin Configuration and Function Descriptions ..............................5
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Outline Dimension ............................................................................8
Ordering Guide .............................................................................8
REVISION HISTORY
10/2017—Revision 0: Initial Version
Data Sheet HMC939ATCPZ-EP
Rev. 0 | Page 3 of 8
SPECIFICATIONS
VDD = 5 V, VSS = −5 V, VPx = 0 V or VDD, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 0.1 33 GHz
INSERTION LOSS 0.1 GHz to 18 GHz 4.5 5.5 dB
18 GHz to 26.5 GHz 5.5 7.0 dB
26.5 GHz to 33 GHz 6 8 dB
ATTENUATION
Range Between minimum and maximum
attenuation states, 0.1 GHz to 33 GHz
31 dB
Step Size Between any successive attenuation
states, 0.1 GHz to 33 GHz
1 dB
Step Error Between any successive attenuation
states, 0.1 GHz to 33 GHz
0.5 dB
State Error Referenced to insertion loss state
1 dB to 15 dB attenuation states,
0.1 GHz to 33 GHz
−(0.5 + 5% of
attenuation state)
+(0.5 + 5% of
attenuation state)
dB
16 dB to 31 dB attenuation states,
0.1 GHz to 20 GHz
−(0.5 + 5% of
attenuation state)
+(0.5 + 5% of
attenuation state)
dB
16 dB to 31 dB attenuation states,
20 GHz to 33 GHz
−(0.6 + 8% of
attenuation state)
+(0.6 + 8% of
attenuation state)
dB
RETURN LOSS RF1 and RF2 pins, all attenuation
states, 0.1 GHz to 33 GHz
10 dB
RELATIVE PHASE Between minimum and maximum
attenuation states
0.1 GHz to 18 GHz 45 Degrees
18 GHz to 26.5 GHz 60 Degrees
26.5 GHz to 33 GHz 80 Degrees
SWITCHING CHARACTERISTICS Between all attenuation states
Rise and Fall Time tRISE, tFALL 10% to 90% of radio frequency (RF)
output
45 ns
On and Off Time
t
ON
, t
OFF
50% digital control input voltage
(VCTL) to 90% of RF output
60
ns
INPUT LINEARITY All attenuation states
0.1 dB Compression P0.1dB 0.1 GHz to 0.5 GHz 20 dBm
0.5 GHz to 33 GHz 24 dBm
Third-Order Intercept IP3 8 dBm per tone, 1 MHz spacing
0.1 GHz to 0.5 GHz 43 dBm
0.5 GHz to 33 GHz 40 dBm
SUPPLY CURRENT
Positive IDD 2.5 4.5 6.5 mA
Negative ISS −7.0 −5.5 −3.0 mA
DIGITAL CONTROL INPUTS P0 to P4 pins
Voltage
Low VINL 0 0.8 V
High VINH 2 5 V
Current
Low and High IINL, IINH <1 µA
HMC939ATCPZ-EP Data Sheet
Rev. 0 | Page 4 of 8
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage
Positive
7 V
Negative −7 V
Digital Control Input Voltage, VCTL VDD + 0.5 V
RF Input Power (All Attenuation States,
f = 0.1 GHz to 33 GHz, TCASE = 85°C)
27 dBm
Continuous Power Dissipation, PDISS
(T
CASE
= 85°C)1
0.453 W
(TCASE = 105°C)1 0.314 W
(TCASE = 125°C)1 0.174 W
Temperature
Junction, TJ 150°C
Case, TCASE −55°C to +125°C
Storage −65°C to +150°C
Reflow2 Moisture Sensitivity Level 3
(MSL3) Rating
260°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM) 250 V (Class 1A)
1 See Figure 2.
2 See the Ordering Guide for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type θJA θJC Unit
CP-24-221 213 143.52 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
2 The device is set to maximum attenuation state.
POWER DERATING CURVE
0
0.2
0.4
0.6
0.8
1.0
1.2
–60 –40 –20 020 40 60 80 100 120
MAXIMUM POWER DISSIPATION (W)
CASE TEMPERATURE ( °C)
16267-002
Figure 2. Maximum Power Dissipation vs. Case Temperature (TCASE)
ESD CAUTION
Data Sheet HMC939ATCPZ-EP
Rev. 0 | Page 5 of 8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HMC939ATCPZ-EP
TOP VIEW
(No t t o Scal e)
PACKAGE
BASE
NIC
P4
P3
P2
P1
P0
NIC
NIC
NIC
NIC
NIC
NIC
NIC
RF2
NIC
NIC
NIC
VDD
NIC
RF1
NIC
NIC
NIC
VSS
24 23 22 21 20 19
7
1
2
3
4
5
6
18
17
16
15
14
13
8 9 10 11 12
GND
NOTES
1. NI C = NO I NTERNAL CONNECTION
2. THE EX P OSED P AD M US T BE CONNECT E D TO GRO UND FO R
PROP E R OPE RATION.
16267-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VSS Negative Supply Voltage.
2 to 4, 6 to 13,
15 to 17, 19
NIC
Not Internally Connected. These pins are not internally connected; however, all data shown herein was
measured with these pins connected to the RF/dc ground of evaluation board.
5, 14 RF1, RF2 RF Inputs or Outputs of Attenuator. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking
capacitor is necessary when the RF line potential is equal to 0 V dc.
18 VDD Positive Supply Voltage.
20 to 24 P4 to P0 Parallel Control Voltage Inputs. These pins select the required attenuation. There is no internal pull-up or
pull-down resistor on these pins; therefore, they must always be kept at a valid logic level (VINH or VINL) and
not be left floating.
EPAD Exposed Pad. The exposed pad must be connected to ground for proper operation.
Table 5. P4 to P0 Truth Table
Digital Control Input1 Attenuation
P4 P3 P2 P1 P0 State (dB)
High
High
High
High
High
0 dB (reference)
High High High High Low 1 dB
High High High Low High 2 dB
High High Low High High 4 dB
High Low High High High 8 dB
Low High High High High 16 dB
Low Low Low Low Low 31 dB
1 Any combination of the control voltage input states shown in Table 5 provides an attenuation equal to the sum of the bits selected.
Data Sheet HMC939ATCPZ-EP
Rev. 0 | Page 7 of 8
TYPICAL PERFORMANCE CHARACTERISTICS
–16
–15
–14
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
0 5 10 15 20 25 30 35 40
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
–55°C
+25°C
+125°C
16267-006
Figure 6. Insertion Loss vs. Frequency at Various Temperatures
–55°C
+25°C
+125°C
10
15
20
25
30
35
05000 10000 15000 20000 25000 30000 35000
INPUT P0.1dB ( dBm)
FREQUENCY (MHz)
16267-007
Figure 7. Input P0.1dB vs. Frequency at Minimum Attenuation State and at
Various Temperatures
10
15
20
25
30
35
0100 200 300 400 500 600 700 800 900 1000
INPUT P0.1dB ( dBm)
FREQUENCY (MHz)
–55°C
+25°C
+125°C
16267-008
Figure 8. Input P0.1dB vs. Frequency at Minimum Attenuation State and at
Various Temperatures (Low Frequency Detail)
10
20
30
40
50
60
70
05000 10000 15000 20000 25000 30000 35000
INPUT I P 3 ( dBm)
FREQUENCY (MHz)
–55°C
–40°C
+25°C
+125°C
16267-009
Figure 9. Input IP3 vs. Frequency at Minimum Attenuation State and at
Various Temperatures
10
20
30
40
50
60
70
0100 200 300 400 500 600 700 800 900 1000
INPUT I P 3 ( dBm)
FREQUENCY (MHz)
–55°C
–40°C
+25°C
+125°C
16267-010
Figure 10. Input IP3 vs. Frequency at Minimum Attenuation State and at
Various Temperatures (Low Frequency Detail)
HMC939ATCPZ-EP Data Sheet
Rev. 0 | Page 8 of 8
OUTLINE DIMENSION
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC S TANDARDS M O-220-VG GD-8.
BO T TOM VIEW
TOP VI EW
4.10
4.00 S Q
3.90
0.90
0.85
0.80 0.05 MAX
0.02 NO M
0.203 RE F
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
712
13
18
19
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFIG URATI ON AND
FUNCT IO N DES CRI P T IO NS
SECTION OF THIS DATA SHEET.
10-04-2016-A
0.30
0.25
0.18
0.20 MI N
2.70
2.60 SQ
2.50
EXPOSED
PAD
PKG-005268
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 11. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(CP-24-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description Package Option
HMC939ATCPZ-EP-PT −55°C to +125°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-22
HMC939ATCPZ-EP-R7 −55°C to +125°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-22
1 All models are RoHS compliant devices.
2 See the Absolute Maximum Ratings section.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16267-0-10/17(0)
