LM5105SDX - National Semiconductor

LM5105

LM5105 100V Half Bridge Gate Driver with Programmable Dead-Time

Literature Number: SNVS349B

LM5105

May 26, 2011

100V Half Bridge Gate Driver with Programmable Dead-

Time

General Description

The LM5105 is a high voltage gate driver designed to drive

both the high side and low side N –Channel MOSFETs in a

synchronous buck or half bridge configuration. The floating

high-side driver is capable of working with rail voltages up to

100V. The single control input is compatible with TTL signal

levels and a single external resistor programs the switching

transition dead-time through tightly matched turn-on delay

circuits. A high voltage diode is provided to charge the high

side gate drive bootstrap capacitor. The robust level shift

technology operates at high speed while consuming low pow-

er and provides clean output transitions. Under-voltage lock-

out disables the gate driver when either the low side or the

bootstrapped high side supply voltage is below the operating

threshold. The LM5105 is offered in the thermally enhanced

10-pin LLP plastic package.

Features

■Drives both a high side and low side N-channel MOSFET

■1.8A peak gate drive current

■Bootstrap supply voltage range up to 118V DC

■Integrated bootstrap diode

■Single TTL compatible Input

■Programmable turn-on delays (Dead-time)

■Enable Input pin

■Fast turn-off propagation delays (26ns typical)

■Drives 1000pF with 15ns rise and fall time

■Supply rail under-voltage lockout

■Low power consumption

Typical Applications

■Solid State motor drives

■Half and Full Bridge power converters

Package

■LLP-10 (4 mm x 4 mm)

Simplified Block Diagram

20137502

FIGURE 1.

LM5105 100V Half Bridge Gate Driver with Programmable Dead-Time

Connection Diagram

20137501

10-Lead LLP

See NS Number SDC10A

Ordering Information

Ordering Number Package Type NSC Package Drawing Supplied As

LM5105SD LLP-10 SDC10A 1000 shipped as Tape & Reel

LM5105SDX LLP-10 SDC10A 4500 shipped as Tape & Reel

Pin Descriptions

Pin Name Description Application Information

1 VDD Positive gate drive supply Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close to the

IC as possible.

2 HB High side gate driver bootstrap

rail

Connect the positive terminal of bootstrap capacitor to the HB pin and connect

negative terminal to HS. The Bootstrap capacitor should be placed as close to

IC as possible.

3 HO High side gate driver output Connect to the gate of high side N-MOS device through a short, low inductance

path.

4 HS High side MOSFET source

connection

Connect to the negative terminal of the bootststrap capacitor and to the source

of the high side N-MOS device.

5 NC Not Connected

6 RDT Dead-time programming pin A resistor from RDT to VSS programs the turn-on delay of both the high and

low side MOSFETs. The resistor should be placed close to the IC to minimize

noise coupling from adjacent PC board traces.

7 EN Logic input for driver Disable/

Enable

TTL compatible threshold with hysteresis. LO and HO are held in the low state

when EN is low.

8 IN Logic input for gate driver TTL compatible threshold with hysteresis. The high side MOSFET is turned on

and the low side MOSFET turned off when IN is high.

9 VSS Ground return All signals are referenced to this ground.

10 LO Low side gate driver output Connect to the gate of the low side N-MOS device with a short, low inductance

path.

EP It is recommended that the exposed pad on the bottom of the package be

soldered to ground plane on the PC board to aid thermal dissipation.

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LM5105

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VDD to VSS –0.3V to +18V

HB to HS –0.3V to +18V

IN and EN to VSS –0.3V to VDD + 0.3V

LO to VSS –0.3V to VDD + 0.3V

HO to VSS HS – 0.3V to HB + 0.3V

HS to VSS (Note 6) −5V to +100V

HB to VSS 118V

RDT to VSS –0.3V to 5V

Junction Temperature +150°C

Storage Temperature Range –55°C to +150°C

ESD Rating HBM (Note 2) 2 kV

Recommended Operating

Conditions

VDD +8V to +14V

HS (Note 6) –1V to 100V

HB HS + 8V to HS + 14V

HS Slew Rate <50V/ns

Junction Temperature –40°C to +125°C

Electrical Characteristics Specifications in standard typeface are for TJ = +25°C, and those in boldface type

apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, EN =

5V. No load on LO or HO. RDT= 100kΩ(Note 4).

Symbol Parameter Conditions Min Typ Max Units

SUPPLY CURRENTS

IDD VDD Quiescent Current IN = EN = 0V 0.34 0.6 mA

IDDO VDD Operating Current f = 500 kHz 1.65 3mA

IHB Total HB Quiescent Current IN = EN = 0V 0.06 0.2 mA

IHBO Total HB Operating Current f = 500 kHz 1.3 3mA

IHBS HB to VSS Current, Quiescent HS = HB = 100V 0.05 10 µA

IHBSO HB to VSS Current, Operating f = 500 kHz 0.1 mA

INPUT IN and EN

VIL Low Level Input Voltage Threshold 0.8 1.8 V

VIH High Level Input Voltage Threshold 1.8 2.2 V

Rpd Input Pulldown Resistance Pin IN and EN 100 200 500 kΩ

DEAD-TIME CONTROLS

VRDT Nominal Voltage at RDT 2.7 33.3 V

IRDT RDT Pin Current Limit RDT = 0V 0.75 1.5 2.25 mA

UNDER VOLTAGE PROTECTION

VDDR VDD Rising Threshold 6.0 6.9 7.4 V

VDDH VDD Threshold Hysteresis 0.5 V

VHBR HB Rising Threshold 5.7 6.6 7.1 V

VHBH HB Threshold Hysteresis 0.4 V

BOOT STRAP DIODE

VDL Low-Current Forward Voltage IVDD-HB = 100 µA 0.6 0.9 V

VDH High-Current Forward Voltage IVDD-HB = 100 mA 0.85 1.1 V

RDDynamic Resistance IVDD-HB = 100 mA 0.8 1.5 Ω

LO GATE DRIVER

VOLL Low-Level Output Voltage ILO = 100 mA 0.25 0.4 V

VOHL High-Level Output Voltage ILO = –100 mA,

VOHL = VDD – VLO

0.35 0.55 V

IOHL Peak Pullup Current LO = 0V 1.8 A

IOLL Peak Pulldown Current LO = 12V 1.6 A

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LM5105

Symbol Parameter Conditions Min Typ Max Units

HO GATE DRIVER

VOLH Low-Level Output Voltage IHO = 100 mA 0.25 0.4 V

VOHH High-Level Output Voltage IHO = –100 mA,

VOHH = HB – HO 0.35 0.55 V

IOHH Peak Pullup Current HO = 0V 1.8 A

IOLH Peak Pulldown Current HO = 12V 1.6 A

THERMAL RESISTANCE

θJA Junction to Ambient (Note 3), (Note 5) 40 °C/W

Switching Characteristics Specifications in standard typeface are for TJ = +25°C, and those in boldface

type apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, No

Load on LO or HO (Note 4).

Symbol Parameter Conditions Min Typ Max Units

tLPHL Lower Turn-Off Propagation Delay 26 56 ns

tHPHL Upper Turn-Off Propagation Delay 26 56 ns

tLPLH Lower Turn-On Propagation Delay RDT = 100k 485 595 705 ns

tHPLH Upper Turn-On Propagation Delay RDT = 100k 485 595 705 ns

tLPLH Lower Turn-On Propagation Delay RDT = 10k 75 105 150 ns

tHPLH Upper Turn-On Propagation Delay RDT = 10k 75 105 150 ns

ten, tsd Enable and Shutdown propagation delay 28 ns

DT1, DT2 Dead-Time LO OFF to HO ON & HO OFF to LO ON RDT = 100k 570 ns

RDT = 10k 80 ns

MDT Dead-Time Matching RDT = 100k 50 ns

tR, tFEither Output Rise/Fall Time CL = 1000pF 15 ns

tBS Bootstrap Diode Turn-On or Turn-Off Time IF = 20 mA, IR = 200 mA 50 ns

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 2, Pin 3 and Pin 4 are rated at 500V.

Note 3: 4 layer board with Cu finished thickness 1.5/1.0/1.0/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and

power planes embedded in PCB. See Application Note AN-1187.

Note 4: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical

Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 5: The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.

Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V.

However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently.

If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must

not exceed -5V.

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LM5105

Typical Performance Characteristics

VDD Operating Current vs Frequency

20137510

Operating Current vs Temperature

20137511

Quiescent Current vs Supply Voltage

20137512

Quiescent Current vs Temperature

20137513

HB Operating Current vs Frequency

20137516

HO & LO Peak Output Current vs Output Voltage

20137517

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LM5105

Diode Forward Voltage

20137515

Undervoltage Hysteresis vs Temperature

20137518

Undervoltage Rising Threshold vs Temperature

20137519

LO & HO - High Level Output Voltage vs Temperature

20137520

LO & HO - Low Level Output Voltage vs Temperature

20137521

Input Threshold vs Temperature

20137522

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LM5105

Dead-Time vs RT Resistor Value

20137514

Dead-Time vs Temperature (RT = 10k)

20137526

Dead-Time vs Temperature (RT = 100k)

20137527

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LM5105

Timing Diagrams

20137503

FIGURE 2. LM5105 Input - Output Waveforms

20137504

FIGURE 3. LM5105 Switching Time Definitions: tLPLH, tLPHL, tHPLH, tHPHL

20137530

FIGURE 4. LM5105 Enable: tsd

20137531

FIGURE 5. LM5105 Dead-Time: DT

Operational Notes

The LM5105 is a single PWM input Gate Driver with Enable

that offers a programmable dead-time. The dead-time is set

with a resistor at the RDT pin and can be adjusted from 100ns

to 600ns. The wide dead-time programming range provides

the flexibility to optimize drive signal timing for a wide range

of MOSFETS and applications.

The RDT pin is biased at 3V and current limited to 1 mA max-

imum programming current. The time delay generator will

accommodate resistor values from 5k to 100k with a dead-

time time that is proportional to the RDT resistance. Ground-

ing the RDT pin programs the LM5105 to drive both outputs

with minimum dead-time.

STARTUP AND UVLO

Both top and bottom drivers include under-voltage lockout

(UVLO) protection circuitry which monitors the supply voltage

(VDD) and bootstrap capacitor voltage (HB – HS) indepen-

dently. The UVLO circuit inhibits each driver until sufficient

supply voltage is available to turn-on the external MOSFETs,

and the UVLO hysteresis prevents chattering during supply

voltage transitions. When the supply voltage is applied to the

VDD pin of LM5105, the top and bottom gates are held low

until VDD exceeds the UVLO threshold, typically about 6.9V.

Any UVLO condition on the bootstrap capacitor will disable

only the high side output (HO).

LAYOUT CONSIDERATIONS

The optimum performance of high and low side gate drivers

cannot be achieved without taking due considerations during

circuit board layout. Following points are emphasized.

1. A low ESR/ESL capacitor must be connected close to the

IC, and between VDD and VSS pins and between HB and

HS pins to support high peak currents being drawn from

VDD during turn-on of the external MOSFET.

2. To prevent large voltage transients at the drain of the top

MOSFET, a low ESR electrolytic capacitor must be

connected between MOSFET drain and ground (VSS).

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LM5105

3. In order to avoid large negative transients on the switch

node (HS) pin, the parasitic inductances in the source of

top MOSFET and in the drain of the bottom MOSFET

(synchronous rectifier) must be minimized.

4. Grounding considerations:

a) The first priority in designing grounding connections is

to confine the high peak currents from charging and

discharging the MOSFET gate in a minimal physical

area. This will decrease the loop inductance and

minimize noise issues on the gate terminal of the

MOSFET. The MOSFETs should be placed as close as

possible to the gate driver.

b) The second high current path includes the bootstrap

capacitor, the bootstrap diode, the local ground

referenced bypass capacitor and low side MOSFET body

diode. The bootstrap capacitor is recharged on the cycle-

by-cycle basis through the bootstrap diode from the

ground referenced VDD bypass capacitor. The recharging

occurs in a short time interval and involves high peak

current. Minimizing this loop length and area on the

circuit board is important to ensure reliable operation.

5. The resistor on the RDT pin must be placed very close

to the IC and seperated from high current paths to avoid

noise coupling to the time delay generator which could

disrupt timer operation.

POWER DISSIPATION CONSIDERATIONS

The total IC power dissipation is the sum of the gate driver

losses and the bootstrap diode losses. The gate driver losses

are related to the switching frequency (f), output load capac-

itance on LO and HO (CL), and supply voltage (VDD) and can

be roughly calculated as:

PDGATES = 2 • f • CL • VDD2

There are some additional losses in the gate drivers due to

the internal CMOS stages used to buffer the LO and HO out-

puts. The following plot shows the measured gate driver

power dissipation versus frequency and load capacitance. At

higher frequencies and load capacitance values, the power

dissipation is dominated by the power losses driving the out-

put loads and agrees well with the above equation. This plot

can be used to approximate the power losses due to the gate

drivers.

Gate Driver Power Dissipation (LO + HO)

VCC = 12V, Neglecting Diode Losses

20137505

The bootstrap diode power loss is the sum of the forward bias

power loss that occurs while charging the bootstrap capacitor

and the reverse bias power loss that occurs during reverse

recovery. Since each of these events happens once per cycle,

the diode power loss is proportional to frequency. Larger ca-

pacitive loads require more current to recharge the bootstrap

capacitor resulting in more losses. Higher input voltages

(VIN) to the half bridge result in higher reverse recovery loss-

es. The following plot was generated based on calculations

and lab measurements of the diode recovery time and current

under several operating conditions. This can be useful for ap-

proximating the diode power dissipation.

Diode Power Dissipation VIN = 80V

20137506

Diode Power Dissipation VIN = 40V

20137507

The total IC power dissipation can be estimated from the

above plots by summing the gate drive losses with the boot-

strap diode losses for the intended application. Because the

diode losses can be significant, an external diode placed in

parallel with the internal bootstrap diode (refer to Figure 6)

and can be helpful in removing power from the IC. For this to

be effective, the external diode must be placed close to the

IC to minimize series inductance and have a significantly low-

er forward voltage drop than the internal diode.

HS Transient Voltages Below Ground

The HS node will always be clamped by the body diode of the

lower external FET. In some situations, board resistances and

inductances can cause the HS node to transiently swing sev-

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LM5105

eral volts below ground. The HS node can swing below

ground provided:

1. HS must always be at a lower potential than HO. Pulling

HO more than -0.3V below HS can activate parasitic

transistors resulting in excessive current to flow from the

HB supply possibly resulting in damage to the IC. The

same relationship is true with LO and VSS. If necessary,

a Schottky diode can be placed externally between HO

and HS or LO and GND to protect the IC from this type

of transient. The diode must be placed as close to the IC

pins as possible in order to be effective.

2. HB to HS operating voltage should be 15V or less .

Hence, if the HS pin transient voltage is -5V, VDD should

be ideally limited to 10V to keep HB to HS below 15V.

3. A low ESR bypass capacitor between HB to HS as well

as VCC to VSS is essential for proper operation. The

capacitor should be located at the leads of the IC to

minimize series inductance. The peak currents from LO

and HO can be quite large. Any series inductances with

the bypass capacitor will cause voltage ringing at the

leads of the IC which must be avoided for reliable

operation.

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LM5105

20137508

FIGURE 6. LM5105 Driving MOSFETs Connected in Half-Bridge Configuration

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LM5105

Physical Dimensions inches (millimeters) unless otherwise noted

Notes: Unless otherwise specified

1. Standard lead finish to be 200 microinches/5.00 micrometers minimum tin/lead (solder) on copper.

2. Pin 1 identification to have half of full circle option.

3. No JEDEC registration as of Feb. 2000.

LLP-10 Outline Drawing

NS Package Number SDC10A

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LM5105

Notes

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LM5105

Notes

LM5105 100V Half Bridge Gate Driver with Programmable Dead-Time

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