INTEGRATED CIRCUITS DATA SHEET TDA8787A 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras Product specification Supersedes data of 2000 Nov 14 2002 Oct 25 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A FEATURES APPLICATIONS * Correlated Double Sampling (CDS), Programmable Gain Amplifier (PGA), 10-bit Analog-to-Digital Converter (ADC) and reference regulator included * Low-power, low-voltage CCD camera systems. GENERAL DESCRIPTION * Fully programmable via a 3-wire serial interface * Low power consumption of only 170 mW at 2.7 V The TDA8787A is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, a PGA, clamp loops and a low-power 10-bit ADC, together with its reference voltage regulator. * Power consumption in standby mode of 4.5 mW (typical value) The PGA gain and the ADC input clamp level are controlled via the serial interface. * Sampling frequency up to 18 MHz * PGA gain range of 36 dB (in steps of 0.1 dB) * 3.0 V operation; 2.5 to 3.6 V operation for the digital outputs An additional DAC is provided for additional system controls. Its output voltage range is 1.0 V peak-to-peak which is available at pin OFDOUT. * Active control pulses polarity selectable via serial interface * 8-bit DAC included for analog settings * TTL compatible inputs, CMOS compatible outputs. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8787AHL 2002 Oct 25 LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm 2 VERSION SOT313-2 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 2.7 3.0 3.6 V VCCD digital supply voltage 2.7 3.0 3.6 V VCCO digital outputs stages supply voltage 2.5 2.6 3.6 V ICCA analog supply current all clamps active; fpix = 18 MHz - 50 60 mA ICCD digital supply current fpix = 18 MHz - 13 17 mA ICCO digital outputs supply current fpix = 18 MHz; CL = 20 pF; input ramp response time is 800 s - 1 2 mA ADCres ADC resolution Vi(CDS)(p-p) CDS input amplitude (video signal) (peak-to-peak value) - 10 - bits VCC = 2.85 V 650 - - mV VCC 3.0 V 800 - - mV fpix(max) maximum pixel frequency 18 - - MHz fpix(min) minimum pixel frequency 2 - - MHz DRPGA PGA dynamic range - 36 - dB Ntot(rms) total noise (RMS value) at CDS input to ADC output PGA code = 0; see Fig.8 - 0.15 - LSB Vn(i)(eq)(rms) equivalent input noise voltage (RMS value) PGA code = 383 - 70 - V Ptot total power consumption VCCA = VCCD = VCCO = 3 V - 190 - mW VCCA = VCCD = VCCO = 2.7 V - 170 - mW 2002 Oct 25 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 48 1 DGND3 VCCA2 2 18 AGND2 CLPOB CLPDM 17 13 AGND5 12 CLK BLK 43 40 11 OE 37 20 19 CDS CLOCK GENERATOR 39 38 26 CPCDS1 7 CLAMP CPCDS2 VCCA3 AGND3 IN TDA8787AHL 36 8 35 42 34 41 CORRELATED DOUBLE SAMPLING 4 33 10-bit ADC PGA 32 SHIFT BLANKING SHIFTER LATCH OUTPUT BUFFER 31 30 29 4 28 27 VCCA1 AGND1 input clamp 6 DAC Vref 5 9-BIT REGISTER 7-BIT REGISTER 8-BIT REGISTER SERIAL INTERFACE 25 DGND1 VCCD1 DGND2 VCCD2 OGND D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Philips Semiconductors 47 VCCD3 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras SHD BLOCK DIAGRAM dbook, full pagewidth 2002 Oct 25 SHP VCCO OFD DAC OFDOUT 9 14 15 16 3 45 46 OPGA OPGAC 23 22 21 REGULATOR 24 44 DCLPC 10 FCE330 TEST1 TEST2 TEST3 AGND4 SCLK SDATA VSYNC STDBY Product specification TDA8787A Fig.1 Block diagram. SEN Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A PINNING SYMBOL PIN DESCRIPTION VCCD3 1 digital supply voltage 3 DGND3 2 digital ground 3 AGND4 3 analog ground 4 IN 4 input signal from CCD AGND1 5 analog ground 1 VCCA1 6 analog supply voltage 1 CPCDS1 7 clamp storage capacitor 1 CPCDS2 8 clamp storage capacitor 2 OFDOUT 9 analog output of the additional 8-bit control DAC STDBY 10 standby mode control input (LOW: TDA8787A active; HIGH: TDA8787A standby) BLK 11 blanking control input CLPDM 12 clamp pulse input at dummy pixel (should be connected to ground) CLPOB 13 clamp pulse input for optical black TEST1 14 test pin input 1 (should be connected to AGND2) TEST2 15 test pin input 2 (should be connected to AGND2) TEST3 16 test pin input 3 (should be connected to AGND2) AGND2 17 analog ground 2 VCCA2 18 analog supply voltage 2 VCCD1 19 digital supply voltage 1 DGND1 20 digital ground 1 SDATA 21 serial data input for serial interface control SCLK 22 serial clock input for serial interface control SEN 23 strobe pin for serial interface control VSYNC 24 vertical sync pulse input VCCO 25 output stages supply voltage OGND 26 digital output ground D0 27 ADC digital output 0 (LSB) D1 28 ADC digital output 1 D2 29 ADC digital output 2 D3 30 ADC digital output 3 D4 31 ADC digital output 4 D5 32 ADC digital output 5 D6 33 ADC digital output 6 D7 34 ADC digital output 7 D8 35 ADC digital output 8 D9 36 ADC digital output 9 (MSB) OE 37 output enable control input (LOW: outputs active; HIGH: outputs in high impedance) VCCD2 38 digital supply 2 DGND2 39 digital ground 2 CLK 40 data clock input 2002 Oct 25 5 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras 41 analog ground 3 PGA output (test pin) 46 PGA complementary output (test pin) SHP 47 preset sample-and-hold pulse input SHD 48 data sample-and-hold pulse input 40 CLK 45 OPGAC 41 AGND3 OPGA 42 VCCA3 regulator decoupling pin 43 AGND5 44 44 DCLPC DCLPC 45 OPGA analog ground 5 46 OPGAC analog supply 3 43 47 SHP 42 48 SHD VCCA3 AGND5 VCCD3 1 36 D9 DGND3 2 35 D8 AGND4 3 34 D7 IN 4 33 D6 AGND1 5 32 D5 VCCA1 6 CPCDS1 7 30 D3 CPCDS2 8 29 D2 OFDOUT 9 28 D1 STDBY 10 27 D0 31 D4 TDA8787AHL 6 VSYNC 24 SEN 23 SDATA 21 DGND1 20 VCCD1 19 VCCA2 18 AGND2 17 TEST2 15 TEST3 16 TEST1 14 26 OGND 25 VCCO CLPOB 13 BLK 11 CLPDM 12 Fig.2 Pin configuration. 2002 Oct 25 37 OE AGND3 38 VCCD2 DESCRIPTION 39 DGND2 PIN SCLK 22 SYMBOL TDA8787A FCE331 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 -0.3 +5.0 V VCCD digital supply voltage note 1 -0.3 +5.0 V VCCO output stages supply voltage note 1 -0.3 +5.0 V VCC supply voltage difference between VCCA and VCCD -0.5 +0.5 V between VCCA and VCCO -0.5 +1.2 V -0.5 +1.2 V -0.3 +5.0 V data output current - 10 mA Tstg storage temperature -55 +150 C Tamb ambient temperature -20 +75 C Tj junction temperature - 150 C between VCCD and VCCO Vi input voltage Io referenced to AGND Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 and +5.0 V provided that the supply voltage difference VCC remains as indicated. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2002 Oct 25 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 7 VALUE UNIT 76 K/W Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A CHARACTERISTICS VCCA = VCCD = 3.0 V; VCCO = 2.6 V; fpix = 18 MHz; Tamb = -20 to +75C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 2.7 VCCD digital supply voltage 2.7 3.0 3.6 V VCCO digital outputs stages supply voltage 2.5 2.6 3.6 V ICCA analog supply current - 50 60 mA ICCD digital supply current - 13 17 mA ICCO digital outputs supply current CL = 20 pF on all data outputs; - input ramp response time is 800 s 1 2 mA Ptot total power consumption VCCA = VCCD = VCCO = 3 V - 190 - mW VCCA = VCCD = VCCO = 2.7 V - 170 - mW all clamps active 3.0 3.6 V Digital inputs INPUTS: PINS STDBY, CLPDM, CLPOB, SCLK, SDATA, SEN, VSYNC, OE, CLK AND BLK VIL LOW-level input voltage 0 - 0.6 V VIH HIGH-level input voltage 2.2 - 5.0 V Ii input current -2 - +2 A 0 - 0.6 V 0 Vi VCCD INPUTS: PINS SHP AND SHD VIL LOW-level input voltage VIH HIGH-level input voltage Ii input current 2.2 - 5.0 V -10 - +10 A 12 - - pixels 1.5 2.7 3.5 mS - 0.27 - PGA input code = 0 - 20 - A PGA input code = 383 - 0.60 - A 0 Vi VCCD Clamps GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS tW(clamp) clamp active pulse width in numbers of pixels PGA input code = 255 for maximum 4 LSB error INPUT CLAMP: PIN CLPDM gm(CDS) CDS input clamp transconductance OPTICAL BLACK CLAMP: PIN CLPOB Gshift gain from CPCDS1 and 2 to PGA inputs ILSB(cp) charge pump current for 1 LSB error at ADC output 2002 Oct 25 8 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras SYMBOL PARAMETER TDA8787A CONDITIONS MIN. TYP. MAX. UNIT Correlated Double Sampling (CDS): pin IN Vi(CDS)(p-p) CDS input amplitude (video signal) (peak-to-peak value) VCC = 2.85 V 650 - - mV VCC 3.0 V 800 - - mV 500 - - mV -1 - +1 A - 2 - pF Vi(rst)(max) maximum CDS input reset pulse amplitude Ii input current Ci input capacitance tCDS(min) CDS control pulses minimum active time Vi(CDS)(p-p) = 800 mV; black-to-white transition in 1 pixel (2 LSB typical); Tamb = 25 C; note 1 11 15 - ns th(IN-SHP) hold time SHP to IN Tamb = 25 C; see Figs 3 and 4 - 1 2 ns th(IN-SHD) hold time SHD to IN Tamb = 25 C; see Figs 3 and 4 - 1 2 ns at floating gate level Amplifier DRPGA PGA dynamic range - 36 - dB GPGA PGA gain step -0.3 - +0.3 dB Analog-to-Digital Converter (ADC) LE(i) integral non-linearity error fpix = 18 MHz; ramp input - 1.3 2.5 LSB LE(d) differential non-linearity error fpix = 18 MHz; ramp input - 0.5 0.9 LSB Total chain characteristics (CDS, PGA and ADC) fpix(max) maximum pixel frequency 18 - - MHz fpix(min) minimum pixel frequency 2 - - MHz tCLKH clock HIGH time 15 - - ns tCLKL clock LOW time 15 - - ns td(SHD-CLK) time delay SHD to CLK 10 - - ns tsu(BLK-CLK) set-up time of BLK compared to CLK 10 - - ns Vi(IN) video input dynamic signal PGA input code = 0 for ADC full-scale output PGA input code = 383 800 - - mV 12.7 - - mV - 0.15 - LSB - 0.8 - LSB PGA input code = 383 - 70 - V PGA input code = 0 - 120 - V -80 - +80 mV Ntot(rms) Vn(i)(eq)(rms) OCCD(max) 2002 Oct 25 see Fig.3 total noise from CDS input see Fig.8 to ADC output PGA input code = 0 (RMS value) PGA input code = 96 equivalent input noise voltage (RMS value) maximum offset between CCD floating level and CCD dark pixel level 9 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras SYMBOL PARAMETER TDA8787A CONDITIONS MIN. TYP. MAX. UNIT Digital-to-Analog Converter (OFDOUT DAC) RL = 1 M VOFDOUT(p-p) additional 8-bit control DAC (OFD) output voltage (peak-to-peak value) - 1.0 - V VOFDOUT OFD input code 0 - AGND - V OFD input code 255 - AGND + 1.0 - V DC output voltage TCOFD OFD output range temperature coefficient - 250 - ppm/K ZOFDOUT OFD output impedance - 2000 - IOFDOUT OFD output drive current - - 100 A static Digital outputs (fpix = 18 MHz; CL = 10 pF); see Figs 3 and 4 VOH HIGH-level output voltage IOH = -1 mA VCCO - 0.5 - VOL LOW-level output voltage IOL = 1 mA 0 - 0.5 0.5 V < VOZ < VCCO -20 - +20 A 9 - - ns - 17 23 ns IOZ OFF-state output current th(o) output hold time td(o) output delay time CL load capacitance VCCO = 3.0 V VCCO = 2.7 V VCCO V V - 19 25 ns - - 22 pF 5 - - MHz Serial interface fSCLK(max) maximum frequency pin SCLK Note 1. Depending on application environments and especially in case of high gain operation and digital supply with jitter, it is preferable to apply 12 ns or higher CDS pulses. 2002 Oct 25 10 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A handbook, full pagewidth IN N+1 N N+2 N+3 t CDS(min) 2.2 V SHP 0.6 V 0.6 V t h(IN-SHP) t CDS(min) 2.2 V SHD 0.6 V 0.6 V 0.6 V t h(IN-SHD) t CLKH 2.2 V CLK 0.6 V 0.6 V t d(SHD-CLK) 50% DATA N-1 N t h(o) t d(o) 2.2 V FCE337 BLK 0.6 V t su(BLK-CLK) Fig.3 Pixel frequency timing diagram with active HIGH-level polarities. 2002 Oct 25 11 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A handbook, full pagewidth IN N+1 N N+2 N+3 2.2 V SHP 0.6 V 0.6 V t CDS(min) t h(IN-SHP) 2.2 V 2.2 V SHD 0.6 V 0.6 V t h(IN-SHD) t CDS(min) 2.2 V 2.2 V CLK 0.6 V t CLKL t d(SHD-CLK) 50% DATA N-1 N t h(o) t d(o) 2.2 V FCE328 BLK 0.6 V t su(BLK-CLK) Fig.4 Pixel frequency timing diagram with active LOW-level polarities. 2002 Oct 25 12 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A FCE332 handbook, full pagewidth 1.0 VOFDOUT (V) 0 255 0 OFD control DAC input code Fig.5 DAC output voltage output as a function of DAC input code. 4 pixels(1) handbook, full pagewidth CLPOB WINDOW PGA output VIDEO OPTICAL BLACK HORIZONTAL FLYBACK DUMMY VIDEO CLPOB (active HIGH) BLK (active HIGH) BLK window FCE333 (1) In this case the number of clamp pixels is limited to 18 x (tW(clamp)); otherwise this timing interval can be Fig.6 Line frequency timing diagram. 2002 Oct 25 13 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A FCE327 42 Total gain (dB) 36 30 24 18 12 6 0 0 64 128 192 256 320 383 PGA input code ADC input range is 1 Vpp. Fig.7 Total gain as a function of PGA input code. FCE329 6 handbook, halfpage Ntot(rms) (LSB) 5 4 3 2 1 0 0 64 128 192 256 320 383 PGA input code Noise measurement at ADC outputs; coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 18 Mpixels with line of 1024 pixels whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this, the standard deviation of the codes statistic is computed, resulting in the noise. Fig.8 Typical total noise performance as a function of PGA gain. 2002 Oct 25 14 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras handbook, full pagewidth SDATA TDA8787A SHIFT REGISTER SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 A0 A1 SCLK LSB MSB 10 LATCH SELECTION SEN 9 8 OFDOUT DAC LATCHES 7 PGA GAIN LATCHES ADC CLAMP LATCHES 6 CONTROL PULSE POLARITY LATCHES VSYNC FLIP-FLOP FLIP-FLOP FLIP-FLOP PGA control 8-bit DAC ADC clamp control control pulses polarity settings FCE334 Fig.9 Serial interface block diagram. t su2 handbook, full pagewidth t hd4 MSB SDATA A1 A0 SD9 SD8 SD7 SD6 LSB SD5 SD4 SD3 SD2 SD1 SD0 SCLK SEN t su1 t su3 t hd3 FCE335 tsu1 = tsu2 = tsu3 = 10 ns (minimum); thd3 = thd4 = 10 ns (minimum). Fig.10 Loading sequence of control input data via the serial interface. 2002 Oct 25 15 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras Table 1 TDA8787A Serial interface programming; see Figs 9 and 10 ADDRESS BITS DATA BITS SD9 TO SD0 A1 A0 0 0 PGA gain control (bits SD8 to SD0); bit SD9 should be set to logic 0 0 1 DAC OFDOUT output control (bits SD7 to SD0); bits SD8 and SD9 should be set to logic 0 1 0 ADC clamp reference control (SD6 to SD0); from code 0 to 127; bits SD7, SD8 and SD9 should be set to logic 0 1 1 control pulses polarity settings (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK) Table 2 Polarity settings SYMBOL PIN SERIAL CONTROL BIT(1) ACTIVE EDGE OR LEVEL SHP and SHD 47 and 48 SD0 1 = HIGH; 0 = LOW 40 SD1 1 = HIGH; 0 = LOW CLPDM 12 (connected to ground) SD2 always 0 = LOW CLPOB 13 SD3 1 = HIGH; 0 = LOW BLK 11 SD5 1 = HIGH; 0 = LOW VSYNC 24 SD6 0 = rising; 1 = falling CLK Note 1. Bit SD4 is not used. Table 3 Standby mode selection; pin STDBY STDBY ADC DIGITAL OUTPUTS; PINS D9 TO D0 ICCA + ICCO + ICCD (typical) 1 logic state LOW 1.5 mA 0 active 64 mA Table 4 Output enable (OE) pin 37 OE ADC DIGITAL OUTPUTS; PINS D9 TO D0 0 active, binary 1 high impedance 2002 Oct 25 16 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras APPLICATION INFORMATION In order to minimize the noise due to package and die parasitics in a two-ground system, the following measures must be implemented: Power and grounding recommendations When designing a printed-circuit board for applications such as PC cameras, surveillance cameras, camcorders and digital still cameras, care should be taken to minimize the noise. * All the analog and digital supply pins must be decoupled to the analog ground plane. Only the ground pin associated with the digital outputs must be connected to the digital ground plane. All the other ground pins should be connected to the analog ground plane. The analog and digital ground planes must be connected together at one point as close as possible to the ground pin associated with the digital outputs. For the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as additional operational amplifiers) must be respected, particularly with respect to power and ground connections. * The digital output pins and their associated lines should be shielded by the digital ground plane which can then be used as a return path for digital signals. The following additional recommendation is given for the CDS input pin(s) which is /are internally connected to the programmable gain amplifier. The connections between the CCD interface and CDS input should be as short as possible and a ground ring protection around these connections can be beneficial. Separate analog and digital supplies provide the best solution. If this is not possible to do this on the board then the analog supply pins must be decoupled effectively from the digital supply pins. If the same power supply and ground are used for all the pins then the decoupling capacitors must be placed as close as possible to the IC package. 2002 Oct 25 TDA8787A 17 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A Application diagram VCCA handbook, full pagewidth VCCD 100 nF 100 nF 1 F OE VCCD2 CLK DGND2 AGND3 VCCA3 AGND5 OPGA DCLPC SHD 1 F SHP CCD (2) VCCD (2) OPGAC (2) 48 47 46 45 44 43 42 41 40 39 38 37 VCCD VCCD3 1 F DGND3 AGND4 IN VCCA 100 nF AGND1 VCCA1 CPCDS1 1 F CPCDS2 OFDOUT 1 F STDBY BLK CLPDM 1 36 2 35 3 34 4 33 5 32 6 31 TDA8787AHL 7 30 8 29 9 28 10 27 11 26 12 25 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OGND VCCO 100 nF VSYNC SEN SCLK SDATA DGND1 VCCD1 VCCA2 TEST3 AGND2 TEST2 TEST1 VCCD CLPOB 13 14 15 16 17 18 19 20 21 22 23 24 VCCD (1) serial interface 100 nF 100 nF VCCA VCCD FCE336 (1) Pins SEN and VSYNC should be interconnected when no vertical synchronization signal is available, while control pin VSYNC should be programmed by serial interface as LOW-level active. (2) The timing of the signals on pins IN, SHD and SHP has to comply with the hold times th(IN-SHP) and th(IN-SHD) (see Fig.3). Fig.11 Application diagram. 2002 Oct 25 18 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M pin 1 index bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 MS-026 2002 Oct 25 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 19 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras SOLDERING TDA8787A If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. To overcome these problems the double-wave soldering method was specifically developed. 2002 Oct 25 20 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Oct 25 21 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras TDA8787A DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 Oct 25 22 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 18 Msps analog-to-digital interface for CCD cameras NOTES 2002 Oct 25 23 TDA8787A Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA74 (c) Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/04/pp24 Date of release: 2002 Oct 25 Document order number: 9397 750 10096