DATA SH EET
Product specification
Supersedes data of 2000 Nov 14 2002 Oct 25
INTEGRATED CIRCUITS
TDA8787A
10-bit, 3.0 V, up to 18 Msps
analog-to-digital interface for
CCD cameras
2002 Oct 25 2
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
FEATURES
•Correlated Double Sampling (CDS), Programmable
GainAmplifier (PGA),10-bitAnalog-to-DigitalConverter
(ADC) and reference regulator included
•Fully programmable via a 3-wire serial interface
•Sampling frequency up to 18 MHz
•PGA gain range of 36 dB (in steps of 0.1 dB)
•Low power consumption of only 170 mW at 2.7 V
•Power consumption in standby mode of 4.5 mW
(typical value)
•3.0 V operation; 2.5 to 3.6 V operation for the digital
outputs
•Active control pulses polarity selectable via serial
interface
•8-bit DAC included for analog settings
•TTL compatible inputs, CMOS compatible outputs.
APPLICATIONS
•Low-power, low-voltage CCD camera systems.
GENERAL DESCRIPTION
The TDA8787A is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, a PGA, clamp loops and a low-power
10-bit ADC, together with its reference voltage regulator.
The PGA gain and the ADC input clamp level are
controlled via the serial interface.
An additional DAC is provided for additional system
controls. Its output voltage range is 1.0 V peak-to-peak
which is available at pin OFDOUT.
ORDERING INFORMATION
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA8787AHL LQFP48 plastic low profile quad flat package; 48 leads; body 7 ×7×1.4 mm SOT313-2
2002 Oct 25 3
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCCA analog supply voltage 2.7 3.0 3.6 V
VCCD digital supply voltage 2.7 3.0 3.6 V
VCCO digital outputs stages supply
voltage 2.5 2.6 3.6 V
ICCA analog supply current all clamps active; fpix = 18 MHz −50 60 mA
ICCD digital supply current fpix =18MHz −13 17 mA
ICCO digital outputs supply current fpix = 18 MHz; CL= 20 pF; input ramp
response time is 800 µs−12mA
ADCres ADC resolution −10 −bits
Vi(CDS)(p-p) CDS input amplitude (video
signal) (peak-to-peak value) VCC = 2.85 V 650 −−mV
VCC ≥3.0 V 800 −−mV
fpix(max) maximum pixel frequency 18 −−MHz
fpix(min) minimum pixel frequency 2 −−MHz
DRPGA PGA dynamic range −36 −dB
Ntot(rms) total noise (RMS value) at
CDS input to ADC output PGA code = 0; see Fig.8 −0.15 −LSB
Vn(i)(eq)(rms) equivalent input noise
voltage (RMS value) PGA code = 383 −70 −µV
P
tot total power consumption VCCA =V
CCD =V
CCO =3V −190 −mW
VCCA =V
CCD =V
CCO = 2.7 V −170 −mW
2002 Oct 25 4
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
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BLOCK DIAGRAM
d
book, full pagewidth
FCE330
10-bit ADC
REGULATOR
CDS CLOCK GENERATOR
BLANKING OUTPUT
BUFFER
26
27
28
29
30
31
32
33
34
35
36
37
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
25 VCCO
44 DCLPC
38 VCCD2
39 DGND2
19 VCCD1
20 DGND1
41
AGND3
42
VCCA3
8
CPCDS2
7
CPCDS1
4
IN
5
AGND1
9
OFDOUT
6
VCCA1
OE
11
BLK
40
CLK
43
AGND5
17
AGND2
2
DGND3
1
VCCD3
18
VCCA2
12
CLPDM
13
CLPOB
47
SHP
SHIFTERSHIFT
CORRELATED
DOUBLE
SAMPLING
7-BIT
REGISTER
9-BIT
REGISTER
8-BIT
REGISTER
46
45
OPGA OPGAC
16
15
14 3
TEST1 AGND4
TEST2 TEST3
48
SHD
SERIAL
INTERFACE
21
22
23
SEN SCLK SDATA
24
VSYNC
10
STDBY
PGA
DAC
input
clamp
Vref
OFD DAC
LATCH
CLAMP TDA8787AHL
Fig.1 Block diagram.
2002 Oct 25 5
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
PINNING
SYMBOL PIN DESCRIPTION
VCCD3 1 digital supply voltage 3
DGND3 2 digital ground 3
AGND4 3 analog ground 4
IN 4 input signal from CCD
AGND1 5 analog ground 1
VCCA1 6 analog supply voltage 1
CPCDS1 7 clamp storage capacitor 1
CPCDS2 8 clamp storage capacitor 2
OFDOUT 9 analog output of the additional 8-bit control DAC
STDBY 10 standby mode control input (LOW: TDA8787A active; HIGH: TDA8787A standby)
BLK 11 blanking control input
CLPDM 12 clamp pulse input at dummy pixel (should be connected to ground)
CLPOB 13 clamp pulse input for optical black
TEST1 14 test pin input 1 (should be connected to AGND2)
TEST2 15 test pin input 2 (should be connected to AGND2)
TEST3 16 test pin input 3 (should be connected to AGND2)
AGND2 17 analog ground 2
VCCA2 18 analog supply voltage 2
VCCD1 19 digital supply voltage 1
DGND1 20 digital ground 1
SDATA 21 serial data input for serial interface control
SCLK 22 serial clock input for serial interface control
SEN 23 strobe pin for serial interface control
VSYNC 24 vertical sync pulse input
VCCO 25 output stages supply voltage
OGND 26 digital output ground
D0 27 ADC digital output 0 (LSB)
D1 28 ADC digital output 1
D2 29 ADC digital output 2
D3 30 ADC digital output 3
D4 31 ADC digital output 4
D5 32 ADC digital output 5
D6 33 ADC digital output 6
D7 34 ADC digital output 7
D8 35 ADC digital output 8
D9 36 ADC digital output 9 (MSB)
OE 37 output enable control input (LOW: outputs active; HIGH: outputs in high impedance)
VCCD2 38 digital supply 2
DGND2 39 digital ground 2
CLK 40 data clock input
2002 Oct 25 6
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
AGND3 41 analog ground 3
VCCA3 42 analog supply 3
AGND5 43 analog ground 5
DCLPC 44 regulator decoupling pin
OPGA 45 PGA output (test pin)
OPGAC 46 PGA complementary output (test pin)
SHP 47 preset sample-and-hold pulse input
SHD 48 data sample-and-hold pulse input
SYMBOL PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
36
35
34
33
32
31
30
29
28
27
26
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
12
24 37
25
TDA8787AHL
FCE331
D9
D8
D7
D6
D4
D3
D2
D1
D0
OGND
VCCO
VCCD3
DGND3
AGND4
IN
AGND1
VCCA1
CPCDS2
OFDOUT
BLK
CLPDM
D5
SHP
OPGAC
OPGA
DCLPC
AGND5
VCCA3
CLK
DGND2
OE
VCCD2
SHD
AGND3
CPCDS1
STDBY
TEST1
TEST2
TEST3
AGND2
VCCA2
VCCD1
DGND1
SCLK
SEN
VSYNC
CLPOB
SDATA
Fig.2 Pin configuration.
2002 Oct 25 7
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +5.0 V provided that the supply
voltage difference ∆VCC remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCCA analog supply voltage note 1 −0.3 +5.0 V
VCCD digital supply voltage note 1 −0.3 +5.0 V
VCCO output stages supply voltage note 1 −0.3 +5.0 V
∆VCC supply voltage difference
between VCCA and VCCD −0.5 +0.5 V
between VCCA and VCCO −0.5 +1.2 V
between VCCD and VCCO −0.5 +1.2 V
Viinput voltage referenced to AGND −0.3 +5.0 V
Iodata output current −±10 mA
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −20 +75 °C
Tjjunction temperature −150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air 76 K/W
2002 Oct 25 8
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
CHARACTERISTICS
VCCA =V
CCD = 3.0 V; VCCO = 2.6 V; fpix = 18 MHz; Tamb =−20 to +75°C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VCCA analog supply voltage 2.7 3.0 3.6 V
VCCD digital supply voltage 2.7 3.0 3.6 V
VCCO digital outputs stages
supply voltage 2.5 2.6 3.6 V
ICCA analog supply current all clamps active −50 60 mA
ICCD digital supply current −13 17 mA
ICCO digital outputs supply
current CL= 20 pFonalldata outputs;
input ramp response time is
800 µs
−12mA
P
tot total power consumption VCCA =V
CCD =V
CCO =3V −190 −mW
VCCA =V
CCD =V
CCO = 2.7 V −170 −mW
Digital inputs
INPUTS:PINS STDBY, CLPDM, CLPOB, SCLK, SDATA, SEN, VSYNC, OE, CLK AND BLK
VIL LOW-level input voltage 0 −0.6 V
VIH HIGH-level input voltage 2.2 −5.0 V
Iiinput current 0 ≤Vi≤VCCD −2−+2 µA
INPUTS:PINS SHP AND SHD
VIL LOW-level input voltage 0 −0.6 V
VIH HIGH-level input voltage 2.2 −5.0 V
Iiinput current 0 ≤Vi≤VCCD −10 −+10 µA
Clamps
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp) clamp active pulse width
in numbers of pixels PGA input code = 255 for
maximum 4 LSB error 12 −−pixels
INPUT CLAMP:PIN CLPDM
gm(CDS) CDS input clamp
transconductance 1.5 2.7 3.5 mS
OPTICAL BLACK CLAMP:PIN CLPOB
Gshift gain from CPCDS1 and 2
to PGA inputs −0.27 −
ILSB(cp) charge pump current for
±1 LSB error at ADC
output
PGA input code = 0 −±20 −µA
PGA input code = 383 −±0.60 −µA
2002 Oct 25 9
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
Correlated Double Sampling (CDS): pin IN
Vi(CDS)(p-p) CDS input amplitude
(video signal)
(peak-to-peak value)
VCC = 2.85 V 650 −−mV
VCC ≥3.0 V 800 −−mV
Vi(rst)(max) maximum CDS input reset
pulse amplitude 500 −−mV
Iiinput current at floating gate level −1−+1 µA
Ciinput capacitance −2−pF
tCDS(min) CDS control pulses
minimum active time Vi(CDS)(p-p) = 800 mV;
black-to-white transition in
1 pixel (±2 LSB typical);
Tamb =25°C; note 1
11 15 −ns
th(IN-SHP) hold time SHP to IN Tamb =25°C; see
Figs 3 and 4 −12ns
t
h(IN-SHD) hold time SHD to IN Tamb =25°C; see
Figs 3 and 4 −12ns
Amplifier
DRPGA PGA dynamic range −36 −dB
∆GPGA PGA gain step −0.3 −+0.3 dB
Analog-to-Digital Converter (ADC)
LE(i) integral non-linearity error fpix = 18 MHz; ramp input −±1.3 ±2.5 LSB
LE(d) differential non-linearity
error fpix = 18 MHz; ramp input −±0.5 ±0.9 LSB
Total chain characteristics (CDS, PGA and ADC)
fpix(max) maximum pixel frequency 18 −−MHz
fpix(min) minimum pixel frequency 2 −−MHz
tCLKH clock HIGH time 15 −−ns
tCLKL clock LOW time 15 −−ns
td(SHD-CLK) time delay SHD to CLK see Fig.3 10 −−ns
tsu(BLK-CLK) set-up time of
BLK compared to CLK 10 −−ns
Vi(IN) video input dynamic signal
for ADC full-scale output PGA input code = 0 800 −−mV
PGA input code = 383 12.7 −−mV
Ntot(rms) total noise from CDS input
to ADC output
(RMS value)
see Fig.8
PGA input code = 0 −0.15 −LSB
PGA input code = 96 −0.8 −LSB
Vn(i)(eq)(rms) equivalent input noise
voltage (RMS value) PGA input code = 383 −70 −µV
PGA input code = 0 −120 −µV
O
CCD(max) maximum offset between
CCD floating level and
CCD dark pixel level
−80 −+80 mV
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 Oct 25 10
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
Note
1. Depending on application environments and especially in case of high gain operation and digital supply with jitter, it
is preferable to apply 12 ns or higher CDS pulses.
Digital-to-Analog Converter (OFDOUT DAC)
VOFDOUT(p-p) additional 8-bit control
DAC (OFD) output voltage
(peak-to-peak value)
RL=1MΩ−1.0 −V
VOFDOUT DC output voltage OFD input code 0 −AGND −V
OFD input code 255 −AGND + 1.0 −V
TCOFD OFD output range
temperature coefficient −250 −ppm/K
ZOFDOUT OFD output impedance −2000 −Ω
I
OFDOUT OFD output drive current static −− 100 µA
Digital outputs (fpix = 18 MHz; CL=10pF); see Figs 3 and 4
VOH HIGH-level output voltage IOH =−1mA V
CCO −0.5 −VCCO V
VOL LOW-level output voltage IOL =1mA 0 −0.5 V
IOZ OFF-state output current 0.5V<V
OZ <V
CCO −20 −+20 µA
th(o) output hold time 9 −−ns
td(o) output delay time VCCO = 3.0 V −17 23 ns
VCCO = 2.7 V −19 25 ns
CLload capacitance −− 22 pF
Serial interface
fSCLK(max) maximum frequency
pin SCLK 5−−MHz
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 Oct 25 11
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
handbook, full pagewidth
N
0.6 V 0.6 V
2.2 V
N + 1N + 2N + 3
tCDS(min)
tCLKH
th(IN-SHP)
0.6 V
0.6 V 0.6 V
0.6 V 0.6 V
th(IN-SHD)
0.6 V
2.2 V
2.2 V
tCDS(min)
td(SHD-CLK)
tsu(BLK-CLK)
2.2 V
FCE337
IN
SHP
SHD
CLK
DATA
BLK
th(o) td(o)
N − 1 N
50%
Fig.3 Pixel frequency timing diagram with active HIGH-level polarities.
2002 Oct 25 12
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
handbook, full pagewidth
N
0.6 V
0.6 V
2.2 V
N + 1N + 2N + 3
tCLKL
th(IN-SHP)
2.2 V
2.2 V 2.2 V
2.2 V
th(IN-SHD)
0.6 V
2.2 V
0.6 V
tCDS(min)
tCDS(min)
td(SHD-CLK)
tsu(BLK-CLK)
0.6 V
0.6 V
FCE328
IN
SHP
SHD
CLK
DATA
BLK
th(o) td(o)
N − 1 N
50%
Fig.4 Pixel frequency timing diagram with active LOW-level polarities.
2002 Oct 25 13
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
handbook, full pagewidth
FCE332
0
VOFDOUT
(V)
1.0
0255
OFD control DAC input code
Fig.5 DAC output voltage output as a function of DAC input code.
handbook, full pagewidth
FCE333
BLK
(active HIGH)
CLPOB
(active HIGH)
PGA output
4 pixels(1)
VIDEO OPTICAL BLACK
CLPOB
WINDOW
HORIZONTAL FLYBACK DUMMY VIDEO
BLK window
Fig.6 Line frequency timing diagram.
(1) In this case the number of clamp pixels is limited to 18 ×(tW(clamp)); otherwise this timing interval can be
2002 Oct 25 14
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
0 64 192 320
PGA input code
128
Total
gain
(dB)
256 383
42
30
6
0
12
24
36
18
FCE327
ADC input range is 1 Vpp.
Fig.7 Total gain as a function of PGA input code.
handbook, halfpage
FCE329
Ntot(rms)
(LSB) 5
4
3
2
0
6
1
0 64 192 320
PGA input code
128 256 383
Noise measurement at ADC outputs; coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works
at 18 Mpixels with line of 1024 pixels whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during
the other pixels. As a result of this, the standard deviation of the codes statistic is computed, resulting in the noise.
Fig.8 Typical total noise performance as a function of PGA gain.
2002 Oct 25 15
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
handbook, full pagewidth
OFDOUT DAC
LATCHES PGA GAIN
LATCHES ADC CLAMP
LATCHES
CONTROL PULSE
POLARITY
LATCHES
LATCH
SELECTION
SD0
LSB MSB
SDATA
SCLK
SEN
8-bit DAC
FCE334
PGA
control ADC clamp
control
control pulses
polarity
settings
VSYNC
SD1 SD2 SD3 SD4 SD5
10
SD6
SHIFT REGISTER
SD7 SD8 SD9 A0 A1
8 9 7 6
FLIP-FLOP FLIP-FLOP FLIP-FLOP
Fig.9 Serial interface block diagram.
handbook, full pagewidth
FCE335
SDATA
SCLK
SEN
A1 A0 SD9 SD7 SD6 SD5 SD4 SD3
MSB LSB
SD2 SD1 SD0
thd3
tsu3
tsu1
thd4
tsu2
SD8
Fig.10 Loading sequence of control input data via the serial interface.
tsu1 =t
su2 =t
su3 = 10 ns (minimum); thd3 =t
hd4 = 10 ns (minimum).
2002 Oct 25 16
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
Table 1 Serial interface programming; see Figs 9 and 10
Table 2 Polarity settings
Note
1. Bit SD4 is not used.
Table 3 Standby mode selection; pin STDBY
Table 4 Output enable (OE) pin 37
ADDRESS BITS DATA BITS SD9 TO SD0
A1 A0
0 0 PGA gain control (bits SD8 to SD0); bit SD9 should be set to logic 0
0 1 DAC OFDOUT output control (bits SD7 to SD0); bits SD8 and SD9 should be set to
logic 0
1 0 ADC clamp reference control (SD6 to SD0); from code 0 to 127; bits SD7, SD8 and
SD9 should be set to logic 0
1 1 control pulses polarity settings (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK)
SYMBOL PIN SERIAL CONTROL BIT(1) ACTIVE EDGE OR LEVEL
SHP and SHD 47 and 48 SD0 1 = HIGH; 0 = LOW
CLK 40 SD1 1 = HIGH; 0 = LOW
CLPDM 12 (connected to ground) SD2 always 0 = LOW
CLPOB 13 SD3 1 = HIGH; 0 = LOW
BLK 11 SD5 1 = HIGH; 0 = LOW
VSYNC 24 SD6 0 = rising; 1 = falling
STDBY ADC DIGITAL OUTPUTS; PINS D9 TO D0 ICCA +I
CCO +I
CCD (typical)
1 logic state LOW 1.5 mA
0 active 64 mA
OE ADC DIGITAL OUTPUTS; PINS D9 TO D0
0 active, binary
1 high impedance
2002 Oct 25 17
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
APPLICATION INFORMATION
Power and grounding recommendations
When designing a printed-circuit board for applications
such as PC cameras, surveillance cameras, camcorders
and digital still cameras, care should be taken to minimize
the noise.
For the front-end integrated circuit, the basic rules
of printed-circuit board design and implementation
of analog components (such as additional operational
amplifiers) must be respected, particularly with respect
to power and ground connections.
The following additional recommendation is given for the
CDS input pin(s) which is /are internally connected to the
programmable gain amplifier.
The connections between the CCD interface and
CDS input should be as short as possible and a ground
ring protection around these connections can be
beneficial. Separate analog and digital supplies provide
the best solution. If this is not possible to do this on the
board then the analog supply pins must be decoupled
effectively from the digital supply pins. If the same power
supply and ground are used for all the pins then the
decouplingcapacitors mustbeplaced asclose aspossible
to the IC package.
In order to minimize the noise due to package and die
parasitics in a two-ground system, the following measures
must be implemented:
•Allthe analog and digitalsupply pinsmustbe decoupled
to the analog ground plane. Only the ground pin
associated with the digital outputs must be connected to
thedigital groundplane.All the othergroundpins should
be connected to the analog ground plane. The analog
anddigital groundplanesmustbeconnected togetherat
one point as close as possible to the ground pin
associated with the digital outputs.
•The digital output pins and their associated lines should
be shielded by the digital ground plane which can then
be used as a return path for digital signals.
2002 Oct 25 18
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
Application diagram
handbook, full pagewidth
FCE336
1
2
3
4
5
6
7
8
9
10
11
36
48
(2) (2)
47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
35
34
33
32
31
30
29
28
27
26
12 25
TDA8787AHL
D9
D8
D7
D6
D4
D3
D2
D1
D0
OGND
VCCO
VCCD3
DGND3
AGND4
IN
AGND1
VCCA1
CPCDS2
OFDOUT
BLK
CLPDM
D5
SHP
OPGAC
OPGA
DCLPC
AGND5
VCCA3
CLK
DGND2
OE
VCCD2
SHD
AGND3
CPCDS1
STDBY
TEST1
TEST2
TEST3
AGND2
VCCA2
VCCD1
DGND1
SCLK
SEN
VSYNC
CLPOB
SDATA
serial interface
VCCA
VCCD
CCD
(2)
VCCD
VCCD
VCCD
VCCA
100 nF
VCCD
100 nF
VCCD
100
nF
100
nF
100
nF
VCCA
100
nF
1 µF
1 µF
1 µF
1 µF
1 µF
(1)
Fig.11 Application diagram.
(1) Pins SEN and VSYNC should be interconnected when no vertical synchronization signal is available, while control pin VSYNC should be
programmed by serial interface as LOW-level active.
(2) The timing of the signals on pins IN, SHD and SHP has to comply with the hold times th(IN-SHP) and th(IN-SHD) (see Fig.3).
2002 Oct 25 19
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
PACKAGE OUTLINE
UNIT A
max. A1A2A3bpcE
(1) eH
E
LL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 1.60 0.20
0.05 1.45
1.35 0.25 0.27
0.17 0.18
0.12 7.1
6.9 0.5 9.15
8.85 0.95
0.55 7
0
o
o
0.12 0.10.21.0
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT313-2 MS-026136E05 99-12-27
00-01-19
D(1) (1)(1)
7.1
6.9
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48
37
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24
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pin 1 index
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
2002 Oct 25 20
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
SOLDERING
Introduction to soldering surface mount packages
Thistext givesa verybriefinsight toacomplex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs, butit isnot suitablefor finepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screenprinting,stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices (SMDs)or printed-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleads onfour sides,the footprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2002 Oct 25 21
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formore detailed informationontheBGA packages refertothe
“(LF)BGAApplicationNote
”(AN01026); order acopy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
2002 Oct 25 22
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese oratany otherconditionsabove thosegivenin the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warrantythat suchapplicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusing orsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2002 Oct 25 23
Philips Semiconductors Product specification
10-bit, 3.0 V, up to 18 Msps analog-to-digital
interface for CCD cameras TDA8787A
NOTES
© Koninklijke Philips Electronics N.V. 2002 SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a world wide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands 753504/04/pp24 Date of release: 2002 Oct 25 Document order number: 9397 750 10096
