ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output FEATURES AND BENEFITS DESCRIPTION * * * * Designed to provide the power supply requirements of next generation car audio and infotainment systems, the ARG81801 provides all the control and protection circuitry to produce a high current regulator with 1.0% output voltage accuracy. After startup, the ARG81801 operates down to at least 3.6VIN (VIN falling). * * * * * * * * Automotive AEC-Q100 qualified Withstands surge voltages up to 40 V Operates as low as 3.6 VIN (max) with VIN decreasing Delivers up to 3.0 A of output current with integrated 110m high voltage MOSFET SLEEP input pin commands ultralow current shutdown mode Adjustable output voltage with 1.0% accuracy from 0C to 85C, 1.5% from -40C to 150C Programmable switching frequency: 250 kHz to 2.4 MHz Applying a clock input to the SYNC pin will increase the PWM frequency Power OK (POK) open-drain output Maximized duty cycle for low dropout Enhanced idle-stop recovery during VIN transients Pre-bias startup capable, VOUT will not cause a reset If the SYNC input is driven by an external clock signal higher than the base frequency (fOSC), the PWM frequency synchronizes to the incoming clock frequency. The SLEEP input pin commands an ultralow current shutdown mode requiring less than 5A for internal circuitry and 10A (max) for MOSFET leakage at 16VIN, 85C. The ARG81801 has external compensation to accommodate a wide range of frequencies and external components, and provides a Power OK (POK) signal validated by the output voltage. The ARG81801 uses an Enhanced Idle/Stop-Start Recovery technique to reduce or eliminate output overshoot when VIN recovers from levels below VIN minimum (i.e. VOUT drops out of regulation). Continued on next page... PACKAGE: 24-pin wettable flank QFN with exposed thermal pad (suffix ES) Extensive protection features of the ARG81801 include pulseby-pulse current limit, hiccup mode short circuit protection, open/short asynchronous diode protection, BOOT open/ short voltage protection, VIN undervoltage lockout, VOUT overvoltage protection, and thermal shutdown. Continued on next page... Not to scale VBAT BOOT VIN CIN LO GND ARG81801 D1 COMP SS FSET VREG CLKIN SLEEP SYNC POK CO RFB1 FB TEST ENABLE VOUT SW RFB2 POK Typical Application Diagram ARG81801-DS, Rev. 2 MCO-0000369 February 11, 2019 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output FEATURES AND BENEFITS * External compensation for maximum flexibility * Excellent set of protection features to satisfy the most demanding applications * Overvoltage, pulse-by-pulse current limit, hiccup mode short circuit, and thermal protection DESCRIPTION The ARG81801 is supplied in a 24-pin wettable flank QFN package with exposed power pad (suffix ES). It is lead (Pb) free, with 100% matte-tin leadframe plating. SELECTION GUIDE Part Number Operating Ambient Temperature Range TA, (C) Packing ARG81801KESJSR -40 to 150 6000 pieces per 13-in. reel Table of Contents Features and Benefits............................................................ 1 Description........................................................................... 1 Package.............................................................................. 1 Typical Application Diagram.................................................... 1 Selection Guide.................................................................... 2 Absolute Maximum Ratings.................................................... 3 Thermal Characteristics......................................................... 3 Functional Block Diagram...................................................... 4 Pinout Diagram and Terminal List............................................ 5 Electrical Characteristics........................................................ 6 Typical Performance Characteristics...................................... 10 Functional Description......................................................... 12 Overview........................................................................ 12 Reference Voltage........................................................... 12 PWM Switching Frequency............................................... 12 SLEEP Input................................................................... 12 Synchronization Input....................................................... 12 Transconductance Error Amplifier...................................... 13 Slope Compensation........................................................ 13 Current Sense Amplifier.................................................... 13 Power MOSFETs............................................................. 13 BOOT Regulator.............................................................. 13 Pulse-Width Modulation (PWM) ........................................ 14 Soft Start (Startup) and Inrush Current Control.................... 14 Pre-Biased Startup........................................................... 15 Power OK (POK) Output................................................... 15 Protection Features.......................................................... 16 Undervoltage Lockout (UVLO)....................................... 16 Pulse-by-Pulse Overcurrent Protection (OCP).................. 16 Overcurrent Protection (OCP) and Hiccup Mode.............. 16 BOOT Capacitor Protection........................................... 17 Asynchronous Diode Protection..................................... 17 Overvoltage Protection (OVP)........................................ 17 Pin-to-Ground and Pin-to-Short Protections..................... 17 Thermal Shutdown (TSD).............................................. 17 Application Information........................................................ 20 Design and Component Selection...................................... 20 Setting the Output Voltage (VOUT)................................... 20 Output Inductor (LO)..................................................... 21 Output Capacitors........................................................ 21 Input Capacitors........................................................... 22 Asynchronous Diode (D1)............................................. 23 Bootstrap Capacitor...................................................... 23 Soft Start and Hiccup Mode Timing (CSS)........................ 23 Compensation Components (RZ, CZ, and CP).................. 24 Power Dissipation and Thermal Calculations.......................... 27 PCB Component Placement and Routing............................... 28 Package Outline Drawing..................................................... 30 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS [1] Characteristic Symbol Notes Rating -0.3 to 40 V Continuous (minimum limit is a function of temperature) -0.3 to VIN + 0.3 V VIN, SLEEP, SS Pin Voltage SW Pin Voltage BOOT Pin Voltage VSW VBOOT t < 50 ns -1.0 to VIN + 0.3 V Continuous VSW - 0.3 to VSW + 5.5 V BOOT OV Fault Condition VSW - 0.3 to VSW + 7.0 V All Other Pin Voltages Maximum Junction Temperature Storage Temperature [1] Unit -0.3 to 5.5 V TJ(max) 150 C Tstg -55 to 150 C Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratingsare stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS: May require derating at maximum conditions, see application information Characteristic Package Thermal Resistance [2] Additional Symbol RqJA Test Conditions [2] On 4-layer PCB based on JEDEC standard Value Unit 37 C/W thermal information available on the Allegro website. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 VIN TEST BIAS VIN LDO TEST 3.05 V OFF + - DELAY 103 s 2.90 V Digital BOOT OFF 2 V, 4.1 V 1.205 V BOOT REG. 5.0 V UVLO BG VREG SLEEP\ - 3.8 V 3.4 V OC 250 mA EN BOOT REG Q POR + BOOT OFF 400 mV BOOT + - ISENSE + SE BOOT FAULT GCSA fSYNC > 1.2 x fOSC blankOn fOSC fOSC /2 fOSC /4 sleep PWM SYNC minOff FB < 0.4 V fOSC FB < 0.2 V FSET S Q R Q Current Comp 110 m Q fSW maxDuty VREG RSYNC swLoDet 10 DIODEOK BOOT < 4.1V IFB ERROR AMP FB sleep PWM CLAMP 800 mV - 400 mV + sleep PWM sleep PWM maxDuty IDLE-STOP compFalling RECOVERY CONTROL OCL COMP ssDischarge SS 5 A 20 A FB < 740 mV FB > 880 mV OCL swLoDet DIODEOK BOOT FAULT UVLO POR TSD SW SW FAULT LOGIC (See Fault Table) sleep PWM HIC SET HICCUP LOGIC 1 k HICCUP 2 k HIC RST PULL DOWN BOOT OFF POK DELAY FB > 880 mV 26 s FB < 740 mV Functional Block Diagram Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output 19 BOOT 20 NC 21 NC 22 NC 23 NC 24 NC PINOUT DIAGRAM AND TERMINAL LIST VIN 1 18 SW VIN 2 17 SW SS 3 SLEEP 4 GND 5 14 TEST SYNC 6 13 FB 16 GND COMP 12 15 VREG NC 11 NC 10 9 NC 7 POK FSET 8 PAD Package ES, 24-Pin QFN Pinout Diagram Terminal List Table Name Number Function VIN 1, 2 SS 3 Soft start and hiccup pin. Connect a capacitor, CSS, from this pin to GND to set soft start mode duration. The capacitor also determines the hiccup period during overcurrent. SLEEP 4 Setting this pin low forces sleep mode (very low current shutdown mode: VOUT = 0 V). This pin must be set high to enable the ARG81801. If the application does not require a sleep mode, then this pin can be tied directly to VIN. Do not float this pin. GND 5, 16 SYNC 6 Applying an external clock input to this pin forces synchronization of PWM to the clock input rate (fSYNC), at a rate higher than fOSC. SLEEP low overrides this pin. POK 7 Power OK output signal. This pin is an open drain output that transitions from low to high impedance after the output has maintained regulation for td(POK), typically 26s. FSET 8 Frequency setting pin. A resistor, RFSET, from this pin to GND sets the base PWM switching frequency (fOSC). See the Design and Component Selection section for information on determining the value of RFSET. NC 9-11, 20-24 COMP 12 Output of the error amplifier and compensation node for the current mode control loop. Connect a series RC network from this pin to GND for loop compensation. See the Design and Component Selection section of this datasheet for further details. FB 13 Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulator output, VOUT, to this pin to program the output voltage. TEST 14 Test mode pin. This pin should be connected to ground. Allegro recommends using a resistor from this pin to ground to limit the regulator output voltage in the event the FB pin becomes shorted to this pin. VREG 15 Internal voltage regulator bypass capacitor pin. Connect a 1 F ceramic capacitor from this pin to ground and place it close to the ARG81801. SW 17, 18 BOOT 19 High-side gate drive boost input. This pin supplies the drive for the high-side N-channel MOSFET. Connect a 47 nF ceramic capacitor from BOOT to SW. PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 6 vias, directly in the pad land. Power input for the control circuits and the drain of the high-side N-channel MOSFET. Connect this pin to a power supply providing from 4.0 to 35 V. A ceramic capacitor should be placed and grounded very close to this pin. Ground pins. No connect pins. These should be connected to ground to aid thermal transfer. The source of the high-side N-channel MOSFET. The external free-wheeling diode (D1) and output inductor (LO) should be connected to this pin. Both D1 and LO should be placed close to this pin and connected with relatively wide traces. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ELECTRICAL CHARACTERISTICS: Valid at 4.0 V VIN 35 V, -40C TJ 150C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit INPUT VOLTAGE Input Voltage Range [1] 4.0 - 35 V VINUV(ON) VIN VIN rising 3.6 3.8 4.0 V VIN UVLO Stop VINUV(OFF) VIN falling 3.2 3.4 3.6 V VIN UVLO Hysteresis VINUV(HYS) - 400 - mV VSLEEP 0.5 V, TJ = 85C, VIN = 16 V - 5 15 A VSLEEP 0.5 V, TJ = 85C, VIN = 35 V - 7 25 A IOUT = 0 mA - 2.5 5.0 mA 0C < TJ < 85C, VIN 4.1 V, VFB = VCOMP 792 800 808 mV -40C < TJ < 150C, VIN 4.1 V, VFB = VCOMP 788 800 812 mV TA = 85C, RDC(LO) 75 m, VIN = 3.6 V, IOUT = 1 A, fSW = 425 kHz 3.27 3.295 - V TA = 85C, RDC(LO) 75 m, VIN = 5.3 V, IOUT = 1 A, fSW = 425 kHz 4.95 5.0 - V TA = 85C, RDC(LO) 50 m, VIN = 3.75 V, IOUT = 1 A, fSW = 2 MHz 3.25 3.3 - V TA = 85C, RDC(LO) 50 m, VIN = 5.5 V, IOUT = 1 A, fSW = 2 MHz 4.89 5.0 - V VIN UVLO Start INPUT SUPPLY CURRENT Sleep Mode Input Supply Current [2][3] PWM Mode Input Supply Current [2] IIN(SLEEP) IIN(PWM) VOLTAGE REGULATION Feedback Voltage Accuracy [4] Output Dropout Voltage [5] VFB VOUT(SAT) ERROR AMPLIFIER Feedback Input Bias Current [2] Open Loop Voltage Gain IFB AVOL Transconductance gm Output Current IEA COMP Pull-Down Resistance RCOMP -38 - -16 nA VCOMP = 1.2 V - 65 - dB 400 mV < VFB 500 750 950 A/V 0 V < VFB < 400 mV 275 375 475 A/V VCOMP = 1.2 V - 75 - A FAULT = 1 or HICCUP = 1 - 1 - k Continued on next page... [1] Thermally limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow. current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. [3] Performance at 85C ensured by design and characterization, not production tested. [4] Performance at the 0C and 85C ranges ensured by design and characterization, not production tested. [5] Ensured by design and characterization, not production tested. [2] Negative Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 ELECTRICAL CHARACTERISTICS (continued): Valid at 4.0 V VIN 35 V, -40C TJ 150C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit VCOMP level required for 0% duty cycle - 12 V < VIN < 16 V, IOUT = 1 A, VBOOT - VSW = 4.5 V - 400 - mV 95 135 ns PULSE WIDTH MODULATION (PWM) PWM Ramp Offset VPWM(OFFS) Minimum Controllable On-Time tON(MIN) Minimum Switch Off-Time tOFF(MIN) - 95 130 ns COMP to SW Current Gain gmPOWER - 4.0 - A/V fOSC = 2.44 MHz 2.31 3.30 4.30 A/s fOSC = 1.00 MHz 0.66 1.00 1.32 A/s fOSC = 252 kHz 0.15 0.22 0.29 A/s TJ =25C, VBOOT - VSW = 4.5 V, IDS = 0.4 A - 110 125 m TJ =150C, VBOOT - VSW = 4.5 V, IDS = 0.4 A - 190 215 m TJ < 85C, VSLEEP 0.5 V, VSW = 0 V, VIN = 16 V - - 10 A Slope Compensation [6] MOSFET PARAMETERS SE [7] High-Side MOSFET On-Resistance [8] High-Side MOSFET Leakage [9][10] SW Node Slew Rate [6] Low-Side MOSFET On-Resistance [8] RDS(on)HS ILKG(HS) SRSW RDS(on)LS TJ 150C, VSLEEP 0.5 V, VSW = 0 V, VIN = 16 V - 60 150 A 12 V < VIN < 16 V - 0.72 - V/ns TJ = 25C, VIN 6 V, IDS = 0.1 A - - 10 PWM SWITCHING FREQUENCY Base Switching Frequency RFSET = 8.06 k 2.20 2.44 2.70 MHz RFSET = 23.7 k 0.90 1.00 1.10 MHz RFSET = 102 k - 252 - kHz fSYNC(MULT) 1.2 x fOSC(typ) - 1.5 x fOSC(typ) - fSYNC - - 2.9 MHz fOSC PWM SYNCHRONIZATION TIMING Synchronization Frequency Range Synchronized Frequency Synchronization Input Duty Cycle DSYNC - - 80 % Synchronization Input Pulse Width tw(SYNC) 200 - - ns Synchronization Input Rise Time [6] tr(SYNC) - 10 15 ns Synchronization Input Fall Time [6] tf(SYNC) - 10 15 ns V Synchronization High Threshold VSYNC(H) - - 2.0 Synchronization Low Threshold VSYNC(L) 0.8 - - V VSYNC(HYS) - 200 - mV RSYNC 120 200 280 k Synchronization Hysteresis [6] Synchronization Input Resistance Continued on next page... [6] Ensured by design and characterization, not production tested. limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow. [8] Performance at 25C ensured by design and characterization, not production tested. [9] Negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. [10] Performance at 85C ensured by design and characterization, not production tested. [7] Thermally Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ELECTRICAL CHARACTERISTICS (continued): Valid at 4.0 V VIN 35 V, -40C TJ 150C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit SLEEP PIN INPUT THRESHOLDS SLEEP High Threshold VSLEEP(H) VSLEEP rising - 1.3 2.1 V SLEEP Low Threshold VSLEEP(L) VSLEEP falling 0.5 1.2 - V td(SLEEP) SLEEP Delay VSLEEP transitioning low 55 103 150 s ISLEEP(BIAS) VSLEEP = 5 V - 500 - nA VVREG VTEST = 0 V - 3.05 - V - fSW - - VBOOT rising 1.7 2.0 2.2 V - 200 - mV VBOOT rising - 4.1 - V VSS(RST) VSS falling due to RSS(FLT) - 200 275 mV Hiccup OCP Threshold VHIC(EN) VSS rising - 2.3 - V Maximum Charge Voltage VSS(MAX) - VVREG - V SLEEP Input Bias Current VREG PIN OUTPUT VREG Output Voltage BOOT REGULATOR BOOT Charging Frequency [11] fBOOT BOOT Voltage Enable Threshold VBOOT(EN) BOOT Voltage Enable Hysteresis VBOOT(HYS) BOOT Voltage Low-Side Switch Disable Threshold VBOOT(LS,DIS) SOFT START PIN FAULT, HICCUP Reset Voltage Startup (Source) Current ISS(SU) HICCUP = FAULT = 0 -30 -20 -10 A Hiccup (Sink) Current ISS(HIC) HICCUP = 1 2.4 5 10 A Pull-Down Resistance RSS(FLT) FAULT = 1 or VSLEEP = low - 2 - k 0 V < VFB < 200 mV - fOSC / 4 - - 200 mV < VFB < 400 mV - fOSC / 2 - - 400 mV < VFB - fOSC - - td(SS) CSS = 22 nF - 440 - s tSS CSS = 22 nF - 880 - s VSS > 2.3 V and OCL = 1 - 120 - counts Soft Start Frequency Foldback Soft Start Delay Time [11] Soft Start Output Ramp Time [11] fSW(SS) HICCUP MODES Hiccup, OCP Count OCPLIM Hiccup, BOOT Undervoltage (Shorted) Count BOOTUV - 120 - counts Hiccup, BOOT Overvoltage (Open) Count BOOTOV - 7 - counts Continued on next page... [11] Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ELECTRICAL CHARACTERISTICS (continued): Valid at 4.0 V VIN 35 V, -40C TJ 150C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit OVERCURRENT PROTECTION (OCP) PWM Pulse-by-Pulse Limit ILIM(TON,MIN) tON = tON(MIN) 4.8 5.5 6.1 A ILIM(TON,MAX) tON = (1/fSW) - tOFF(MIN), no synchronization 3.0 4.1 5.1 A VFB rising, PWM mode 860 880 902 mV - -10 - mV OUTPUT VOLTAGE PROTECTION (OVP) VOUT Overvoltage Threshold VOUT(OV) VOUT Overvoltage Hysteresis VOUT(OV)HYS VOUT Undervoltage Threshold VOUT(UV) VOUT Undervoltage Hysteresis VOUT(UV)HYS VFB falling, relative to VOUT(OV) VFB falling, PWM mode 715 740 765 mV VFB rising, relative to VOUT(UV) - 10 - mV td(POK) VFB rising only 19 30 41 s POK Low Output Voltage VPOK(L) IPOK = 5 mA - 185 400 mV POK Leakage Current [12] IPOK(LKG) VPOK = 5.5 V -1 - 1 A PWM stops immediately and COMP and SS are pulled low 155 170 185 C - 20 - C POWER OK (POK) OUTPUT POK Rising Delay THERMAL PROTECTION Thermal Shutdown Rising Threshold [13] Thermal Shutdown Hysteresis [13] [12] Negative [13] Ensured TSD TSD(HYS) current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. by design and characterization, not production tested. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 TYPICAL PERFORMANCE CHARACTERISTICS Reference Voltage versus Temperature Oscillator Frequency versus Temperature 3.50 808 fOSC = 2.44 MHz 806 3.00 fOSC = 1.00 MHz 2.50 802 fOSC (MHz) VVREF (mV) 804 800 798 2.00 1.50 796 1.00 794 792 -50 75 25 50 Temperature (C) 0 100 125 VIN UVLO Start and Stop Thresholds versus Temperature START, VINUV(ON) STOP, VINUV(OFF) 3.5 3.4 75 25 50 Temperature (C) 0 100 125 150 Pulse-by-Pulse Current Limit at tON(MIN) (ILIM(TON,MIN)) versus Temperature 150 850 VOUT(OV) VOUT(UV) 800 750 700 -25 0 75 25 50 Temperature (C) 100 125 150 VFB > 400 mV ILIM 800 Transconductance (A/V) ILIM (A) 125 900 4.30 4.20 4.10 4.00 3.90 3.80 3.70 -50 100 Error Amplifier Transconductance versus Temperature 4.50 4.40 75 25 50 Temperature (C) 900 650 -50 3.3 -25 0 950 3.7 -50 -25 VOUT Overvoltage and Undervoltage Thresholds versus Temperature 3.8 3.6 0.20 -50 150 VOUT OV and UV Thresholds (V) VIN UVLO Thresholds (V) 3.9 -25 VFB < 400 mV 700 600 500 400 300 200 -25 0 25 50 75 Temperature (C) 100 125 150 100 -50 -25 0 75 25 50 Temperature (C) 100 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 125 150 10 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output SLEEP High and Low Voltage Thresholds Thresholds versus Temperature SS Start and Hiccup Currents versus Temperature 1.40 25.0 VSLEEP(H) Startup, ISSSU VSLEEP(L) Hiccup, ISSHIC 20.0 Current (A) SLEEP Thresholds (V) 1.60 1.20 1.00 15.0 10.0 0.80 5.0 0.60 -50 -25 0 75 25 50 Temperature (C) 100 125 0 150 -50 POK Low Output Voltage at 5 mA versus Temperature 35 350 34 100 125 150 td(POK) 32 250 td(POK) (s) VPOK (mV) 75 25 50 Temperature (C) 33 300 200 150 100 31 30 29 28 27 50 26 25 -50 -25 0 75 25 50 Temperature (C) 100 125 150 -50 -25 0 25 50 75 100 125 150 Temperature (C) Sync High and Low Voltage Thresholds versus Temperature 1.60 VSYNC(H) 1.55 VSYNC(L) 1.50 Sync Thresholds (V) 0 POK Time Delay versus Temperature 400 0 -25 1.45 1.40 1.35 1.30 1.25 1.20 1.15 -50 -25 0 75 25 50 Temperature (C) 100 125 150 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 FUNCTIONAL DESCRIPTION Overview The ARG81801 is an asynchronous current mode buck regulator that incorporates all the control and protection circuitry necessary to provide the power supply requirements of car audio and infotainment systems. The ARG81801 has two modes of operation. First, the ARG81801 can deliver up to 3.0 A in pulse-width modulation (PWM) mode. Second, with the SLEEP pin low, the ARG81801 will enter an ultralow current shutdown (sleep) mode where VOUT=0V and the total current drawn from VIN will typically be less than 10 A. The ARG81801 was designed to support up to 3.0 A. However, the exact amount of current it will supply, before possible thermal shutdown, depends heavily on duty cycle, ambient temperature, airflow, PCB layout, and PCB construction. Figure 1 shows calculated current ratings versus ambient temperature for VIN=12V and VOUT = 3.3 V and 5.0 V, at fSW = 425 kHz and fSW=2MHz. This analysis assumed a 4-layer PCB constructed according to the JEDEC standard (yielding a thermal resistance of 37C/W), with no nearby heat sources, and no airflow. -40C to 150C. The output voltage is programmed by connecting a resistor divider from VOUT to the FB pin of the ARG81801, as shown in the Typical Applications schematics. PWM Switching Frequency The PWM switching frequency of the ARG81801 is adjustable from 250 kHz to 2.4 MHz and has an accuracy of about 10% across the operating temperature range. During startup, the PWM switching frequency changes from 25% to 50% and finally to 100% of fOSC, as VOUT rises from 0 V to the regulation voltage. The startup switching frequency is discussed in more detail in the section describing soft start. If the regulator output is shorted to ground, VFB 0 V, the PWM frequency will be 25% of fOSC. In this case, the extra low switching frequency allows extra off-time between SW pulses. The extra off time allows the output inductor current to decay back to 0 A before the next SW pulse occurs. This prevents the inductor current from climbing to a value that could damage the ARG81801 or the output inductor. SLEEP Input 3.25 The ARG81801 has a SLEEP logic level input pin. To get the ARG81801 to operate, the SLEEP pin must be a logic high (>2.1V). The SLEEP pin is rated to 40 V, allowing the SLEEP pin to be connected directly to VIN if there is no suitable logic signal available to wake up the ARG81801. 3.00 Current Rating (A) 2.75 2.50 2.25 2.00 1.75 12 VIN / 5 VO / 2.1 MHz 1.50 12 VIN / 5 VO / 410 kHz 1.25 12 VIN / 3.3 VO / 2.1 MHz 1.00 0.75 When SLEEP transitions low, the ARG81801 waits approximately 103 s before shutting down. This delay provides plenty of filtering to prevent the ARG81801 from prematurely entering sleep mode because of any small glitch coupling onto the PCB trace or SLEEP pin. 12 VIN / 3.3 VO / 410 kHz 50 60 70 80 90 100 110 120 130 Ambient Temperature (C) Figure 1: ARG81801 Typical Current Derating Reference Voltage The ARG81801 incorporates an internal reference that allows output voltages (VOUT) as low as 0.8 V. The accuracy of the internal reference is 1.0% from 0C to 85C and 1.5% from Synchronization Input If an external clock is applied to the SYNC pin, the ARG81801 synchronizes its PWM frequency to the external clock. The external clock may be used to increase the ARG81801's base PWM frequency (fOSC(TYP)) set by RFSET. Synchronization operates from 1.2xfOSC(TYP) to 1.5xfOSC(TYP). The external clock pulses must satisfy the pulse width, duty-cycle, and rise/fall time requirements shown in the Electrical Characteristics table in this datasheet. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output Transconductance Error Amplifier The transconductance error amplifier primary function is to control the regulator output voltage. The error amplifier is shown in Figure 2. Here, it is shown as a three-terminal input device with two positive and one negative input. The negative input is simply connected to the FB pin and is used to sense the feedback voltage for regulation. The two positive inputs are used for soft start and steady-state regulation. The error amplifier performs an analog OR selection between its two positive inputs. The error amplifier regulates to either the soft start pin voltage (minus 400 mV) or the ARG81801 internal reference, VREF, whichever is lower. To stabilize the regulator, a series RC compensation network (RZ and CZ) must be connected from the error amplifier output (the COMP pin) to GND, as shown in the Typical Applications schematics. In most instances, an additional relatively low value capacitor (CP) should be connected in parallel with the RZ-CZ components to reduce the loop gain at very high frequencies. However, if the CP capacitor is too large, the phase margin of the regulator may be reduced. Calculating RZ, CZ, and CP is covered in detail in the Design and Component Selection section of this datasheet. table, the amount of slope compensation scales with the base switching frequency set by RFSET (fOSC). The amount of slope compensation does not change when the regulator is synchronized to an external clock. The value of the output inductor should be chosen such that SE is from 0.5x to 1x the falling slope of the inductor current (SF). Current Sense Amplifier The ARG81801 incorporates a high-bandwidth current sense amplifier to monitor the current in the high-side MOSFET. This current signal is used by the PWM control circuitry to regulate the peak current. The current signal is also used by the protection circuitry to prevent damage to the ARG81801. Power MOSFETs The ARG81801 includes a 40 V, 110 m high-side N-channel MOSFET, capable of delivering at least 3.0 A. The ARG81801 also includes a 10 , low-side MOSFET to help ensure the BOOT capacitor is always charged. The typical RDS(on) increase versus temperature is shown in Figure 3. 1.8 If a fault occurs or the regulator is disabled (SLEEP = low), the COMP pin is pulled to GND via approximately 1 k and PWM switching is inhibited. 1.6 1.4 1.2 Normalized RDS(on) 400 mV Error Amplifier SS Pin COMP Pin VREF 800 mv 1.0 0.8 0.6 0.4 0.2 0.0 -40 -20 0 20 80 40 50 Temperature (C) 100 120 140 160 Figure 3: Typical MOSFET RDS(on) versus Temperature FB Pin BOOT Regulator Figure 2: ARG81801 Error Amplifier Slope Compensation The ARG81801 incorporates internal slope compensation (SE) to allow PWM duty cycles above 50% for a wide range of input/output voltages and inductor values. The slope compensation signal is added to the sum of the current sense amplifier output and the PWM ramp offset. As shown in the Electrical Characteristics The ARG81801 contains a regulator to charge the boot capacitor. The voltage across the BOOT capacitor is typically 5.0 V. If the BOOT capacitor is missing, the ARG81801 detects a boot overvoltage. Similarly, if the BOOT capacitor is shorted, the ARG81801 detects a boot undervoltage. Also, the BOOT regulator has a current limit to protect itself during a short circuit condition. The details of how each type of boot fault is handled by the ARG81801 are summarized in Table 1 and shown in Figure 10. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output Pulse-Width Modulation (PWM) The ARG81801 uses fixed-frequency, peak current mode control to provide excellent load and line regulation, fast transient response, and ease of compensation. A high-speed comparator and control logic, capable of typical pulse widths of 95 ns, are included in the ARG81801. The inverting input of the PWM comparator is connected to the output of the error amplifier. The non-inverting input is connected to the sum of the current sense signal, the slope compensation, and a DC offset voltage (VPWM(OFFS), 400 mVTYP). At the beginning of each PWM cycle, the CLK signal sets the PWM flip-flop and the high-side MOSFET is turned on. When the summation of the DC offset, slope compensation, and current sense signal rises above the error amplifier voltage, the PWM flip-flop is reset and the high-side MOSFET is turned off. The PWM flip-flop is reset-dominant, so the error amplifier may override the CLK signal in certain situations. For example, at very light loads or extremely high input voltages, the error amplifier will reduce its output voltage below the 400 mV DC offset and the PWM flip-flop will ignore one or more of the incoming CLK pulses. The high-side MOSFET will not turn on, and the regulator will skip pulses to maintain output voltage regulation. The ARG81801 includes a comprehensive set of protection circuits. See Figure 10 for a timing diagram showing how faults are handled. Also, the Protection Features section of this datasheet provides a detailed description of each fault and Table 1 presents a summary. Soft Start (Startup) and Inrush Current Control Inrush current is controlled by a soft start function. When the ARG81801 is enabled and all faults are cleared, the soft start pin will source ISS(SU) and the voltage on the soft start capacitor, CSS, will ramp upward from 0 V. When the voltage at the soft start pin exceeds approximately 400 mV, the error amplifier will slew its output voltage above the PWM Ramp Offset (VPWM(OFFS)). At that instant, the high-side and low-side MOSFETs will begin switching. As shown in Figure 4, there is a small delay (td(SS)) between when the enable pin transitions high, and when both the soft start voltage exceeds 400 mV and the error amplifier slews its output high enough to initiate PWM switching. After the ARG81801 begins switching, the error amplifier will regulate the voltage at the FB pin to the soft start pin voltage minus approximately 400 mV. During the active portion of soft start, the voltage at the soft start pin rises from 400 mV to 1.2 V (a difference of 800 mV), the voltage at the FB pin rises from 0 V to 800 mV, and the regulator output voltage rises from 0 V to the targeted setpoint, which is determined by the feedback resistor divider on the FB pin. VSLEEP td(SS) VOUT 3.3 V tSS VSS=1.2 V VSS = 400 mV VCOMP fOSC VSS IL fOSC/4 fOSC/2 Figure 4: Normal Startup to VOUT = 3.3V, IOUT = 1.6A, SLEEP Transitions High During startup, the PWM switching frequency is reduced to 25% of fOSC while VFB is below 200 mV. If VFB is above 200 mV but below 400 mV, the switching frequency is reduced to 50% of fOSC. Also, if VFB is below 400 mV, the gm of the error amplifier is reduced to gm/2. When VFB is above 400 mV the switching frequency will be fOSC and the error amplifier gain will be gm. The reduced switching frequencies and error amplifier gain are necessary to help improve output regulation and stability when VOUT is at a very low voltage. When VOUT is very low, the PWM control loop requires on-times near the minimum controllable ontime, as well as extra-low duty cycles that are not possible at the base operating switching frequencies. When the voltage at the soft start pin reaches approximately 1.2V, the error amplifier will change mode and begin regulating the voltage at the FB pin to the ARG81801 internal reference, 800 mV. The voltage at the soft start pin will continue to rise to approximately VREG. Complete soft start operation from VOUT = 0 V is shown in Figure 4. If the ARG81801 is disabled or a fault occurs, the internal fault latch will be set and the capacitor on the soft start pin will be discharged to ground very quickly by an 2 k pull-down resistor. The ARG81801 will clear the internal fault latch when the voltage at the soft start pin decays to approximately 200 mV (VSS(RST)). Conversely, if the ARG81801 enters hiccup mode, the capacitor on the soft start pin is slowly discharged by a current sink, ISS(HIC). Therefore, the soft start capacitor (CSS) not only controls the startup time but also the time between soft start attempts in hiccup mode. Hiccup mode operation is discussed in more detail in the Protection Features section of this datasheet. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output Pre-Biased Startup If the output of the regulator (VOUT) is pre-biased to some voltage, the ARG81801 will modify the normal startup routine to prevent discharging the output capacitors. As described previously, the error amplifier usually becomes active when the voltage at the soft start pin exceeds 400 mV. If the output is pre-biased, the FB pin will be at some non-zero voltage. The ARG81801 will not start switching until the voltage at the soft start pin increases to approximately VFB + 400 mV. When the soft start pin voltage exceeds this value, the error amplifier becomes active, the voltage at the COMP pin rises, PWM switching starts, and VOUT ramps upward from the pre-bias level. Figure 5 shows startup when the output voltage is pre-biased to 1.6 V. VSLEEP VOUT VOUT rises from 1.6 V, it is not pulled to 0 V threshold (TSD). For other faults, POK behavior depends on the output voltage. Table 1 summarizes all the ARG81801 fault modes and their effect on POK. At power-up, POK must be initialized (set to a logic low) when VIN is relatively low. Figure 6 shows VIN ramping up, and also POK being set to a logic low when VIN is only 2.2 V. For this test, POK was pulled up to an external 3.3 V supply via a 2 k resistor. At power-down, POK must be held in the logic low state as long as possible. Figure 7 shows VIN ramping down and also POK being held low until VIN is only 1.3 V. For this test, POK was pulled up to an external 3.3 V supply via a 2 k resistor. VIN = 2.2 V 3.3 V VSS=1.2 V 1.6 V Switching delayed until VSS = VFB +400 mV VIN VPOK VSS = 400 mV VCOMP VSS IL fOSC fOSC/2 Figure 6: Initialization of POK as VIN Ramps Up Figure 5: Pre-biased Startup from VOUT = 1.6V to VOUT = 3.3V, at IOUT = 1.6A Power OK (POK) Output The ARG81801 has a Power OK output (POK) with a fixed delay of its rising edge (td(POK)). The POK output is an open drain output so an external pull-up resistor must be used, as shown in the Typical Applications schematics. POK transitions high when the output voltage (VOUT), sensed at the FB pin, is within regulation. POK is high when the output voltage is typically within 92.5% to 110% of the target value. The POK overvoltage and undervoltage comparators incorporate a small amount of hysteresis (10 mV typically) and filtering (5 s typically) to help reduce chattering due to voltage ripple at the FB pin. The POK output is immediately pulled low either: if an output overvoltage or an undervoltage condition occurs, or if the ARG81801 junction temperature exceeds the thermal shutdown VIN = 1.3 V VIN VPOK Figure 7: POK being Held Low as VIN Ramps Down Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output Protection Features The ARG81801 was designed to satisfy the most demanding automotive and non-automotive applications. In this section, a description of each protection feature is described and Table 1 summarizes the protection features and operation. UNDERVOLTAGE LOCKOUT (UVLO) able at lower switching frequencies than higher frequencies. Figure 8 shows the typical and worst case min/max pulse-by-pulse current limits versus duty cycle at fOSC = 250 kHz and 2.45 MHz. If the synchronization input (SYNC) is used to increase the switching frequency, the on-time and the current ripple will decrease. This will allow slightly more current than at the base switching frequency (fOSC). An undervoltage lockout (UVLO) comparator monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage is below the stop threshold (VINUV(OFF)). The UVLO comparator incorporates some hysteresis (VINUV(HYS)) to help reduce on-off cycling of the regulator due to resistive or inductive drops in the VIN path during heavy loading or during startup. The exact current the buck regulators can support is heavily dependent on: duty cycle (VIN, VOUT, VF ), ambient temperature, thermal resistance of the PCB, airflow, component selection, and nearby heat sources. PULSE-BY-PULSE OVERCURRENT PROTECTION (OCP) An OCP counter and hiccup mode circuit protect the buck regulator when the output of the regulator is shorted to ground or when the load is too high. When the voltage at the soft start pin is below the hiccup OCP threshold (VHIC(EN)), the hiccup mode counter is disabled. Two conditions must be met for the OCP counter to be enabled and begin counting: The ARG81801 monitors the current in the high-side MOSFET and if the current exceeds the pulse-by-pulse overcurrent threshold (ILIM) then the high-side MOSFET is turned off. Normal PWM operation resumes on the next clock pulse from the oscillator. The ARG81801 includes leading edge blanking to prevent falsely triggering the pulse-by-pulse current limit when the highside MOSFET is turned on. ILIM (A) Because of the addition of the slope compensation ramp to the inductor current, the ARG81801 delivers more current at lower duty cycles and less current at higher duty cycles. Also, the slope compensation is not a perfectly linear function of switching frequency. For a given duty cycle, this results in a little more current being avail6.2 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 MIN_250kHz TYP_250kHz MAX_250kHz MIN_2.45MHz TYP_2.45MHz MAX_2.45MHz 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Duty Cycle (%) Figure 8: Pulse-by-Pulse Current Limit versus Duty Cycle At fOSC = 250 kHz (dashed lines) and fOSC = 2.45 MHz (solid lines) OVERCURRENT PROTECTION (OCP) AND HICCUP MODE * VSS > VHIC(EN) (2.3 V (typ)) and * VCOMP is clamped at its maximum voltage (OCL = 1) As long as these two conditions are met, the OCP counter remains enabled and will count pulses from the overcurrent comparator. If the COMP pin voltage decreases (OCL = 0) the OCP counter is cleared. If the OCP counter reaches OCPLIM counts (120), a hiccup latch is set and the COMP pin is quickly pulled down by a relatively low resistance (1 k). The hiccup latch also enables a small current sink connected to the soft start pin (ISS(HIC)). This causes the voltage at the soft start pin to slowly ramp downward. When the voltage at the soft start pin decays to a low enough level (VSS(RST), 200 mV (typ)), the hiccup latch is cleared and the small current sink turned off. At that instant, the soft start pin will begin to source current (ISS(SU)) and the voltage at the soft start pin will ramp upward. This marks the beginning of a new, normal soft start cycle as described earlier. (Note: OCP is the only fault that results in hiccup mode that is ignored when VSS < 2.3 V.) When the voltage at the soft start pin exceeds the soft start offset (typically 400 mV), the error amplifier forces the voltage at the COMP pin to quickly slew upward and PWM switching will resume. If the short circuit at the regulator output remains, another hiccup cycle will occur. Hiccups will repeat until the short circuit is removed or the regulator is disabled. If the short circuit is removed, the ARG81801 will soft start normally and the output voltage will automatically recover to the target level, as shown in Figure 9. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 16 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 Short removed VOUT VCOMP 120 OCP counts VSS IL chronous diode is short-circuited, the ARG81801 will experience extremely high currents in the high-side MOSFET. If this occurs, the ARG81801 will enter hiccup mode after detecting one shortcircuited diode fault. OVERVOLTAGE PROTECTION (OVP) The ARG81801 provides a basic level of overvoltage protection by monitoring the voltage level at the FB pin. Two overvoltage conditions can be detected: 2.3 V ILIM(TONMIN) 200 mV Figure 9: Hiccup Mode Operation and Recovery to VOUT = 3.3V, IOUT = 1.6A BOOT CAPACITOR PROTECTION The ARG81801 monitors the voltage across the BOOT capacitor to detect if the capacitor is missing or short-circuited. If the BOOT capacitor is missing, the regulator will enter hiccup mode after 7 PWM cycles. If the BOOT capacitor is short-circuited, the regulator will enter hiccup mode after 120 PWM cycles, provided there is no VOUT overvoltage detection. At no load or very light loads, the boot charging circuit will increase the output voltage (via the output inductor) and cause an overvoltage condition to be detected if VIN > VOUT + 5.7 V. For a boot fault, hiccup mode will operate virtually the same as described previously for an output short circuit fault (OCP) with the soft start pin ramping up and down as a timer to initiate repeated soft start attempts. Boot faults are a non-latched condition, so the ARG81801 will automatically recover when the fault is corrected. ASYNCHRONOUS DIODE PROTECTION If the asynchronous diode (D1 in the Typical Applications schematics) is missing or damaged (open), the SW pin will be subject to unusually high negative voltages. These negative voltages may cause the ARG81801 to malfunction and could lead to damage. The ARG81801 includes protection circuitry to detect when the asynchronous diode is missing. If the SW pin is below typically -1.25 V for more than 50 ns, the ARG81801 will enter hiccup mode after detecting one missing diode fault. Also, if the asyn- * The FB pin is disconnected from its feedback resistor divider. In this case, a tiny internal current source forces the voltage at the FB pin to rise. When the voltage at the FB pin exceeds the overvoltage threshold (VOUT(OV), 880 mV (typ)), PWM switching will stop and POK will be pulled low. * A higher, external voltage supply is accidently shorted to the ARG81801's output. VFB will probably rise above the overvoltage threshold and be detected as an overvoltage condition. In this case, the low-side MOSFET will continue to operate and can correct the OVP condition, provided that only a few milliamperes of pull-down current are required. In either case, if the condition causing the overvoltage is corrected, the regulator will automatically recover. PIN-TO-GROUND AND PIN-TO-PIN SHORT PROTECTIONS The ARG81801 is designed to satisfy the most demanding automotive applications. For example, the ARG81801 has been carefully designed from the very beginning to withstand a short circuit to ground at each pin without suffering damage. In addition, care was taken when defining the ARG81801 pin-out to optimize protection against pin-to-pin adjacent short circuits. For example, logic pins and high voltage pins are separated as much as possible. Inevitably, some low voltage pins are located adjacent to high voltage pins, but in these instances the low voltage pins are designed to withstand increased voltages, with clamps and/or series input resistance, to prevent damage to the ARG81801. THERMAL SHUTDOWN (TSD) The ARG81801 monitors junction temperature and will stop PWM switching and pull POK low if it becomes too hot. Also, to prepare for a restart, the soft start and COMP pins will be pulled low until VSS < VSS(RST). TSD is a non-latched fault, so the ARG81801 will automatically recover if the junction temperature decreases by approximately 20C. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 17 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output Table 1: Summary of ARG81801 Fault Modes and Operation During Fault Counting, before Hiccup Mode BOOT Charging POK State Latched? Reset Condition Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after remove the short fOSC / 4 due to VFB > 400 mV, responds to VCOMP Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after decrease load current Pulled low for hiccup Forced off when BOOTOV fault occurs Forced off when BOOT fault occurs Off after BOOT fault occurs Depends on VOUT No Automatic, after replace capacitor Hiccup, after 120 BOOTUV faults Not affected, pulled low for hiccup Forced off when BOOTUV fault occurs Forced off only during hiccup Off only during hiccup Depends on VOUT No Automatic, after unshort capacitor Asynchronous diode missing Hiccup after 1 fault Pulled low for hiccup Forced off after 1 fault Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after install diode Asynchronous diode (or SW) hard short to ground Hiccup after 1 fault Pulled low for hiccup Forced off after 1 fault Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after remove the short Asynchronous diode (or SW) soft short to ground Hiccup, after 120 OCP faults Clamped for ILIM, then pulled low for hiccup Active, responds to VCOMP Can be activated if VBOOT is too low Not affected Depends on VOUT No Automatic, after remove the short FB pin open (FB floats high) Begins to ramp up for soft start Transitions low via loop response Forced off by low VCOMP Active during tOFF(MIN) Off when VFB is too high Pulled low when VFB is too high No Automatic, after connect FB pin Output overvoltage (VFB > 880mV) Not affected Transitions low via loop response Forced off by low VCOMP Active during tOFF(MIN) Off when VFB is too high Pulled low when VFB is too high No Automatic, after VFB returns to normal range Output undervoltage (VFB < 740mV) Not affected Transitions high via loop response Active, responds to VCOMP Can be activated if VBOOT is too low Not affected Pulled low when VFB is too low No Automatic, after VFB returns to normal range Thermal shutdown Pulled low and latched until VSS < VSS(RST) Pulled low and latched until VSS < VSS(RST) Forced off by low VCOMP Disabled Off Pulled low No Automatic, after part cools down Fault Mode VSS Output overcurrent, VFB< 200 mV VCOMP High-Side MOFSET Low-Side MOFSET Hiccup, after 120 OCP faults Clamped for ILIM, then pulled low for hiccup fOSC / 4 due to VFB < 200 mV, responds to VCOMP Output overcurrent, VFB > 400 mV Hiccup, after 120 OCP faults Clamped for ILIM, then pulled low for hiccup Boot capacitor open/missing (BOOTOV) Hiccup, after 7 BOOTOV faults Boot capacitor shorted (BOOTUV) Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 18 COMP SS VOUT SW VIN DIODE FAULT BOOT FAULT OC FAULT HICCUP OC HIC_EN POK TSD SYNC MODE OFF fOSC/4 then fOSC/2 SS 20 s fOSC O C HICCUP fOSC/4 x120 VOUT shorted to GND PWM fOSC/4 SS x120 OC HICCUP fOSC/4 then fOSC/2 SS 20 s fOSC PWM HICCUP x7 OV x120 UV BOOT FAULTS S S TO 2.3 V FRO M 2.3 V x7 OV x120 UV HICC UP fOSC/4 then fOSC/2 SS 20 s fOSC PWM HICCUP x1 DIODE or SW FAULTS x1 TO 2.3 V HI C FRO M 2.3 V fOSC/4 SS fOSC/4 then fOSC/2 SS 20 s fOSC PWM TSD fOSC/4 then fOSC/2 SS 20 s fOSC PWM ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output Figure 10: Operation with SLEEP = 1 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 19 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 APPLICATION INFORMATION Design and Component Selection SETTING THE OUTPUT VOLTAGE (V OUT) VOUT RFB1 FB PIN 2.50 2.25 2.00 1.75 Frequency (MHz) The output voltage of the regulator is determined by connecting a resistor divider from the output node (VOUT) to the FB pin as shown in Figure 11. If the parallel combination (RFB1 // RFB2) is too high, then the regulator may be susceptible to noise coupling onto the FB pin. Allegro recommends a parallel combination in the range 1 to 4 k. 1.50 1.25 1.00 0.75 0.50 RFB2 0.25 0.00 5.0 Figure 11: Connecting a Feedback Resistor Divider to Set the Output Voltage 15.0 25.0 35.0 45.0 55.0 65.0 75.0 85.0 95.0 RFSET (k) Figure 12: PWM Switching Frequency versus RFSET The feedback resistors must satisfy the ratio shown in the following equation to produce the target output voltage, VOUT: RFB1 = RFB2 VOUT -1 0.8 (V) (1) PWM BASE SWITCHING FREQUENCY (fOSC, RFSET) The PWM base switching frequency, fOSC, is set by connecting a resistor from the FSET pin to ground. Figure 12 is a graph showing the relationship between the typical switching frequency and the FSET resistor. For a given base frequency (fOSC), the FSET resistor can be calculated as follows: RFSET = 26385 - 2.75 fOSC (2) where fOSC is in kHz and RFSET is in k. When the PWM base switching frequency is chosen, the designer should be aware of the minimum controllable on-time, tON(MIN) of the ARG81801. If the system required on-time is less than the ARG81801 minimum controllable on-time, switch node jitter occurs and the output voltage will have increased ripple or oscillations. The PWM base switching frequency required should be calculated as follows: fOSC < VOUT tON(MIN) x VIN(MAX) where (3) VOUT is the output voltage, tON(MIN) is the minimum controllable on-time, and VIN(MAX) is the maximum required operational input voltage (not the peak surge voltage, i.e. load dump voltage). If the ARG81801 synchronization function is employed, then the base switching frequency should be chosen such that jitter will not result at the maximum synchronized switching frequency, determined from equation 4: fOSC < 0.66 x VOUT tON(MIN) x VIN(MAX) Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com (4) 20 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 OUTPUT INDUCTOR (L O) For a peak current mode regulator, it is common knowledge that without adequate slope compensation, the system will become unstable when the duty cycle is near or above 50%. However, the slope compensation in the ARG81801 is a fixed value (SE). Therefore, it is important to calculate an inductor value such that the falling slope of the inductor current (SF) will work well with the ARG81801 slope compensation. The following equation can be used to calculate a range of values for the output inductor based on the well-known approach of providing slope compensation that matches 50% to 100% of the falling slope of the inductor current: VOUT + VF 2 x SE LO VOUT + VF SE (5) where VF is the forward voltage of the asynchronous diode, and LO is in H. In equation 5, the slope compensation (SE) is a function of switching frequency according the following: SE = 0.253 x f2OSC + 0.726 x fOSC + 0.021 (6) where SE is in A/s and fOSC is in MHz. More recently, Dr. Raymond Ridley presented a formula to calculate the amount of slope compensation required to critically damp the double poles at half the PWM switching frequency: LO = (ILIM(TON,MIN)), 6.1AMAX. This may be too costly. At the very least, the inductor should not saturate at the peak operating current according to the following equation: IPEAK = 6.1 - SE x (VOUT +VF) 1.15 x fOSC x (VIN(max)+VF ) (8) where VIN(MAX) is the maximum continuous input voltage, such as 18 V (not a surge voltage, such as 40 V). Starting with equation 8, and subtracting half of the inductor ripple current, provides an interesting equation to predict the typical DC load capability of the regulator at a given duty cycle (D): IOUT(DC) = 6.1 - SEx D fOSC VOUT x (1- D) 2 x fOSC x LO (9) After an inductor is chosen, it should be tested during output short circuit conditions. The inductor current should be monitored using a current probe. A good design would ensure neither the inductor nor the regulator are damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. OUTPUT CAPACITORS VOUT + VF 1 - 0.18 D SE The output capacitors filter the output voltage to provide an acceptable level of ripple voltage and they store energy to help maintain voltage regulation during a load transient. The voltage rating of the output capacitors must support the output voltage with sufficient design margin. (VIN(MIN) +VF) VOUT + VF 1 - 0.18 x VOUT+VF SE The output voltage ripple (VOUT) is a function of the output capacitor parameters: COUT, ESRCOUT, and ESLCOUT: (7) This formula allows the inclusion of the duty cycle (D), which should be calculated at the minimum input voltage to ensure optimal stability. Also, to avoid dropout (that is, saturation of the buck regulator), VIN(MIN) must be approximately 1 to 1.5 V above VOUT when calculating the inductor value. If equations 5 or 7 yield an inductor value that is not a standard value, then the next highest available value should be used. The final inductor value should allow for 10% to 20% of initial tolerance and 20% to 30% of inductor saturation. The saturation current of the inductor should be higher than the peak current capability of the ARG81801. Ideally, for output short circuit conditions, the inductor should not saturate given the highest pulse-by-pulse current limit at minimum duty cycle VOUT = IL x ESRCOUT VIN - VOUT x ESLCOUT LO IL + 8 x fSW x C OUT + (10) The type of output capacitors will determine which terms of equation 10 are dominant. For ceramic output capacitors, the ESRCOUT and ESLCOUT are virtually zero, so the output voltage ripple will be dominated by the third term of equation 11: VOUT = IL 8 x fSW x C OUT Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com (11) 21 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output To reduce the voltage ripple of a design using ceramic output capacitors, simply increase the total capacitance, reduce the inductor current ripple (that is, increase the inductor value), or increase the switching frequency. bandwidth system, it may be more difficult to obtain acceptable gain and phase margins. Selection of the compensation components (RZ, CZ, and CP) are discussed in more detail in the Compensation Components section of this datasheet. For electrolytic output capacitors, the value of capacitance will be relatively high, so the third term in equation 10 will be very small. The output voltage ripple will be determined primarily by the first two terms of equation 10: INPUT CAPACITORS VOUT = IL x ESRCOUT VIN -VOUT LO x ESLCOUT (12) To reduce the voltage ripple of a design using electrolytic output capacitors, simply decrease the equivalent ESRCO and ESLCO by using a high(er) quality capacitor, or add more capacitors in parallel, or reduce the inductor current ripple (that is, increase the inductor value). The ESR of some electrolytic capacitors can be quite high so Allegro recommends choosing a quality capacitor for which the ESR or the total impedance is clearly documented in the datasheet. Also, the ESR of electrolytic capacitors usually increases significantly at cold ambients, as much as 10x, which increases the output voltage ripple and, in most cases, reduces the stability of the system. The transient response of the regulator depends on the quantity and type of output capacitors. In general, minimizing the ESR of the output capacitance will result in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. At the instant of a fast load transient (di/dt), the output voltage will change by the amount: di x ESLCOUT VOUT = ILOAD x ESRCOUT + dt The input capacitors must deliver the rms current according to: Irms = IOUT D x (1- D) (14) where the duty cycle is: D (VOUT + VF ) / (VIN + VF)(15) and VF is the forward voltage of the asynchronous diode, D1. Figure 13 shows the normalized input capacitor rms current versus duty cycle. To use this graph, simply find the operational duty cycle (D) on the x-axis and determine the input/output current multiplier on the y-axis. For example, at a 20% duty cycle, the input/output current multiplier is 0.40. Therefore, if the regulator is delivering 3.0 A of steady-state load current, the input capacitor(s) must support 0.40 x 3.0 A, or 1.2 Arms. 0.55 0.50 0.45 (13) After the load transient occurs, the output voltage will deviate from its nominal value for a short time. This time will depend on the system bandwidth, the output inductor value, and output capacitance. Eventually, the error amplifier will bring the output voltage back to its nominal value. The speed at which the error amplifier brings the output voltage back to its setpoint depends mainly on the closed-loop bandwidth of the system. A higher bandwidth usually results in a shorter time to return to the nominal voltage. However, with a higher 0.40 Ir m s / IOUT + Three factors should be considered when choosing the input capacitors. First, they must be chosen to support the maximum expected input surge voltage with adequate design margin. Second, the capacitor rms current rating must be higher than the expected rms input current to the regulator. Third, they must have enough capacitance and a low enough ESR to limit the input voltage dV/dt to something much less than the hysteresis of the VIN pin UVLO circuitry (VINUV(HYS), nominally 400 mV for the ARG81801), at maximum loading and minimum input voltage. 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) Figure 13: Input Capacitor Ripple versus Duty Cycle Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 22 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output The input capacitor(s) must limit the voltage deviations at the VIN pin to something significantly less than the ARG81801 UVLO hysteresis during maximum load and minimum input voltage. The minimum input capacitance can be calculated as follows: IOUT x D x (1- D) CIN 0.85 x fOSC x VIN(MIN) (16) where VIN(MIN) is chosen to be much less than the hysteresis of the VIN pin UVLO comparator (VIN(MIN) 150 mV is recommended). The D x (1-D) term in equation 16 has an absolute maximum value of 0.25 at 50% duty cycle. So, for example, a very conservative design, based on: IOUT = 3.0 A, fOSC = 85% of 425 kHz, D x (1-D) = 0.25, and VIN = 150 mV, yields: CIN 3.0 (A) x 0.25 = 13.8 F 361 (kHz) x 150 (mV) A good design should consider the DC bias effect on a ceramic capacitor: as the applied voltage approaches the rated value, the capacitance value decreases. This effect is very pronounced with the Y5V and Z5U temperature characteristic devices (as much as 90% reduction) so these types should be avoided. The X5R and X7R type capacitors should be the primary choices due to their stability versus both DC bias and temperature. For all ceramic capacitors, the DC bias effect is even more pronounced on smaller sizes of device case, so a good design uses the largest affordable case size (such as 1206 or 1210). Also, it is advisable to select input capacitors with plenty of design margin in the voltage rating to accommodate the worst case transient input voltage (such as a load dump as high as 40 V for automotive applications). ASYNCHRONOUS DIODE (D1) There are three requirements for the asynchronous diode. First, the asynchronous diode must be able to withstand the regulator input voltage when the high-side MOSFET is on. Therefore, one should choose a diode with a reverse voltage rating (VR) higher than the maximum expected input voltage (that is, the surge voltage). Second, the forward voltage of the diode (VF) should be minimized or the regulator efficiency suffers. Also if VF is too high, the ARG81801 missing diode protection function could be falsely activated. A Schottky-type diode that can maintain a very low VF when the regulator output is shorted to ground--at the coldest ambient temperature--is highly recommended. Third, the asynchronous diode must conduct the output current when the high-side MOSFET is turned off. Therefore, the average forward current rating of this diode (IF(AVG)) must be high enough to deliver the load current according to: IF(AVG) IOUT(MAX) ( 1 - DMIN )(17) where DMIN = (VOUT + VF) / (VIN(MAX) + VF), VIN(MAX) is the maximum required operational input voltage (not the peak surge voltage), and IOUT(MAX) is the maximum continuous ouput current of the regulator. BOOTSTRAP CAPACITOR A bootstrap capacitor must be connected between the BOOT and SW pins to provide the floating gate drive to the high-side MOSFET. Usually, 47 nF is an adequate value. This capacitor should be a high-quality ceramic capacitor, such as an X5R or X7R, with a voltage rating of at least 16 V. The ARG81801 incorporates a 10 low-side MOSFET to ensure that the bootstrap capacitor is always charged, even when the regulator is lightly loaded or pre-biased. SOFT START AND HICCUP MODE TIMING (C SS) The soft start time of the ARG81801 is determined by the value of the capacitance at the soft start pin, CSS. When the ARG81801 is enabled, the voltage at the soft start pin starts from 0 V and is charged by the soft start current, ISS(SU). However, PWM switching does not begin instantly because the voltage at the soft start pin must rise above 400 mV. The soft start delay (td(SS)) can be calculated as: td(SS) = CSS x 400 (mV) ISS(SU) (18) If the ARG81801 is starting with a very heavy load, a very fast soft start time may cause the regulator to exceed the pulse-bypulse overcurrent threshold. This occurs because the total of the full load current, the inductor ripple current, and the additional current required to charge the output capacitors, ICO = COUT x VOUT / tSS (19) is higher than the pulse-by-pulse current threshold, as shown in Figure 14. This phenomenon is more pronounced when using high value electrolytic-type output capacitors. To avoid prematurely triggering hiccup mode, the soft start capacitor, CSS, should be calculated according to: Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 23 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 CSS COMPENSATION COMPONENTS (R Z, C Z, AND C P) ISS(SU)x VOUT x COUT 0.8 (V) x ICO (20) where VOUT is the output voltage, COUT is the output capacitance, ICO is the amount of current allowed to charge the output capacitance during soft start (recommended: 0.1 A < ICO < 0.3A). Higher values of ICO result in faster soft start times. However, lower values of ICO ensure that hiccup mode is not falsely triggered. Allegro recommends starting the design with an ICO of 0.1 A and increasing it only if the soft start time is too slow. If a non-standard capacitor value for CSS is calculated, the next larger value should be used. The output voltage ramp time, tSS, can be calculated by using either of the following methods: tSS = VOUT x or COUT ICO tSS = 0.8 (V) x CSS I SS(SU) (21) When the ARG81801 is in hiccup mode, the soft start capacitor is used as a timing capacitor and sets the hiccup period. The soft start pin charges the soft start capacitor with ISS(SU) during a startup attempt and discharges the same capacitor with ISS(HIC) between startup attempts. Because the ratio ISS(SU) / ISS(HIC) is approximately 4:1, the time between hiccups will be about four times as long as the startup time. Therefore, the effective duty cycle of the ARG81801 will be very low and the junction temperature will be kept low. } ILIM AVDC = RL x gmPOWER x AVOL x VFB VOUT (22) where RL is the load resistance in (VOUT/IOUT), gmPOWER is the COMP to SW current gain (4.0 A/V), and AVOL is the error amplifier voltage gain (65dB, or 1778 V/V). The system has two noteworthy poles at low frequency. One is due to the compensation capacitor (CZ) and the error amplifier output resistance, the other is due to the output capacitor (COUT) and the load resistance. These poles are located at: gm 1 = fP1 = 2 x CZ x RO 2 x CZ x AVOL (23) fP2 = 1 2 x COUT x RL (24) where gm is the error amplifier transconductance, 750A/V. The system has one noteworthy zero. This is due to the compensation capacitor (CZ) and the compensation resistor (RZ). This zero is located at: 1 fZ1 = 2 x RZ x CZ (25) A third, high frequency pole is set by the compensation capacitor (CP) and the compensation resistor (RZ). This pole is located at: ILOAD tSS The ARG81801 employs current-mode control for easy compensation and fast transient response. The system stability and transient response are controlled through the COMP pin. The COMP pin is the output of the internal transconductance error amplifier. A series capacitor-resistor combination sets a pole-zero pair to control the characteristics of the control system. The DC voltage gain, AVDC, of the complete feedback loop is given by: Output capacitor current, I CO Figure 14: Output Capacitor Current (ICO) During Startup fP3 = 1 2 x CP x RZ (26) With ceramic output capacitors, fP3 should be set to limit the high frequency gain of the loop by placing a pole 5x to 10x higher than the 0dB crossover frequency. Limiting the high frequency gain of the loop usually helps reduce pulse width jitter. The goal of compensation design is to shape the converter transfer function to obtain a desired loop gain. The system crossover frequency (fC) where the feedback loop has unity gain is important. Lower crossover frequencies result in slower load and line transient responses, while higher crossover frequencies could Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 24 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 cause the system to be unstable. A good rule of thumb is to set the crossover frequency of a 2MHz regulator below 100kHz. For a 400kHz regulator, the crossover frequency should be set below 50kHz. The following procedure can be used to calculate the compensation components. 1. Calculate the compensation resistor (RZ) to set the desired crossover frequency (fC) using the following formula: RZ = VOUT 2 x COUT x fC x gm x gmPOWER VFB (27) 2. Choose the compensation capacitor (CZ) to achieve the desired phase margin. For most applications, setting the compensation zero (fZ1) below one-fourth of the crossover frequency provides sufficient phase margin. Determine the CZ value by the following equation: CZ 4 2 x RZ x fC (28) To maximize stability (that is, to have the greatest phase margin), use a higher value of CZ. To optimize transient recovery time, although at the expense of some phase margin, use a lower value of CZ. Figure 15 compares the output voltage recovery time due to a 1A load transient for a system with fZ2 at 4.5kHz with 63 phase margin versus 15kHz with 51 phase margin. The system with the higher frequency zero has less phase margin but recovers about 3 times faster than the other system. 3. Lastly, set the high frequency pole at 5 x fC using the following equation: CP = 1 2 x RZ x 5 x fC (29) This should be a good starting value for CP. Decreasing CP will improve phase margin slightly, but may result in increased pulse width jitter. Table 2 lists typical values of compensation components for a high frequency, high output voltage and a low frequency, low output voltage design with recommended output ceramic capacitors and inductors. The output capacitances and bandwidths were chosen to support 0.5 to 3A load transients at approximately 125mA/s. As shown in Figure 16a and Figure 16b, the output voltage deviates about 4% during the load transients and fully recovers in less than 65s. For reduced load transients, the output capacitance can be decreased, but the compensation components must be recalculated to maintain good stability margins. Table 2: Typical Component Values for 2.5A Load Steps VOUT / fOSC (V / kHz) LOUT (H) COUT (F) RZ (k) CZ (nF) CP (pF) 5.0 / 2100 3.3 20 20 1.0 15 1.25 / 410 10 188 30.1 0.68 15 5.00 fZ2 = 15 kHz 4.99 Voltage (V) 4.98 fZ2 = 4.5 kHz 4.97 4.96 4.95 4.94 4.93 0 40 80 120 Time (s) 160 200 240 Figure 15: Transient Recovery Comparison Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 25 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output Figure 16a: 0.5to 3A Load Transient - 12 VIN, 5 VOUT, 2.1 MHz Figure 16b: 0.5 to 3A Transient - 12 VIN, 1.25 VOUT, 410kHz Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 26 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output POWER DISSIPATION AND THERMAL CALCULATIONS The power dissipated in the ARG81801 is the sum of the power dissipated from the VIN supply current (PIN), the power dissipated due to the switching of the high-side power MOSFET (PSW), the power dissipated due to the rms current being conducted by the internal MOSFET (PCOND), and the power dissipated by the internal gate driver (PDRIVERS). The power dissipated from the VIN supply current can be calculated using equation 30, where VIN is the input voltage, IQ is the input quiesent current drawn by the ARG81801 (nominally 2.5mA), VGS is the MOSFET gate drive voltage (typically 5V), QG is the internal MOSFET gate charge (approximately 2.5nC), and fOSC is the PWM switching frequency. PIN = VIN x IQ + (VIN - VGS) x QG x fOSC(30) The power dissipated by the internal high-side MOSFET during PWM switching can be calculated using Equation 31, where VIN is the input voltage, IOUT is the regulator output current, fOSC is the PWM switching frequency, and tr and tf are the rise and fall times measured at the SW node. The exact rise and fall times at the SW node will depend on the external components and PCB layout, so each design should be measured at full load. Approximate values for both tr and tf range from 5 to 10ns. PSW = VIN x IOUT x (tr + tf ) x fSW 2 (31) The power dissipated by the internal high-side MOSFET while it is conducting can be calculated using equation 32, where IOUT is the regulator output current, IL is the peak-to-peak inductor ripple current, RDS(on) is the on resistance of the high-side MOSFET, and VF is the forward voltage of the asynchronous diode, PCOND = Irms(FET)2 x RDS(on) 2 VOUT +VF 2 IL I x RDS(on) = x OUT + 12 VIN +VF The RDS(on) of the high-side MOSFET will have some initial tolerance plus an increase from self-heating and elevated ambient temperatures. A conservative design should accommodate an RDS(on) with at least a 15% initial tolerance plus 0.39%/C increase due to temperature. The power dissipated by the internal gate driver can be calculated using equation 33, where VGS is the gate drive voltage (typically 5V), QG is the gate charge to drive the internal MOSFET to VGS=5V (about 2.5nC), and fOSC is the PWM switching frequency: PDRIVER = QG x VGS x fOSC(33) Finally, the total power dissipated by the ARG81801 (PTOTAL) is the sum of the previous equations, PTOTAL = PIN + PSW + PCOND + PDRIVER(34) The average junction temperature can be calculated with the equation 35, where PTOTAL is the total power dissipated from equation 34, RJA is the junction-to-ambient thermal resistance (37C/W on a 4-layer PCB), and TA is the ambient temperature, TJ = PTOTAL + RJA + TA(35) The maximum junction temperature will be dependent on how efficiently heat can be transferred from the PCB to ambient air. It is critical that the thermal pad on the bottom of the IC should be connected to a at least one ground plane using multiple vias. As with any regulator, there are limits to the amount of heat that can be dissipated before risking thermal shutdown. There are tradeoffs between ambient operating temperature, input voltage, output voltage, output current, switching frequency, PCB thermal resistance, airflow, and other nearby heat sources. Even a small amount of airflow will reduce the junction temperature considerably. (32) Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 27 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output PCB COMPONENT PLACEMENT AND ROUTING A good PCB layout is critical if the ARG81801 is to provide clean, stable output voltages. Follow these guidelines to insure a good PCB layout. Figure 17 shows a typical buck converter schematic with the critical power paths/loops. Figure 18 shows an example PCB component placement and routing with the same critical power paths/loops as shown in the schematic. 1. By far, the highest di/dt in the asynchronous buck regulator occurs at the instant the high-side MOSFET turns on and the capacitance of the asynchronous Schottky diode is quickly charged to VIN. The ceramic input capacitors must deliver this fast, short pulse of current. Therefore the loop, from the ceramic input capacitors through the high-side MOSFET and into the asynchronous diode to ground, must be minimized. Ideally these components are all connected using only the top metal layer (that is, do not use vias to other power/signal layers). 2. When the upper FET is off, free-wheeling current flows from ground, through the asynchronous diode, into the load via the output inductor, and back to ground. This loop should be minimized and have relatively wide traces. 3. When the high-side MOSFET is on, current flows from the input supply and capacitors, through the high-side MOSFET, into the load via the output inductor, and back to ground. This loop should be minimized and have relatively wide traces. 4. The voltage on the SW node transitions from 0 V to VIN very quickly and is the root cause of many noise issues. It is best to place the asynchronous diode and output inductor close to the ARG81801 to minimize the size of the SW polygon. Also, keep low-level analog signals (like FB and COMP) away from the SW polygon. 5. Place the feedback resistor divider (RFB1 and RFB2) very close to the FB pin. Ground this resistor divider as close as possible to the ARG81801. 6. To have the highest output voltage accuracy, the output voltage sense trace (from VOUT to RFB1) should be connected as close as possible to the load. 7. Place the compensation components (RZ, CZ, and CP) as close as possible to the COMP pin. Place vias to the GND plane as close as possible to these components. 8. Place the bootstrap capacitor (CBOOT) near the BOOT pin and keep the routing from this capacitor to the SW polygon as short as possible. 9. When connecting the input and output ceramic capacitors, use multiple vias to GND and place the vias as close as possible to the pads of the components. 10.To minimize PCB losses and improve system efficiency, the input and output traces should be as wide as possible and be duplicated on multiple layers, if possible. 11. The thermal pad under the ARG81801 must connect to the GND plane using multiple vias. More vias will ensure the lowest junction temperature and highest efficiency. 12. EMI/EMC issues are always a concern. Allegro strongly recommends having component locations for an RC snubber from SW to ground. The resistor should be 1206 size and connect directly to the ground plane to aid thermal dissipation. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 28 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 BOOT CBOOT VIN LOUT VOUT SW DOUT CIN COUT GND Figure 17: Buck Regulator Circuit with Critical Paths/Loops Shown "Hot Loop" (Blue): To minimize radiated emissions (RE), the loop area from CIN, through the high-side MOSFET (M1), asynchronous diode (DOUT), to ground directly at CIN must be minimized. These components should be placed on the same side of the PCB--this loop should not use vias to make the connections. Figure 18: Recommended Component Placement and Routing The area of the Hot Loop, shown in blue, must be minimized. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 29 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output ARG81801 PACKAGE OUTLINE DRAWING For Reference Only - Not for Tooling Use (Reference JEDEC MO-220WGGD) Dimensions in millimeters - NOT TO SCALE Exact case and lead configuration at supplier discretion within limits shown 0.30 0.50 4.00 0.10 24 24 0.90 1 1 A 2 2 4.00 0.10 2.20 DETAIL A 24X 2.20 D 0.08 4.10 C 0.75 0.05 C 0.22 0.05 4.10 SEATING PLANE C PCB Layout Reference View 0.0-0.05 0.50 BSC 0.14 REF 0.20 REF 0.40 0.10 0.10 REF 0.05 REF 0.203 REF 0.40 0.10 0.05 REF B Detail A 2.10 0.10 2 1 0.55 REF 24 2.10 0.10 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 0.10 REF Figure 19: Package ES, 24-pin wettable flank QFN with exposed thermal pad Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 30 ARG81801 Wide Input Voltage, 2.4 MHz, 3.0 A Asynchronous Buck Regulator with Sleep Mode, External Synchronization, and POK Output Revision History Number Date Description - February 2, 2018 1 March 20, 2018 Minor editorial updates 2 February 11, 2019 Minor editorial updates Initial release Copyright (c)2019, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 31