PRELIMINARY
1-Mbit (128K x 8) Static RAM
CY7C1019D
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-05464 Rev. *C Revised January 11, 2005
Features
• Pin- and function-compatible with CY7C1019B
•High speed
—t
AA = 10 ns
• CMOS for optimum speed/po we r
• Low active pow er
—I
CC = 60 mA @ 10 ns
• Low CMOS standby power
—I
SB2 = 1.2 mA (‘L’ Version only)
• Data Retention at 2.0V
• Center power/ground pinout
• Automatic power-down wh en deselected
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019B
• Available in Pb-F ree Packages
Functional Description[1]
The CY7C1019D is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight
I/O pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a wri te
operation (CE LOW, and WE LOW).
The CY7C1019D is available in standard 32-pin TSOP Type
II and 400-mil-wide SOJ Pb-Free packages.
Note:
1. For guidelines on SRAM syste m design, please refe r to the ‘ System Design Guidelin es’ Cypress applicatio n note, availa ble on t he inter net at www .cypress.com.
14
15
Logic Block Diagram Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMP S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15 17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
A
13
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
10
A
9
I/O
2
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
A
8
I/O
3
WE
V
SS
A
14
V
SS
/TSOPII
PRELIMINARY CY7C1019D
Document #: 38-05464 Rev. *C Page 2 of 9
Selection Guide
CY7C1019D-10 CY7C1019D-12 Unit
Maximum Access Time 10 12 ns
Maximum Operating Current 60 50 mA
Maximum Standby Current 3 3 mA
L1.21.2
PRELIMINARY CY7C1019D
Document #: 38-05464 Rev. *C Page 3 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[2] ....–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z S tate[2]....................................–0.5V to VCC + 0.5V
DC Input V oltage[2].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW ).........................................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
7C1019D-10 7C1019D-12
UnitMin. Max. Min. Max.
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC
+ 0.3 2.0 VCC
+ 0.3 V
VIL Input LOW Voltage[2] –0.5 0.8 –0.5 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND < VI < VCC,
Output Disabled –1 +1 –1 +1 µA
ICC VCC Operating
Supply Current VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC 60 50 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
10 10 mA
L1010
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
3.0 3.0 mA
L1.21.2
Capacitance[3]
Parameter Description Test Co nditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 6pF
COUT Output Capacitance 8 pF
Thermal Resistance[3]
Parameter Description Test Con ditio ns All - Packages Unit
ΘJA Thermal Resistance
(Junction to Ambient)[3] Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board TBD °C/W
ΘJC Thermal Resistance
(Junction to Case)[3] TBD °C/W
Notes:
2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
PRELIMINARY CY7C1019D
Document #: 38-05464 Rev. *C Page 4 of 9
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
(c)
≤ 3 ns ≤3ns
OUTPUT
R1 480Ω
R1 480Ω
R2
255Ω
R2
255Ω
167Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
OUTPUT Z = 50Ω
50Ω
1.5V
(a)
10-ns Devices 12 -ns Devices
High-Z characteristics:
Switching Characteristics Over the Operating Range[5]
Parameter Description
7C1019D-10 7C1019D-12
UnitMin. Max. Min. Max.
Read Cycle
tpower[4] VCC(typical) to the first access 100 100 µs
tRC Read Cycle Time 10 12 ns
tAA Address to Data Valid 10 12 ns
tOHA Data Hold from Address Change 3 3 ns
tACE CE LOW to Data Valid 10 12 ns
tDOE OE LOW to Data Va lid 5 6 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 56ns
tLZCE CE LOW to Low Z[7] 33ns
tHZCE CE HIGH to High Z[6, 7] 56ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 10 12 ns
Write Cycle[8, 9]
tWC Write Cycle Time 10 12 ns
tSCE CE LOW to Write End 8 9 ns
tAW Address Set-Up to Write End 7 8 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 7 8 ns
tSD Data Set-Up to Write End 5 6 ns
Notes:
4. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE ar e specified with a lo ad capacit ance of 5 pF as in (b ) of AC Test Loads. T ransitio n is measured ±200 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the me mory is define d by t he overlap o f CE LOW and WE LOW . CE and WE must be LOW to initiate a writ e, and the tr ansition o f a ny of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminat es the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
PRELIMINARY CY7C1019D
Document #: 38-05464 Rev. *C Page 5 of 9
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[7] 33ns
tHZWE WE LOW to High Z[6, 7] 56ns
Switching Characteristics Over the Operating Range (continued)[5]
Parameter Description
7C1019D-10 7C1019D-12
UnitMin. Max. Min. Max.
Data Retention Characteristics Over the Operating Range
Parameter Description Conditions Min. Max. Unit
VDR VCC for Data Retention VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
2.0 V
ICCDR Data Retention Current Non-L, Com’l/Ind’l 3 mA
L-Version Only 1.2 mA
tCDR[3] Chip Deselect to Data Retention Time 0 ns
tR[10] Operation Recovery Time tRC ns
Data Retention Waveform
4.5V4.5V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
Switching Waveforms
Read Cycle No. 1[1 1, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
Notes:
10.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
11.Device is co ntinuously selected. OE, CE = VIL.
12.WE is HIGH for read cycle.
13.Address valid prior to or coincident with CE transition LOW .
PREVIOUS DATA VALID DATA VALID
t
RC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
PRELIMINARY CY7C1019D
Document #: 38-05464 Rev. *C Page 6 of 9
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
Write Cycle No. 3 (WE Controlled, OE LOW)[15]
Notes:
14.Data I/O is hi gh impedance if OE = VIH.
15.If CE goes HIGH simultan eously with WE goin g HIGH, the output remains in a high- impedance stat e.
16.During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
ADDRESS
WE
DATA I/O
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 16
PRELIMINARY CY7C1019D
Document #: 38-05464 Rev. *C Page 7 of 9
Truth Table
CE OE WE I/O0–I/O7Mode Power
H X X High Z Power-Down Standby (ISB)
X X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
10 CY7C1019D-10VXC V33 32-Lead 400-Mi l Molded SOJ (Pb-Free) Commercial
CY7C1019D-10VXI V33 32-Lead 400-Mi l Molded SOJ (Pb-Free) Industrial
CY7C1019D-10ZXC ZS32 32-Lead TSOP Type II (Pb-Free) Commercial
CY7C1019D-10ZXI ZS32 32-Lead TSOP Type II (Pb-Free) Industrial
12 CY7C1019D-12VXC V33 32-Lead 400-Mi l Molded SOJ (Pb-Free) Commercial
CY7C1019D-12VXI V33 32-Lead 400-Mi l Molded SOJ (Pb-Free) Industrial
CY7C1019D-12ZXC ZS32 32-Lead TSOP Type II (Pb-Free) Commercial
CY7C1019D-12ZXI ZS32 32-Lead TSOP Type II (Pb-Free) Industrial
Shaded areas conta i n advance information. Please contact your local Cypress sales representative for availability of these parts.
Package Diagrams
51-85033-A
51-85033-*B
32-Lead (400-Mil) Molded SOJ V33
PRELIMINARY CY7C1019D
Document #: 38-05464 Rev. *C Page 8 of 9
© Cypress Semi con duct or Cor po rati on , 20 05 . The information contained he re i n is su bj ect to ch an ge wi t hou t notice. Cypress Semiconductor Corporation assu mes no resp onsib ility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furthermore , Cypress does not authorize i ts
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product or company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-85095-**
32-Lead TSOP II ZS32
PRELIMINARY CY7C1019D
Document #: 38-05464 Rev. *C Page 9 of 9
Document History Page
Document Title: CY7C1019D 1-Mbit (128K x 8) Static RAM (Preliminary)
Document Number: 38-05464
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 201560 See ECN SWI Advance Information data sheet for C9 IPP
*A 233715 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165)
Pb-free offering in the Ordering Information
*B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table
Added Data Retention Characteristics table and waveforms
Shaded Ordering Information
*C 307598 See ECN RKF Reduced Speed bins to -10 and -12 ns
