CY7C1019D PRELIMINARY 1-Mbit (128K x 8) Static RAM Functional Description[1] Features * Pin- and function-compatible with CY7C1019B * High speed -- tAA = 10 ns * CMOS for optimum speed/power * Low active power The CY7C1019D is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). -- ICC = 60 mA @ 10 ns * Low CMOS standby power -- ISB2 = 1.2 mA (`L' Version only) * Data Retention at 2.0V * Center power/ground pinout * Automatic power-down when deselected * Easy memory expansion with CE and OE options * Functionally equivalent to CY7C1019B * Available in Pb-Free Packages Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019D is available in standard 32-pin TSOP Type II and 400-mil-wide SOJ Pb-Free packages. Logic Block Diagram Pin Configurations SOJ /TSOPII Top View A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O0 INPUT BUFFER I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1 512 x 256 x 8 ARRAY I/O3 I/O2 I/O3 WE A4 A5 A6 A7 I/O4 I/O5 CE COLUMN DECODER POWER DOWN I/O7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 WE OE I/O6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05464 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised January 11, 2005 PRELIMINARY CY7C1019D Selection Guide CY7C1019D-10 CY7C1019D-12 Unit Maximum Access Time 10 12 ns Maximum Operating Current 60 50 mA Maximum Standby Current 3 3 mA 1.2 1.2 L Document #: 38-05464 Rev. *C Page 2 of 9 PRELIMINARY Maximum Ratings CY7C1019D Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Supply Voltage on VCC to Relative GND[2] .... -0.5V to +7.0V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V Commercial 0C to +70C 5V 10% -40C to +85C 5V 10% DC Input Voltage[2] .................................-0.5V to VCC + 0.5V Industrial Electrical Characteristics Over the Operating Range 7C1019D-10 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA Min. Max. 7C1019D-12 Min. 2.4 Max. Unit 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL Input LOW Voltage[2] -0.5 0.8 -0.5 0.8 V IIX Input Load Current GND < VI < VCC -1 +1 -1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled -1 +1 -1 +1 A ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 60 50 mA ISB1 Automatic CE Max. VCC, CE > VIH Power-Down Current VIN > VIH or VIN < VIL, f = fMAX --TTL Inputs Automatic CE Max. VCC, Power-Down Current CE > VCC - 0.3V, VIN > VCC - 0.3V, --CMOS Inputs or VIN < 0.3V, f = 0 10 10 mA 10 10 3.0 3.0 1.2 1.2 ISB2 0.4 V L L mA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. Unit 6 pF 8 pF Thermal Resistance[3] Parameter Description JA Thermal Resistance (Junction to Ambient)[3] JC Thermal Resistance (Junction to Case)[3] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board All - Packages Unit TBD C/W TBD C/W Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05464 Rev. *C Page 3 of 9 PRELIMINARY CY7C1019D AC Test Loads and Waveforms 10-ns Devices 12 -ns Devices Z = 50 OUTPUT R1 480 5V 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT OUTPUT 30 pF* R2 255 30 pF 1.5V INCLUDING JIG AND (b) SCOPE (a) THEVENIN EQUIVALENT 167 1.73V OUTPUT Equivalent to: High-Z characteristics: R1 480 5V ALL INPUT PULSES 3.0V 90% 3 ns R2 255 5 pF 10% 10% GND OUTPUT 90% INCLUDING JIG AND SCOPE (c) 3ns Switching Characteristics Over the Operating Range [5] 7C1019D-10 Parameter Description Min. 7C1019D-12 Max. Min. Max. Unit Read Cycle tpower[4] VCC(typical) to the first access 100 100 s tRC Read Cycle Time 10 12 ns tAA Address to Data Valid tOHA Data Hold from Address Change 10 3 12 3 ns ns tACE CE LOW to Data Valid 10 12 ns tDOE OE LOW to Data Valid 5 6 ns tLZOE OE LOW to Low Z 0 Z[6, 7] tHZOE OE HIGH to High tLZCE CE LOW to Low Z[7] CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down Write Cycle 5 3 [6, 7] tHZCE 0 ns 6 3 5 0 ns 6 0 10 ns ns ns 12 ns [8, 9] tWC Write Cycle Time 10 12 ns tSCE CE LOW to Write End 8 9 ns tAW Address Set-Up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-Up to Write End 5 6 ns Notes: 4. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05464 Rev. *C Page 4 of 9 PRELIMINARY CY7C1019D Switching Characteristics Over the Operating Range (continued)[5] 7C1019D-10 Parameter Description Min. 7C1019D-12 Max. Min. Max. Unit tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z[7] 3 3 ns tHZWE WE LOW to High Z[6, 7] 5 6 ns Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current Conditions VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Non-L, Com'l/Ind'l L-Version Only tCDR [3] Min. Unit 3 mA 1.2 mA 2.0 Chip Deselect to Data Retention Time tR[10] Max. Operation Recovery Time V 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC VDR > 2V tCDR 4.5V tR CE Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes: 10. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05464 Rev. *C Page 5 of 9 PRELIMINARY CY7C1019D Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tSA tSCE tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 3 (WE Controlled, OE LOW)[15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 16 tHD DATA VALID tHZWE tLZWE Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05464 Rev. *C Page 6 of 9 PRELIMINARY CY7C1019D Truth Table CE OE WE I/O0-I/O7 Mode Power H X X High Z Power-Down Standby (ISB) X X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 12 Ordering Code Package Name Operating Range Package Type CY7C1019D-10VXC V33 32-Lead 400-Mil Molded SOJ (Pb-Free) Commercial CY7C1019D-10VXI V33 32-Lead 400-Mil Molded SOJ (Pb-Free) Industrial CY7C1019D-10ZXC ZS32 32-Lead TSOP Type II (Pb-Free) Commercial CY7C1019D-10ZXI ZS32 32-Lead TSOP Type II (Pb-Free) Industrial CY7C1019D-12VXC V33 32-Lead 400-Mil Molded SOJ (Pb-Free) Commercial CY7C1019D-12VXI V33 32-Lead 400-Mil Molded SOJ (Pb-Free) Industrial CY7C1019D-12ZXC ZS32 32-Lead TSOP Type II (Pb-Free) Commercial CY7C1019D-12ZXI ZS32 32-Lead TSOP Type II (Pb-Free) Industrial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Package Diagrams 32-Lead (400-Mil) Molded SOJ V33 51-85033-A 51-85033-*B Document #: 38-05464 Rev. *C Page 7 of 9 PRELIMINARY CY7C1019D Package Diagrams (continued) 32-Lead TSOP II ZS32 51-85095-** All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05464 Rev. *C Page 8 of 9 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C1019D Document History Page Document Title: CY7C1019D 1-Mbit (128K x 8) Static RAM (Preliminary) Document Number: 38-05464 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233715 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in the Ordering Information *B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table Added Data Retention Characteristics table and waveforms Shaded Ordering Information *C 307598 See ECN RKF Reduced Speed bins to -10 and -12 ns Document #: 38-05464 Rev. *C Page 9 of 9