CX72302 Spur-Free, 6.1 GHz Dual Fractional-N Frequency Synthesizer Skyworks' CX72302 direct digital modulation fractional-N frequency synthesizer provides ultra-fine frequency resolution, fast switching speed, and low phase-noise performance. This synthesizer is a key building block for high-performance radio system designs that require low power and fine step size. The ultra-fine step size of less than 400 Hz allows this synthesizer to be used in very narrowband wireless applications. With proper temperature sensing or through control channels, the synthesizer's fine step size can compensate for crystal oscillator or Intermediate Frequency (IF) filter drift. As a result, crystal oscillators or crystals can replace temperature-compensated or ovenized crystal oscillators, reducing parts count and associated component cost. The CX72302's fine step size can also be used for Doppler shift corrections. The CX72302 has a phase noise floor of -80 dBc/Hz up to 6.1 GHz operation as measured inside the loop bandwidth. This is permitted by the on-chip low noise dividers and low divide ratios provided by the IC's high fractionality. Reference crystals or oscillators up to 50 MHz can be used with the CX72302. The crystal frequency divides by independent programmable dividers (1 to 32) for the main and auxiliary synthesizers. The phase detectors can operate at a maximum speed of 25 MHz, which allows better phase noise due to the lower division value. With a high reference frequency, the loop bandwidths can also be increased. Larger loop bandwidths improve the settling times and reduce in-band phase noise. Therefore, typical switching times of less than 100 s can be achieved. The CX72302's lower in-band phase noise also permits the use of lower cost Voltage Controlled Oscillators (VCOs) in customer applications. The CX72302 has a frequency power steering circuit that helps the loop filter to steer the VCO when the frequency is too fast or too slow, further enhancing acquisition time. The unit operates with a three-wire, high-speed serial interface. A combination of a large bandwidth, fine resolution, and the three-wire, high-speed serial interface allows for a direct frequency modulation of the VCO. This supports any continuous phase, constant envelope modulation scheme such as Frequency Modulation, Frequency Shift Keying, Minimum Shift Keying, or Gaussian Minimum Shift Keying (FM, FSK, MSK, GMSK). This capability can eliminate the need for In-Phase and Quadrature Digital-to-Analog Converters (I and Q DACs), quadrature upconverters, and IF filters from the transmitter portion of the radio system. Distinguishing Features * * * * * * * * * * * * * * * * * * * Spur-free operation 6.1 GHz maximum operating frequency Ultra-fine step size, 400 Hz or less 1000 MHz maximum auxiliary synthesizer High internal reference frequency, up to 25 MHz, enables a larger loop bandwidth Phase Locked Loop (PLL) Very fast switching speed (for example, below 100 s) Phase noise to -80 dBc/Hz inside loop filter bandwidth @6100 MHz Software programmable power-down modes High speed serial interface up to 100 Mbps Three-wire programming Programmable division ratios on reference frequency Phase detectors with programmable gains to provide a programmable loop bandwidth Frequency power steering further enhances rapid acquisition time On-chip crystal oscillator Frequency adjust for temperature compensation Direct Digital Modulation 3 V operation 5 V output to loop filter 28-pin EP-TSSOP package Applications General purpose RF systems 2.5G and 3G wireless infrastructures Broadband wireless access Low bit rate wireless telemetry Wireless Local Loop (WLL) * Instrumentation * * * * * Figure 1 shows a functional block diagram for the CX72302. The device package and pinout for the 28-pin Exposed Pad Thin Shrink Small Outline Package (EPTSSOP) are shown in Figure 2. Data Sheet Skyworks Proprietary Information and Specifications Are Subject to Change Doc. No. 101216E December 2, 2002 CX72302 Frequency Synthesizer Data Registers Clock CS Main Modul. Data Serial Interface Main Div. Modul. Ctl Ref. Div. Synth Ctl Aux. Aux. Div. Mod_in Modulation Unit 18-Bit 10-Bit Fractional Unit Fractional Unit Reference Frequency Oscillator Fvco_main Fvco_main Mux_out Mux Fvco_aux Main Divider Main Divider Auxiliary Divider Fpd_main Fref_main Main Phase/Freq. Detector and Charge Pump Fref_aux Fref Reference Frequency Oscillator Fvco_aux Fpd_aux Auxiliary Phase/Freq. Detector and Charge Pump CPout_aux CPout_main LD/PSmain Lock Detection or Power Steering Auxiliary Prescaler LD/PSaux Lock Detection or Power Steering C1447 Figure 1. CX72302 Functional Block Diagram Clock 1 28 CS Mod_in 2 27 Data Mux_out 3 26 VCCdigital VSUBdigital 4 25 GNDdigital GNDcml 5 24 VCCcml_aux VCCcml_main 6 23 Fvco_aux Fvco_main 7 22 Fvco_aux Fvco_main 8 21 GNDcp_aux LD/PSmain 9 20 CPout_aux VCCcp_main 10 19 VCCcp_aux CPout_main 11 18 LD/PSaux GNDcp_main 12 17 GNDxtal Xtalacgnd/OSC 13 16 VCCxtal Xtalin/OSC 14 15 Xtalout/NC C1412 Figure 2. CX72302 Pinout, 28-Pin EP-TSSOP 2 Skyworks Proprietary Information and Specifications Are Subject to Change 101216E December 2, 2002 Frequency Synthesizer CX72302 Technical Description Main and Auxiliary VCO Dividers _______________________ The CX72302 is supplied as a 28-pin EP-TSSOP. The exposed pad is located on the bottom side of the package and must be connected to ground for proper operation. The exposed pad should be soldered directly to the circuit board. The device pinout is shown in Figure 2. The CX72302 provides programmable dividers that control the CML prescalers and supply the required signals to the charge pump phase detectors. Programmable divide ratios ranging from 152 to 2148 are possible in fractional-N mode, and from 128 to 2172 in integer-N mode. Note that due to the fixed divide-by-four divider on the main synthesizer, the divide ratios are multiples of four. The CX72302 is a fractional-N frequency synthesizer using a modulation technique. The fractional-N implementation provides low in-band noise by having a low division ratio and fast frequency settling time. In addition, the CX72302 provides arbitrarily fine frequency resolution with a digital word, so that the frequency synthesizer can be used to compensate for crystal frequency drift in the RF transceiver. Programmable divide ratios ranging from 38 to 537 are possible in fractional-N mode, and from 32 to 543 in integer-N mode for the auxiliary synthesizer. Reference Frequency Oscillator________________________ Serial Interface _____________________________________ The serial interface is a versatile three-wire interface consisting of three pins: serial clock (Clock), serial input (Data), and chip select (CS). It enables the CX72302 to operate in a system where one or multiple masters and slaves are present. To perform a loopback test at start-up and to check the integrity of the board and processor, the serial data is fed back to the master device (for example, a microcontroller or microprocessor unit) through a programmable multiplexer. This facilitates hardware and software debugging. For more information see the Operation section of this document. Registers__________________________________________ The CX72302 has a self-contained, low-noise crystal oscillator. This crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency dividers. Reference Frequency Dividers _________________________ The crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequencies for the phase detectors. The CX72302 has both a main and auxiliary frequency synthesizer, and provides independently configurable dividers of the crystal oscillator frequency for both the main and auxiliary phase detectors. The divide ratios are programmed through the Reference Frequency Dividers Register. Note: The divided crystal oscillator frequencies (which are the internal reference frequencies), Fref_main and Fref_aux, are referred to as reference frequencies throughout this document. There are ten 16-bit registers in the CX72302. For more information, see the Registers section of this document. Main and Auxiliary Modulators_____________________ The fractionality of the CX72302 is accomplished by the use of a proprietary, configurable 10-bit or 18-bit modulator for the main synthesizer and 10-bit modulator for the auxiliary synthesizer. Main and Auxiliary Fractional Units ____________________ The CX72302 provides fractionality through the use of main and auxiliary modulators. The output from the main and auxiliary modulators is combined with the main and auxiliary divider ratios through their respective fractional units. VCO Prescalers ____________________________________ The VCO prescalers provide low-noise signal conditioning of the VCO signals. They translate from an off-chip, single-ended or differential signal to an on-chip differential Current Mode Logic (CML) signal. The CX72302 has independent main and auxiliary VCO prescalers. Phase Detectors and Charge Pumps____________________ The CX72302 uses a separate charge pump phase detector for each synthesizer which provides a programmable gain, Kd, from 31.25 to 1000 A/2 radians in 32 steps programmed via the Control Register. Frequency Steering __________________________________ When programmed for frequency power steering, the CX72302 has a circuit that helps the loop filter steer the VCO, through the LD/PSmain pin. In this configuration, the LD/PSmain pin can provide for more rapid acquisition. When programmed for lock detection, internal frequency steering is implemented and provides frequency acquisition times comparable to conventional phase/frequency detectors. Lock Detection ______________________________________ When programmed for lock detection, the CX72302 provides an active low, pulsing open collector output on the LD/PSmain pin 101216E December 2, 2002 Skyworks Proprietary Information and Specifications Are Subject to Change 3 CX72302 Frequency Synthesizer modulation data samples. In this case, it is assumed that no address bits are present and that all the bits in the stream should be loaded into the Modulation Data Register. to indicate the out-of-lock condition. When locked, the LD/PSmain pin is three-stated (high impedance). Power Down _______________________________________ Synthesizer Register Programming_____________________ The CX72302 supports a number of power-down modes through the serial interface. For more information, see the General Synthesizer Registers section of this document. Synthesizer register programming equations, described in this section, use the following variables and constants: Operation Nfractional Desired VCO division ratio in fractional-N applications. This is a real number and can be interpreted as the reference frequency (Fref) multiplying factor such that the resulting frequency is equal to the desired VCO frequency. Ninteger Desired VCO division ratio in integer-N applications. This number is an integer and can be interpreted as the reference frequency (Fref) multiplying factor such that the resulting frequency is equal to the desired VCO frequency. Nreg 9-bit unsigned input value to the divider ranging from 0 to 511 (integer-N mode) and from 6 to 505 (fractional-N mode) divider This constant equals 262144 when the modulator is in 18-bit mode, and 1024 when the modulator is in 10-bit mode dividend When in 18-bit mode, this is the 18-bit signed input value to the modulator, ranging from -131072 to +131071 providing 262144 steps, each of Fdiv_ref/218 Hz. This section describes the operation of the CX72302. The serial interface is described first, followed by information on how to obtain values for the Divide Ratio Registers. Serial Interface _____________________________________ The serial interface consists of three pins: Clock, Data, and CS. The Clock signal controls data transfers that synchronizes and samples the information on the two serial data lines (Data and CS). The Data pin bits shift into a temporary register on the rising edge of Clock. The CS line allows individual selection of slave devices on the same bus. Figure 3 functionally depicts how a serial transfer takes place. A serial transfer is initiated when a microcontroller or microprocessor forces the CS line to a low state. This is immediately followed by an address/data stream sent to the Data pin that coincides with the rising edges of the clock presented on the Clock line. Each rising edge of the Clock signal shifts in one bit of data on the Data line into a shift register. At the same time, one bit of data is shifted out of the Mux_out pin (if the serial bit stream is selected) at each falling edge of Clock. To load any of the synthesizer registers, 16 bits of address or data must be presented to the Data line with the data LSB last while CS is low. If CS is low for more than 16 clock cycles, only the last address or data bits are used to load the synthesizer registers. When in 10-bit mode, this is the 10-bit signed input value to the modulator, ranging from -512 to +511 providing 1024 steps, each of Fdiv_ref/210 Hz. If the CS line is brought to a high state before the thirteenth clock edge on Clock, the bit stream is assumed to be FVCO Desired VCO frequency (either Fvco_main or Fvco_aux). Fdiv_ref Divided reference frequency presented to the phase detector (either Fref_main or Fref_aux). Clock Data X A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX CS Last C1413 Figure 3. Serial Transfer Timing Diagram 4 Skyworks Proprietary Information and Specifications Are Subject to Change 101216E December 2, 2002 Frequency Synthesizer CX72302 where Ninteger is an integer number from 32 to 543 for both the main and auxiliary synthesizers. Fractional-N Applications The desired division ratio for the main synthesizer is given by: Nfrac tion al F VCO_main = --------------------------------( 4 x F div_r ef ) The desired division ratio for the auxiliary synthesizer is given by: FVCO_aux Nfrac tion al = -----------------------Fdiv_r ef where Nfractional must be between 150 and 2150 for the main synthesizer or between 37.5 and 537.5 for the auxiliary synthesizer. The value to be programmed in the Main or Auxiliary Divider Register is given by: N r eg = R ound [ ( N f racti onal ) ] - 32 Note: The Round function rounds the number to the nearest integer. When in fractional mode, allowed values for Nreg are from 6 to 505 inclusive. The value to be programmed in the Main or Auxiliary Dividend Register is given by: dividend = R ound [ divider x ( N fra ctio nal ) - N reg - 32 ] where the divider is either 1024 in 10-bit mode or 262144 in 18-bit mode. Therefore, the dividend is a signed binary value either 10 or 18 bits long. Note: Because of the high fractionality of the CX72302 there is no practical need for any integer relationship between the reference frequency and the channel spacing or desired VCO frequencies. Sample calculations for two fractional-N applications are provided in Figure 4. N r eg = N intege r - 32 When in integer mode, allowed values for Nreg are from 0 to 511 for both the main and auxiliary synthesizers. Note: As with all integer-N synthesizers, the minimum step size is related to the crystal frequency and reference frequency division ratio. A sample calculation for an integer-N application is provided in Figure 5. Register Loading Order In applications where the main synthesizer is in 18-bit mode, the Main Dividend MSB Register holds the 10 MSBs of the dividend and the Main Dividend LSB Register holds the 8 LSBs of the dividend. The registers that control the main synthesizer's divide ratio are to be loaded in the following order: * * * The desired division ratio for the main or auxiliary synthesizer is given by: FVCO_main Nintege r = --------------------------F d iv _re f Main Divider Register Main Dividend LSB Register Main Dividend MSB Register (at which point the new divide ratio takes effect) In applications where the main synthesizer is in 10-bit mode, the Main Dividend MSB Register holds the 10 bits of the dividend. The registers that control the main synthesizer's divide ratio are to be loaded in the following order: * * Main Divider Register Main Dividend MSB Register (at which point the new divide ratio takes effect) For the auxiliary synthesizer, the Auxiliary Dividend Register holds the 10 bits of the dividend. The registers that control the auxiliary synthesizer's divide ratio are to be loaded in the following order: * * Integer-N Applications 101216E December 2, 2002 The value to be programmed in the Main or Auxiliary Divider Register is given by: Auxiliary Divider Register Auxiliary Dividend Register (at which point the new divide ratio takes effect) Note: When in integer mode, the new divide ratios take effect as soon as the Main or Auxiliary Divider Register is loaded. Skyworks Proprietary Information and Specifications Are Subject to Change 5 CX72302 Frequency Synthesizer Case 1: To achieve a desired Fvco_main frequency of 5900.4530 MHz using a crystal frequency of 40 MHz with operation of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz. Therefore: Nfractional = Fvco_main 4 x Fdiv_ref = 5900.4530 80 = 73.755663 The value to be programmed in the Main Divider Register is: Nreg = Round[Nfractional] - 32 = Round[73.755663] - 32 = 74 - 32 = 42 (decimal) = 000101010 (binary) With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is: dividend = Round[divider x (Nfractional - Nreg - 32)] = Round[262144 x (73.755663 - 42 - 32)] = Round[262144 x (-0.2443375)] = Round[-64051.6096] = -64052 (decimal) = 110000010111001100 (binary) where 11 0000 0101 is loaded in the MSB of the Main Dividend Register and 11001100 is loaded in the LSB of the Main Dividend Register. Summary: * * * * Main Divider Register = 0 0010 1010 Main Dividend LSB Register = 1100 1100 Main Dividend MSB Register = 11 0000 0101 The resulting main VCO frequency is 5900.4529 MHz Note: The frequency step size for this case is 4 x 20 MHz divided by 218, giving 305.2 Hz. C1449 Figure 4. Fractional-N Applications: Sample Calculation (1 of 2) 6 Skyworks Proprietary Information and Specifications Are Subject to Change 101216E December 2, 2002 Frequency Synthesizer CX72302 Case 2: To achieve a desired Fvco_main frequency of 5217.1776 MHz using a crystal frequency of 19.2 MHz with operation of the synthesizer in 10-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency does not require the internal division to be greater than 1, which makes Fdiv_ref = 19.2 MHz. Therefore: Nfractional = Fvco_main 4 x Fdiv_ref = 5217.1776 4 x 19.2 = 67.9320 The value to be programmed in the Main Divider Register is: Nreg = Round[Nfractional] - 32 = Round[67.9320] - 32 = 68 - 32 = 36 (decimal) = 000100100 (binary) With the modulator in 10-bit mode, the value to be programmed in the Main Dividend Registers is: dividend = Round[divider x (Nfractional - Nreg - 32)] = Round[1024 x (67.9320 - 36 - 32)] = Round[1024 x (- 0.068)] = Round[- 69.632] = -70 (decimal) = 1110111010 (binary) where 11 1011 1010 is loaded in the MSB of the Main Dividend Register. Summary: * * * Main Divider Register = 0 0010 0100 Main Dividend MSB Register = 11 1011 1010 The resulting main VCO frequency is 5217.15 MHz Note: The frequency step size for this case is 4 x 19.2 MHz divided by 210, giving 75 kHz. C1450 Figure 4. Fractional-N Applications: Sample Calculation (2 of 2) 101216E December 2, 2002 Skyworks Proprietary Information and Specifications Are Subject to Change 7 CX72302 Frequency Synthesizer To achieve a desired Fvco_aux frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum divide ratio is 32, the reference frequency (Fdiv_ref) must be a maximum of 12.5 MHz. Choosing a reference frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore: Ninteger = Fvco_aux Fdiv_ref = 400 8 = 50 The value to be programmed in the Auxiliary Divider Register is: Nreg = Ninteger - 32 = 50 - 32 = 18 (decimal) = 000010010 (binary) Summary: * Auxiliary Divide Register = 0 0001 0010 C1416 Figure 5. Integer-N Applications: Sample Calculation Direct Digital Modulation_____________________________ The high fractionality and small step size of the CX72302 allow the user to tune to practically any frequency in the VCO's operating range. This frequency tuning allows direct digital modulation by programming the different desired frequencies at precise instants. Typically, the channel frequency is selected through the Main Divider and Dividend Register and the instantaneous frequency offset from the carrier is entered through the Modulation Data Register. The Modulation Data Register can be accessed in three ways, which are defined in the following subsections. Normal Register Write. A normal 16-bit serial interface write occurs when CS is 16 clock cycles wide. The corresponding 16bit modulation data is simultaneously presented to the Data pin. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Short CS Through Data Pin (No Address Bits Required). A shortened serial interface write occurs when CS is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented to the Data pin. The Data pin is the default pin used to enter modulation data directly in the Modulation Data Register with shortened CS strobes. This method of data entry eliminates the register address overhead on the serial interface. All serial interface bits are resynchronized internally at the reference oscillator frequency. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). 8 Short CS Through Mod_in Pin (No Address Bits Required). A shortened serial interface write occurs when CS is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented to the Mod_in pin. The Mod_in pin is the alternate pin used to enter modulation data directly into the Modulation Data Register with shortened CS strobes. This mode is selected through the Modulation Control Register. This method of data entry also eliminates the register address overhead on the serial interface and allows a different device than the one controlling the channel selection to enter the modulation data (e.g., a microcontroller for channel selection and a digital signal processor for modulation data). All serial interface bits are re-synchronized internally at the reference oscillator frequency and the content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Modulation data samples in the Modulation Data Register can be from 2 to 12 bits long, and enable the user to select how many distinct frequency steps are to be used for the desired modulation scheme. The user can also control the frequency deviation through the modulation data magnitude offset in the Modulation Control Register. This allows shifting of the modulation data to accomplish a 2m multiplication of frequency deviation. Note: The programmable range of -0.5 to +0.5 of the main modulator can be exceeded up to the condition where the sum of the dividend and the modulation data conform to: - 0.5625 N mod + dividend + 0.5625 Skyworks Proprietary Information and Specifications Are Subject to Change 101216E December 2, 2002 Frequency Synthesizer CX72302 Table 1. CX72302 Register Map Address (Hex) Register (Note 1) Length (Bits) Address (Bits) 0 Main Divider Register 16 4 1 Main Dividend MSB Register 16 4 2 Main Dividend LSB Register 16 4 3 Auxiliary Divider Register 16 4 4 Auxiliary Dividend Register 16 4 5 Reference Frequency Dividers Register 16 4 6 Control Register--phase detector/charge pumps 16 4 7 Control Register--power down/multiplexer output select 16 4 8 Modulation Control Register 16 4 9 Modulation Data Register 16 4 -- Modulation Data Register (Note 2) -- direct input 2 length 12 bits 0 Note 1: All registers are write only. Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data. A3 0 A2 A1 0 0 A0 11 0 X 10 9 8 X X MSB 7 6 5 4 3 2 1 0 LSB Main Synthesizer Divider Index C1417 Figure 6. Main Divider Register (Write Only) When the sum of the dividend and modulation data lie outside this range, the value of Ninteger must be changed. Synthesizer Registers For a more detailed description of direct digital modulation functionality, refer to the Skyworks' document, CX72300/CX72301/CX72302 Direct Digital Modulation Application Note, document number 101349. Main Synthesizer Registers ___________________________ The Main Divider Register contains the integer portion closest to the desired fractional-N (or the integer-N) value minus 32 for the main synthesizer. This register, in conjunction with the Main Dividend Registers (which control the fraction offset from -0.5 to +0.5), allows selection of a precise frequency. Registers This section describes the CX72302 registers. All register writes are programmed address first, followed directly with data. MSBs are entered first. On power-up, all registers are reset to 0x000 except registers at addresses 0x0 and 0x3, which are set to 0x006. Register Map_______________________________________ Table 1 provides a description for each of the CX72302 device registers. For more information on register loading, refer to the Synthesizer Register Programming section in this document. 101216E December 2, 2002 Note: The fixed divide-by-four divider upstream from the programmable main divider must be taken into consideration to determine the value to be programmed in this register. For more information, refer to the Synthesizer Register Programming section in this document. As shown in Figure 6, the value to be loaded is: * Main Synthesizer Divider Index = 9-bit value for the integer portion of the main synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-N). Skyworks Proprietary Information and Specifications Are Subject to Change 9 CX72302 Frequency Synthesizer the Auxiliary Dividend Register, which controls the fraction offset (from -0.5 to + 0.5) allows selection of a precise frequency. As shown in Figure 9, the value to be loaded is: The Main Dividend MSB and LSB Registers control the fraction part of the desired fractional-N value and allow an offset of -0.5 to + 0.5 to the main integer selected through the Main Divider Register. As shown in Figures 7 and 8, the values to be loaded are: * * * Main Synthesizer Dividend (MSBs) = 10-bit value for the MSBs of the 18-bit dividend for the main synthesizer. Main Synthesizer Dividend (LSBs) = 8-bit value for the LSBs of the 18-bit dividend for the main synthesizer. Auxiliary Synthesizer Divider Index = 9-bit value for the integer portion of the auxiliary synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-N). The Auxiliary Dividend Register controls the fraction part of the desired fractional-N value and allows an offset of -0.5 to + 0.5 to the auxiliary integer selected through the Auxiliary Divider Register. As shown in Figure 10, the value to be loaded is: The Main Dividend MSB and LSB Register values are 2's complement format. * Note: When in 10-bit mode, the Main Synthesizer Dividend (LSBs) is not required. For information on programming and loading order for these registers, see the Operation section in this document. Auxiliary Synthesizer Dividend = 10-bit value for the dividend for the auxiliary synthesizer. For information on programming and loading order for these registers, refer to the Operation section in this document. Auxiliary Synthesizer Registers _______________________ The Auxiliary Divider Register contains the integer portion closest to the desired fractional-N (or integer-N) value minus 32 for the auxiliary synthesizer. This register, in conjunction with A3 0 A2 A1 0 0 A0 11 1 X 10 9 8 7 6 5 4 3 2 1 X MSB 0 LSB Main Synthesizer Dividend (MSBs) C1418 Figure 7. Main Dividend MSB Register (Write Only) A3 0 A2 A1 0 1 A0 11 0 X 10 9 8 X X X MSB 7 6 5 4 3 2 1 0 LSB Main Synthesizer Dividend (LSBs) C1419 Figure 8. Main Dividend LSB Register (Write Only) A3 0 A2 A1 0 1 A0 11 1 X 10 9 X X MSB 8 7 6 5 4 3 2 1 0 LSB Auxiliary Synthesizer Divider Index C1420 Figure 9. Auxiliary Divider Register (Write Only) 10 Skyworks Proprietary Information and Specifications Are Subject to Change 101216E December 2, 2002 Frequency Synthesizer A3 0 CX72302 A2 A1 1 A0 11 0 0 10 X 9 8 7 6 5 4 3 2 1 X MSB 0 LSB Auxiliary Synthesizer Dividend C1421 Figure 10. Auxiliary Dividend Register (Write Only) A3 0 A2 A1 1 0 A0 11 1 X 10 9 8 7 6 5 4 3 2 1 0 X Main Reference Frequency Divider Index Auxiliary Reference Frequency Divider Index C1422 Figure 11. Reference Frequency Dividers Register (Write Only) * General Synthesizer Registers ________________________ The Reference Frequency Dividers Register configures the dual-programmable reference frequency dividers for the main and auxiliary synthesizers. * The dual-programmable reference frequency dividers provide the reference frequencies to the phase detectors by dividing the crystal oscillator frequency. The lower five bits hold the reference frequency divide index for the main phase detector. The next five bits hold the reference frequency divide index for the auxiliary phase detector. Divide ratios from 1 to 32 are possible for each reference frequency divider. As shown in Figure 11, the values to be loaded are: * * * Main Reference Frequency Divider Index = Desired main oscillator frequency division ratio - 1. Default value on power-up is 0, signifying that the reference frequency is not divided for the main phase detector (see Table 2). Auxiliary Reference Frequency Divider Index = Desired Auxiliary oscillator frequency division ratio - 1. Default value on power up is 0, signifying that the reference frequency is not divided for the auxiliary phase detector (see Table 3). * Main Phase Detector Gain = 5-bit value for programmable main phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 A/ 2 radian, respectively. Main Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the main phase detector. When this bit is a 0, the LD/PSmain pin is configured to be a lock detect, active-low, open collector pin. When this bit is a 1, the LD/PSmain pin is configured to be a frequency power steering pin and can be used to bypass the external main loop filter to provide faster frequency acquisition. Auxiliary Phase Detector Gain = 5-bit value for programmable auxiliary phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 A/ 2 radian, respectively. Auxiliary Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the auxiliary phase detector. When this bit is a 0, the LD/PSaux pin is configured to be a lock detect, active-low, open collector pin. When this bit is a 1, the LD/PSaux pin is configured to be a frequency power steering pin and may be used to bypass the external auxiliary loop filter to provide faster frequency acquisition. The Control Register allows control of the gain for both phase detectors and configuration of the LD/PSmain and LD/PSaux pins for frequency power steering or lock detection. As shown in Figure 12, the values to be loaded are: 101216E December 2, 2002 Skyworks Proprietary Information and Specifications Are Subject to Change 11 CX72302 Frequency Synthesizer Table 2. Programming the Main Reference Frequency Divider Decimal Bit 4 (MSB) Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Reference Divider Ratio 0 0 0 0 0 0 1 1 0 0 0 0 1 2 2 0 0 0 1 0 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31 1 1 1 1 1 32 Table 3. Programming the Auxiliary Reference Frequency Divider Decimal Bit 9 (MSB) Bit 8 Bit 7 Bit 6 Bit 5 (LSB) Reference Divider Ratio 0 0 0 0 0 0 1 1 0 0 0 0 1 2 2 0 0 0 1 0 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31 1 1 1 1 1 32 A3 0 A2 A1 1 1 A0 11 10 9 8 7 6 5 4 3 2 1 0 0 Main Phase Detector Gain Main Power Steering/Lock Detect Enable Auxiliary Phase Detector Gain Auxiliary Power Steering/Lock Detect Enable C1423 Figure 12. Control Register (Write Only) The Power Down and Multiplexer Output Register allows control of the power-down modes, internal multiplexer output, and Main synthesizer fractionality. As shown in Figure 13, the values to be loaded are: * * 12 Full Power Down = 1-bit value that powers down the CX72302 except for the reference oscillator and the serial interface. When this bit is 0, the CX72302 is powered up. When this bit is 1, the CX72302 is in full power-down mode excluding the Mux_out pin. Main Synthesizer Power Down = 1-bit value that powers down the main synthesizer. When this bit is 0, the main * * synthesizer is powered up. When this bit is 1, the main synthesizer is in power-down mode. Main Synthesizer Mode = 1-bit value that powers down the main synthesizer's modulator and fractional unit to operate as an integer-N synthesizer. When this bit is 0, the main synthesizer is in fractional-N mode. When this bit is 1, the main synthesizer is in integer-N mode. Main Synthesizer Fractionality = 1-bit value that configures the size of the main modulator. This has a direct effect on power consumption and on the level of fractionality and step size. When this bit is 0, the main modulator is 18-bit with a fractionality of 218 and a step size of Fref_main/262144. When this bit is 1, the main Skyworks Proprietary Information and Specifications Are Subject to Change 101216E December 2, 2002 Frequency Synthesizer * * CX72302 - modulator is 10-bit with a fractionality of 210 and a step size of Fref_main/1024. Auxiliary Synthesizer Power Down = 1-bit value that powers down the auxiliary synthesizer. When this bit is 0, the auxiliary synthesizer is powered up. When this bit is 1, the auxiliary synthesizer is in power-down mode. Auxiliary Synthesizer Mode = 1-bit value that powers down the auxiliary synthesizer's modulator and fractional unit to operate as an integer-N synthesizer. When this bit is 0, the auxiliary synthesizer is in fractional-N mode. When this bit is 1, the auxiliary synthesizer is in integer-N mode. - Refer to Table 4 for more information. * Multiplexer Output Selection = 3-bit value that selects which internal signal is output to the Mux_out pin. The following internal signals are available on this pin: - - Mux_out Pin Three-State Enable = 1-bit value to threestate the Mux_out pin. When this bit is 0, the Mux_out pin is enabled. When this bit is 1, the Mux_out pin is threestated. The Modulation Control Register is used to configure the modulation unit of the main synthesizer The modulation unit adds or subtracts a frequency offset to the selected center frequency at which the main synthesizer operates. The size of the modulation data sample, controlled by the duration of the CS signal, can be from 2 to 12 bits wide, to provide from 4 to 4096 selectable frequency offset steps. Note: There are no special power-up sequences required for the CX72302. * Main or auxiliary phase detector frequency (post main and auxiliary frequency dividers): Fpd_main or Fpd_aux Serial data out, for loop-back and test purposes Reference Oscillator: Fref Main or auxiliary divided reference (post reference frequency main or auxiliary dividers): Fref_main or Fref_aux A3 0 A2 A1 1 A0 11 1 1 X 10 X 9 8 7 MSB 6 5 4 3 2 1 0 LSB Full Power Down Main Synthesizer Power Down Main Synthesizer Mode Main Synthesizer Fractionality Auxiliary Synthesizer Power Down Auxiliary Synthesizer Mode Multiplexer Output Selection Mux_out Pin Three-State Enable C1424 Figure 13. Power Down and Multiplexer Output Register (Write Only) Table 4. Multiplexer Output 101216E December 2, 2002 Multiplexer Output Select (Bit 8) Multiplexer Output Select (Bit 7) Multiplexer Output Select (Bit 6) Multiplexer Output (Mux_out) 0 0 0 Reference Oscillator 0 0 1 Auxiliary Reference Frequency (Fref_aux) 0 1 0 Main Reference Frequency (Fref_main) 0 1 1 Auxiliary Phase Detector Frequency (Fpd_aux) 1 0 0 Main Phase Detector Frequency (Fpd_main) 1 0 1 Serial data out 1 1 0 Serial Interface Register test output Skyworks Proprietary Information and Specifications Are Subject to Change 13 CX72302 Frequency Synthesizer The modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be from 0 to 8. As shown in Figure14, the values to be loaded are: * * * Register values are 2's complement format. As shown in Figure 15, the value to be loaded is: * Modulation Data Magnitude Offset = 4-bit value that indicates the magnitude multiplier (m) for the modulation data samples. Valid values range from 0 to 13, effectively providing a 2m multiplication of the modulation data sample. Modulation Data Input Select = 1-bit value that indicates the pin on which modulation data samples are serially input when CS is between 2 and 12 bits long. When this bit is 0, modulation data samples are to be presented on the Data pin. When this bit is 1, modulation data samples are to be presented on the Mod_in pin. Modulation Address Disable = 1-bit value that indicates the presence of the address as modulation data samples are presented on either the Mod_in or Data pins. When this bit is 0, the address is presented with the modulation data samples (i.e., all transfers are 16 bits long). When this bit is 1, no address is presented with the modulation data samples (i.e., all transfers are 2 to 12 bits long). Electrical and Mechanical Specifications Signal pin assignments and functional pin descriptions are specified in Table 5. The absolute maximum ratings of the CX72302 are provided in Table 6. The recommended operating conditions are specified in Table 7 and electrical specifications are provided in Table 8. Figure 16 provides a schematic diagram for the CX72302. Figure 17 shows the package dimensions for the 28-pin EP-TSSOP and Figure 18 provides the tape and reel dimensions. Electrostatic Discharge (ESD) Sensitivity The Modulation Data Register is used to load the modulation data samples to the modulation unit. This value is transferred to the modulation unit on the falling edge of Fpd_main where it is passed to the main modulator at the selected magnitude offset on the next falling edge of Fpd_main. Modulation Data A3 1 A2 A1 0 0 A0 11 0 10 X 9 8 7 6 Modulation Data Bits = Modulation data samples that represent the desired instantaneous frequency offset to the selected main synthesizer frequency (selected channel) before being affected by the modulation data magnitude offset. The CX72302 is a static-sensitive electronic device. Do not operate or store near strong electrostatic fields. Take proper ESD precautions. 5 4 X 3 2 1 0 0 0 0 0 Reserved Bits Modulation Data Magnitude Offset Modulation Data Input Select Modulation Address Disable C1425 Figure 14. Modulation Control Register (Write Only) A3 1 A2 A1 0 0 A0 11 10 9 8 7 6 5 4 1 MSB 3 2 1 0 LSB Modulation Data Bits C1426 Figure 15. Modulation Data Register (Write Only) 14 Skyworks Proprietary Information and Specifications Are Subject to Change 101216E December 2, 2002 Frequency Synthesizer CX72302 Table 5. CX72302 Signal Descriptions Pin # Name Type Description 1 Clock Digital input 2 Mod_in Digital input Alternate serial modulation data input pin. Address bits are followed by data bits. 3 Mux_out Digital output Internal multiplexer output. Selects from oscillator frequency, main or auxiliary reference frequency, main or auxiliary divided VCO frequency, serial data out, or testability signals. This pin can be three-stated from the general synthesizer registers. 4 VSUBdigital 5 GNDecl/cml (Note 1) Power and ground Emitter Coupled Logic (ECL)/Current Mode Logic (CML) ground. 6 VCCcml_main (Note 1) Power and ground ECL/CML 3 V. Removing power safely powers down the associated divider chain and charge pump. 7 Fvco_main Input Main VCO differential input. 8 Fvco_main Input Main VCO complimentary differential input. 9 LD/PSmain Analog output Programmable output pin. Indicates main phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the main VCO. This pin is configured from the general synthesizer registers. 10 VCCcp_main (Note 1) Power and ground Main charge pump 3 to 5 V. Removing power safely powers down the associated divider chain and charge pump. 11 CPout_main Analog output Main charge pump output. The gain of the main charge pump phase detector can be controlled from the general synthesizer registers. 12 GNDcp_main (Note 1) Power and ground Main charge pump ground. 13 Xtalacgnd/OSC Ground/input Reference crystal AC ground or external oscillator differential input. 14 Xtalin/OSC Input Reference crystal input or external oscillator differential input. 15 Xtalout/NC Input Reference crystal output or no connect. 16 VCCxtal Power and ground Crystal oscillator ECL/CML 3 V. 17 GNDxtal Power and ground Crystal oscillator ground. 18 LD/PSaux Analog output Programmable output pin. Indicates auxiliary phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the auxiliary VCO. This pin is configured from the general synthesizer registers. 19 VCCcp_aux (Note 1) Power and ground Auxiliary charge pump 3 to 5 V. Removing power safely powers down the associated divider chain and charge pump. 20 CPout_aux Analog output Auxiliary charge pump output. The gain of the auxiliary charge pump phase detector can be controlled from the general synthesizer registers. 21 GNDcp_aux (Note 1) Power and ground Auxiliary charge pump ground. 22 Fvco_aux Input Auxiliary VCO complimentary differential input. 23 Fvco_aux Input Auxiliary VCO differential input. 24 VCCcml_aux (Note 1) Power and ground ECL/CML 3 V. Removing power safely powers down the associated divider chain and charge pump. 25 GNDdigital (Note 1) Power and ground Digital ground. 26 VCCdigital (Note 1) Power and ground Digital 3 V. 27 Data Digital input Serial address and data input pin. Address bits are followed by data bits. 28 CS Digital input Active low enable pin. Enables loading of address and data on the Data pin on the rising edge of Clock. When CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges are ignored. - Clock signal pin. When CS is low, the register address and data are shifted in address bits first on the Data pin on the rising edge of Clock. Substrate isolation. Connect to ground. Note 1: Associated pairs of power and ground pins must be decoupled using 0.1 F capacitors. 101216E December 2, 2002 Skyworks Proprietary Information and Specifications Are Subject to Change 15 CX72302 Frequency Synthesizer Table 6. Absolute Maximum Ratings Parameter Min Max Units Maximum analog RF supply voltage 3.6 VDC Maximum digital supply voltage 3.6 VDC Maximum charge pump supply voltage 5.25 VDC Storage temperature -65 +150 C Operating temperature -40 +85 C Note: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set at or below their nominal conditions. Table 7. Recommended Operating Conditions Parameter Min Max Units Analog RF supplies 2.7 3.3 VDC Digital supply 2.7 3.3 VDC Charge pump supplies 2.7 5.0 VDC Operating temperature (TA) -40 +85 C Table 8. Electrical Characteristics (1 of 2) (VDD = 3 V, TA = 25 C, unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units Power Consumption Total power consumption PTOTAL Power-down current ICC-PWDN Reference oscillator frequency FOSC Oscillator sensitivity (as a buffer) VOSC AC coupled, single-ended Frequency shift versus supply voltage FSHIFT_SUPPLY 2.7 V VXTAL 3.3 V 54 mW 39 mW 10 (Note 1) A Charge pump currents of 200 A. Both synthesizers fractional, FREF_MAIN = 20 MHz, FREF_AUX = 1 MHz Auxiliary synthesizer power-down Reference Oscillator 50 MHz 2.0 Vpp 0.3 ppm 0.1 VCOs Main synthesizer operating frequency FVCO_MAIN Sinusoidal, -40 C to +85 C 400 (Note 2) 6100 MHz Auxiliary synthesizer operating frequency FVCO_AUX Sinusoidal, -40 C to +85 C 100 (Note 3) 1000 MHz RF input sensitivity VVCO AC coupled 50 250 mVpeak Main fractional-N tuning step size Auxiliary fractional-N tuning step size 16 FSTEP_MAIN 4 x FREF_MAIN/218 or FREF_MAIN/210 Hz FSTEP_AUX FREF_AUX /210 Hz Skyworks Proprietary Information and Specifications Are Subject to Change 101216E December 2, 2002 Frequency Synthesizer CX72302 Table 8. Electrical Characteristics (2 of 2) (VDD = 3 V, TA = 25 C, unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units Noise Phase noise floor PNF Measured inside the loop bandwidth using 25 MHz reference frequency, -40 C to +85 C dBc/Hz -128 + 20 Log (N) Phase Detectors and Charge Pumps Main phase detector frequency FREF_MAIN -40 C to +85 C 25 MHz Auxiliary phase detector frequency FREF_AUX -40 C to +85 C 25 MHz Charge pump output source current ICP-source VCP = 0.5 VCCCP 125 1000 A Charge pump output sink current ICP-sink VCP = 0.5 VCCCP -125 -1000 A Charge pump accuracy ICP-accuracy Charge pump output voltage linearity range ICP vs. VCP 0.5 V VCP (VCCCP - 0.5 V) Charge pump current versus temperature ICP vs. T Charge pump current versus voltage ICP vs. VCP 20 GND + 400 % VCCCP - 400 mV VCP = 0.5 VCCCP -40 C < T < +85 C 5 % 0.5 V VCP (VCCCP - 0.5 V) 8 % Digital Pins High level input voltage VIH Low level input voltage VIL 0.7 VDIGITAL V High level output voltage VOH IOH = -2 mA Low level output voltage VOL IOL = 2 mA Clock frequency fCLOCK Data and CS set up time to Clock rising tSU 3 ns Data and CS hold time after Clock rising tHOLD 0 ns 0.3 VDIGITAL VDIGITAL -0.2 V V GND + 0.2 V 100 MHz Timing - Serial Interface Note 1: A 5 V charge pump power supply (on pin 10 and/or pin 19) results in higher power-down leakage current. Note 2: When operating in fractional mode, minimum synthesizer frequency is 48 x Fosc, where Fosc is the frequency at the Xtalin/OSC pin. Note 3: When operating in fractional mode, minimum synthesizer frequency is 12 x Fosc, where Fosc is the frequency at the Xtalin/OSC pin. 101216E December 2, 2002 Skyworks Proprietary Information and Specifications Are Subject to Change 17 CX72302 18 To Microprocessor RF Out Auxiliary J1 3V 1 3 4 5 VSUBdigital GNDdigital GNDecl/cml VCCcml_aux C1 1 nF C2 1 nF 25 R1 100 k C5 7 C7 8 VCCcml_main Fvco_aux Fvco_main Fvco_aux Fvco_main GNDcp_aux 23 C4 22 C6 Auxiliary VCO A LD/PSmain CPout_aux RFOUT 2 C11 1 nF 11 A 12 VCCcp_main VCCcp_aux CPout_main LD/PSaux GNDcp_main GNDxtal VT Xtalacgnd/OSC VCCxtal A 3V 17 16 R4 R5 GND Xtalin/OSC A C15 C14 A Xtalout/NC 5 C12 15 A Auxiliary Synthesizer Loop Filter C17 1 nF 29 1 14 C9 A C10 1 nF A A Main VCO R2 R3 18 A 13 4 C8 19 A GND 3 20 3V 10 VCC VCC A 9 3V 3 VCC Auxiliary VCO 4 GND A 21 A VCC 4 A A A 24 A VT 2 4 3 VCCdigital 3V 26 2 6 3V A Mux_out 27 A A Lock Detect Main Output Data 1 RF Out Main J1 1 Mod_in 28 RFOUT C3 1 nF 5 Figure 16. CX72302 Application Schematic Skyworks Proprietary Information and Specifications Are Subject to Change 3V CS 3 2 Clock 2 1 A A C16 100 pF C17 Y1 C18 C19 C1427 101216E December 2, 2002 3V R6 100 k Lock Detect Auxiliary Output Frequency Synthesizer A Main Synthesizer Loop Filter External Pad Connection to Ground Frequency Synthesizer CX72302 b e 1 E P1 E1 D P EXPOSED PAD BOTTOM VIEW TOP VIEW Millimeters Dim. MIN. MAX. 1.10 A A2 A A1 L SIDE VIEW DETAIL A1 0.05 0.15 A2 0.85 0.95 D 9.70 BSC E 6.40 BSC E1 4.30 4.50 L 0.50 0.70 3.50 P 3.00 P1 e b 0.65 BSC 0.19 0.30 C1428 Figure 17. CX72302 28-Pin EP-TSSOP Package Dimension Drawing 1.50 0.10 1.75 0.10 2.00 0.05 4.00 0.10 8.00 0.10 Pin #1 indicator 7.50 0.10 16.00 +0.30/-0.10 1.50 0.25 3.96 1.10 0.318 0.013 8o Max 6.75 0.10 1.60 0.10 7o Max 9.95 0.10 NOTE(S): 1. Carrier tape material: black conductive polycarbonate 2. Cover tape material: transparent conductive PSA 3. Cover tape size: 13.3 mm width 4. Tolerance: .XX = 0.10 5. All measurements are in millimeters C1430 Figure 18. CX72302 Tape and Reel Dimensions 101216E December 2, 2002 Skyworks Proprietary Information and Specifications Are Subject to Change 19 CX72302 Frequency Synthesizer Ordering Information Model Name CX72302 Frequency Synthesizer Ordering Part Number CX72302-11 Evaluation Kit Part Number PH00-D122 (c) 2001, 2002, Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. ("Skyworks") products. These materials are provided by Skyworks as a service to its customers and may be used for informational purposes only. Skyworks assumes no responsibility for errors or omissions in these materials. Skyworks may make changes to its products, specifications and product descriptions at any time, without notice. Skyworks makes no commitment to update the information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from future changes to its products and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as may be provided in Skyworks' Terms and Conditions of Sale for such products, Skyworks assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF SKYWORKSTM PRODUCTS INCLUDING WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. SKYWORKS FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. 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Additional information, posted at www.skyworksinc.com, is incorporated by reference. 20 Skyworks Proprietary Information and Specifications Are Subject to Change 101216E December 2, 2002 General Information: Skyworks Solutions, Inc. 4311 Jamboree Rd. Newport Beach, CA 92660-3007 www.skyworksinc.com