FEATURES FUNCTIONAL BLOCK DIAGRAM 2 5 VGG2 RFIN VGG1 8 7 6 13738-001 Test instrumentation Microwave radios and VSATs Military and space Telecommunications infrastructure Fiber optics HMC930A RFOUT/VDD 1 APPLICATIONS 4 ACG2 3 ACG1 High output power for 1 dB compression (P1dB): 22 dBm High saturated output power (PSAT): 24 dBm High gain: 13 dB High output third-order intercept (IP3): 33.5 dBm Supply voltage: 10 V at 175 mA 50 matched input/output Die size: 2.82 mm x 1.50 mm x 0.1 mm ACG4 ACG3 Data Sheet GaAs, pHEMT, MMIC, 0.25 W Power Amplifier, DC to 40 GHz HMC930A Figure 1. GENERAL DESCRIPTION The HMC930A is a gallium arsenide (GaAs), pseudomorphic, high electron mobility transfer (pHEMT), monolithic microwave integrated circuit (MMIC), distributed power amplifier that operates from dc to 40 GHz. The HMC930A provides 13 dB of gain, 33.5 dBm output IP3, and 22 dBm of output power at 1 dB gain compression, requiring 175 mA from a 10 V supply. The HMC930A exhibits a slightly positive gain slope from Rev. A 8 GHz to 32 GHz, making it ideal for electronic warfare (EW), electronic countermeasures (ECM), radar, and test equipment applications. The HMC930A amplifier inputs/outputs (I/Os) are internally matched to 50 , facilitating integration into multichip modules (MCMs). All data is taken with the chip connected via two 0.025 mm (1 mil) wire bonds of minimal length at 0.31 mm (12 mils). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2015-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC930A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions .............................6 Applications ...................................................................................... 1 Interface Schematics .....................................................................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics .............................................8 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Revision History ............................................................................... 2 Applications Information ............................................................. 14 Electrical Specifications ................................................................... 3 Biasing Procedures ..................................................................... 14 DC to 12 GHz Frequency Range ................................................ 3 12 GHz to 32 GHz Frequency Range ........................................ 3 Mounting and Bonding Techniques for Millimeterwave GaAs MMICs .............................................................................. 15 32 GHz to 40 GHz Frequency Range ........................................ 4 Outline Dimensions ....................................................................... 16 Total Supply Current by VDD ...................................................... 4 Die Packaging Information ...................................................... 16 Absolute Maximum Ratings ........................................................... 5 Ordering Guide .............................................................................. 16 ESD Caution.................................................................................. 5 REVISION HISTORY 3/2020--Rev. 0 to Rev. A Changes to Channel Temperature Parameter and Continuous Power Dissipation, PDISS (TA = 85C, Derate 32.1 mW/C Above 85C) Parameter, Table 5 ................................................................ 5 12/2015--Revision 0: Initial Version Rev. A | Page 2 of 16 Data Sheet HMC930A ELECTRICAL SPECIFICATIONS DC TO 12 GHz FREQUENCY RANGE TA = 25C, VDD = 10 V, VGG2 = 3.5 V, IDD = 175 mA. Adjust VGG1 between -2 V to 0 V to achieve IDD = 175 mA, typical. Table 1. Parameter FREQUENCY RANGE GAIN Gain Flatness Gain Variation Over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept NOISE FIGURE SUPPLY CURRENT Symbol Test Conditions/Comments P1dB PSAT IP3 IDD Min DC 11.5 21 VDD = 10 V, VGG1 = -0.8 V, typical Typ Max 12 13.5 0.5 0.01 Unit GHz dB dB dB/C 18 28 dB dB 23 25 36 4.5 175 dBm dBm dBm dB mA 12 GHz TO 32 GHz FREQUENCY RANGE TA = 25C, VDD = 10 V, VGG2 = 3.5 V, IDD = 175 mA. Adjust VGG1 between -2 V to 0 V to achieve IDD = 175 mA, typical. Table 2. Parameter FREQUENCY RANGE GAIN Gain Flatness Gain Variation Over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept NOISE FIGURE SUPPLY CURRENT Symbol Test Conditions/Comments P1dB PSAT IP3 IDD VDD = 10 V, VGG1 = -0.8 V, typical Rev. A | Page 3 of 16 Min 12 11 Typ Max 32 13 0.3 0.017 Unit GHz dB dB dB/C 16 20 dB dB 22 24 33.5 5 175 dBm dBm dBm dB mA HMC930A Data Sheet 32 GHz TO 40 GHz FREQUENCY RANGE TA = 25C, VDD = 10 V, VGG2 = 3.5 V, IDD = 175 mA. Adjust VGG1 between -2 V to 0 V to achieve IDD = 175 mA, typical. Table 3. Parameter FREQUENCY RANGE GAIN Gain Flatness Gain Variation Over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept NOISE FIGURE SUPPLY CURRENT Symbol Test Conditions/Comments Min 32 10 P1dB PSAT IP3 IDD VDD = 10 V, VGG1 = -0.8 V, typical Typ 12 1.0 0.032 Unit GHz dB dB dB/C 15 20 dB dB 20 23 29 7.5 175 dBm dBm dBm dB mA TOTAL SUPPLY CURRENT BY VDD Table 4. Parameter SUPPLY CURRENT VDD = 9 V VDD = 10 V VDD = 11 V Symbol IDD Min Typ 175 175 175 Rev. A | Page 4 of 16 Max Unit mA mA mA Max 40 Data Sheet HMC930A ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Drain Bias Voltage (VDD) Gate Bias Voltage VGG1 VGG2 VDD = 12 V VDD = 8.5 V to 11 V VDD < 8.5 V RF Input Power (RFIN) Channel Temperature Continuous Power Dissipation, PDISS (TA = 85C, Derate 32.1 mW/C Above 85C) Thermal Resistance (Channel to Die Bottom) Output Power into Voltage Standing Wave Ratio (VSWR) > 7:1 Storage Temperature Range Operating Temperature Range ESD Sensitivity, Human Body Model (HBM) Rating 13 V -3 V to 0 V dc VGG2 = 5.5 V, IDD >145 mA VGG2 = (VDD - 6.5 V) up to 4.5 V VGG2 must remain > 2 V 22 dBm 175C 2.89 W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 31.1C/W 24 dBm -65C to +150C -55C to +85C Class 1A, passed 250 V Rev. A | Page 5 of 16 HMC930A Data Sheet 4 RFOUT/VDD 5 ACG2 HMC930A ACG4 ACG3 1 RFIN VGG1 2 VGG2 TOP VIEW (Not to Scale) 8 7 6 NOTES 1. DIE BOTTOM MUST BE CONNECTED TO RF/DC GROUND. 13738-002 3 ACG1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pad Configuration Table 6. Pad Function Descriptions Pad No. 1 2 Mnemonic RFIN VGG2 3 4 5 ACG1 ACG2 RFOUT/VDD1 6 7 8 ACG3 ACG4 VGG1 Die Bottom GND 1 Description RF Input. This pin is dc-coupled and matched to 50 . A blocking capacitor is required on this pin. Gate Control 2 for the Amplifier. Attach bypass capacitors as shown in Figure 37. For nominal operation, apply 3.5 V to VGG2. Low Frequency Termination 1. Attach bypass capacitors as shown in Figure 37. Low Frequency Termination 2. Attach bypass capacitors as shown in Figure 37. RF Output for the Amplifier (RFOUT). DC Bias (VDD). Connect VDD to the bias tee network to provide the drain current (IDD). See Figure 37. Low Frequency Termination 3. Attach bypass capacitors as shown in Figure 37. Low Frequency Termination 4. Attach bypass capacitors as shown in Figure 37. Gate Control 1 for the Amplifier. Attach bypass capacitors as shown in Figure 37. Follow the procedures described in the Biasing Procedures section. Die bottom must be connected to RF/dc ground. RFOUT/VDD is a multifunction pad. Rev. A | Page 6 of 16 Data Sheet HMC930A 13738-006 Figure 6. ACG3 Interface Schematic 13738-004 Figure 3. RFIN Interface Schematic VGG2 VGG1 Figure 4. VGG2 Interface Schematic Figure 7. VGG1 Interface Schematic GND 13738-005 13738-008 RFOUT/VDD ACG1 ACG3 IN 13738-007 RFIN 13738-003 INTERFACE SCHEMATICS Figure 5. ACG1 and RFOUT/VDD Interface Schematic Figure 8. GND Interface Schematic Rev. A | Page 7 of 16 HMC930A Data Sheet 20 18 10 16 S11 S21 S22 12 -20 10 -30 8 -40 5 10 20 15 25 30 35 40 45 50 FREQUENCY (GHz) 6 0 8 12 16 20 24 28 32 36 40 44 FREQUENCY (GHz) Figure 9. Gain and Return Loss Figure 12. Gain vs. Frequency for Various Temperatures 0 0 +85C +25C -55C +85C +25C -55C -10 RETURN LOSS (dB) -10 -20 -20 -30 -30 0 4 8 12 16 20 24 28 32 36 40 44 FREQUENCY (GHz) -40 13738-010 -40 Figure 10. Input Return Loss vs. Frequency for Various Temperatures 0 4 8 12 16 20 24 28 32 36 40 44 FREQUENCY (GHz) 13738-013 RETURN LOSS (dB) 4 13738-012 -10 0 +85C +25C -55C 14 GAIN (dB) 0 13738-009 RESPONSE (dB) TYPICAL PERFORMANCE CHARACTERISTICS Figure 13. Output Return Loss vs. Frequency for Various Temperatures 10 20 +85C +25C -55C 0 NOISE FIGURE (dB) 8 S11 S21 S22 -10 -20 6 4 -30 2 -50 0.00001 0.0001 0.001 0.01 0.1 1 FREQUENCY (GHz) 10 Figure 11. Low Frequency Gain and Return Loss 0 0 4 8 12 16 20 24 28 32 36 40 FREQUENCY (GHz) Figure 14. Noise Figure vs. Frequency for Various Temperatures Rev. A | Page 8 of 16 13738-014 -40 13738-011 RESPONSE (dB) 10 HMC930A 30 30 28 28 26 26 P1dB (dBm) 24 22 +85C +25C -55C 20 8V 10V 11V 4 8 12 16 20 24 28 32 36 40 FREQUENCY (GHz) 16 13738-015 0 0 8 12 16 20 24 28 32 36 40 FREQUENCY (GHz) Figure 15. P1dB vs. Frequency for Various Temperatures Figure 18. P1dB vs. Frequency for Various Supply Voltages 30 28 28 26 26 PSAT (dBm) 30 24 +85C +25C -55C 22 4 13738-018 18 16 24 22 8V 10V 11V 20 20 0 4 8 12 16 20 24 28 32 36 40 FREQUENCY (GHz) 18 13738-016 18 0 8 12 16 20 24 28 32 36 40 FREQUENCY (GHz) Figure 16. PSAT vs. Frequency for Various Temperatures Figure 19. PSAT vs. Frequency for Various Supply Voltages 30 28 28 26 26 PSAT (dBm) 30 24 22 20 4 13738-019 PSAT (dBm) 22 20 18 24 22 20 125mA 175mA 18 125mA 175mA 18 16 0 4 8 12 16 20 24 28 32 36 FREQUENCY (GHz) 40 13738-017 P1dB (dBm) 24 Figure 17. P1dB vs. Frequency and Supply Current 16 0 4 8 12 16 20 24 28 32 36 FREQUENCY (GHz) Figure 20. PSAT vs. Frequency and Supply Current Rev. A | Page 9 of 16 40 13738-020 P1dB (dBm) Data Sheet HMC930A Data Sheet 42 42 40 40 +85C +25C -55C 38 36 34 32 34 32 30 30 28 28 26 26 0 4 8 12 16 20 24 28 32 36 40 FREQUENCY (GHz) 24 13738-021 24 0 4 8 12 16 20 24 28 32 Figure 21. Output IP3 vs. Frequency for Various Temperatures at POUT = 14 dBm/Tone 40 Figure 24. Output IP3 vs. Frequency for Various Supply Voltages at POUT = 14 dBm/Tone 80 42 125mA 175mA 40 2GHz 8GHz 14GHz 20GHz 28GHz 34GHz 40GHz 70 38 60 36 IM3 (dBc) 50 IP3 (dBm) 36 FREQUENCY (GHz) 13738-024 IP3 (dBm) 36 IP3 (dBm) 8V 10V 11V 38 34 32 40 30 30 20 28 0 4 8 12 16 20 24 28 32 36 40 FREQUENCY (GHz) 0 13738-022 24 0 2 6 8 10 12 14 16 POUT/TONE (dBm) Figure 25. Output IM3 at VDD = 8 V Figure 22. Output IP3 vs. Frequency and Supply Current at POUT = 14 dBm/Tone 80 2GHz 8GHz 14GHz 20GHz 28GHz 34GHz 40GHz 70 60 60 50 IM3 (dBc) 50 40 40 30 20 20 10 10 0 2 4 6 8 10 POUT/TONE (dBm) 12 14 16 13738-023 30 0 2GHz 8GHz 14GHz 20GHz 28GHz 34GHz 40GHz 70 Figure 23. Output Third-Order Intermodulation Tone (IM3) at VDD = 10 V Rev. A | Page 10 of 16 0 0 2 4 6 8 10 12 POUT/TONE (dBm) Figure 26. Output IM3 at VDD = 11 V 14 16 13738-026 80 IM3 (dBc) 4 13738-025 10 26 Data Sheet HMC930A 30 250 POUT GAIN PAE IDD -10 POUT (dBm), GAIN (dB), PAE (%) ISOLATION (dB) -20 -30 -40 -50 +85C +25C -55C -60 25 235 20 220 15 205 10 190 5 175 IDD (mA) 0 -70 4 8 12 16 20 24 28 32 36 40 44 FREQUENCY (GHz) 160 0 2 0 8 10 12 14 16 18 Figure 30. Power Compression at 20 GHz 35 GAIN (dB), P1dB (dBm), PSAT (dBm) GAIN P1dB PSAT 30 25 20 10 125 135 145 155 165 175 IDD (mA) Figure 28. Gain and Power (P1dB and PSAT) vs. Supply Current (IDD) at 20 GHz 25 20 15 10 13738-028 15 GAIN P1dB PSAT 30 8 9 10 11 VDD (V) 13738-031 35 Figure 31. Gain and Power (P1dB and PSAT) vs. Supply Voltage (VDD) at 20 GHz 3 70 4GHz 10GHz 20GHz 30GHz 40GHz SECOND HARMONIC (dBc) 60 2 1 +85C +25C -40C 50 40 30 20 10 0 3 6 9 INPUT POWER (dBm) Figure 29. Power Dissipation 12 15 0 13738-029 0 0 4 8 12 16 FREQUENCY (GHz) 20 24 13738-032 GAIN (dB), P1dB (dBm), PSAT (dBm) 6 INPUT POWER (dBm) Figure 27. Reverse Isolation vs. Frequency for Various Temperatures POWER DISSIPATION (W) 4 13738-030 0 13738-027 -80 Figure 32. Second-Order Harmonic vs. Frequency for Various Temperatures at POUT = 14 dBm, VDD = 10 V, VGG = 3.5 V, and IDD = 175 mA Rev. A | Page 11 of 16 HMC930A Data Sheet 70 40 30 20 10 0 0 4 8 12 16 FREQUENCY (GHz) 20 24 Figure 33. Second-Order Harmonic vs. Frequency for Various POUT Values, VDD = 10 V, VGG = 3.5 V, and IDD = 175 mA 60 8V 10V 11V 50 40 30 20 10 0 0 4 8 12 16 FREQUENCY (GHz) 20 24 13738-034 50 SECOND-ORDER HARMONIC (dBc) 4dBm 6dBm 8dBm 10dBm 12dBm 14dBm 60 13738-033 SECOND-ORDER HARMONIC (dBc) 70 Figure 34. Second-Order Harmonic vs. Frequency for Various VDD Values at POUT = 14 dBm and IDD = 175 mA Rev. A | Page 12 of 16 Data Sheet HMC930A THEORY OF OPERATION VDD RFOUT VGG2 RFIN VGG1 13738-039 The HMC930A is a GaAs, pHEMT, MMIC, cascaded, distributed power amplifier. The cascade distributed architecture uses a fundamental cell consisting of a stack of two field effect transistors (FETs) connected from source to drain. The basic schematic for a fundamental cell is shown in Figure 35. The fundamental cell is duplicated several times, with transmission lines connecting the drains of the top devices and the gates of the bottom devices, respectively. Additional circuit design techniques around each cell optimize the overall response. The major benefit of this architecture is that acceptable gain is maintained across a bandwidth that is far greater than what is typically provided by a single instance of the fundamental cell. Figure 35. Fundamental Cell Schematic To obtain the best performance from the HMC930A and to avoid damaging the device, follow the recommended biasing sequences described in the Biasing Procedures section. Rev. A | Page 13 of 16 HMC930A Data Sheet APPLICATIONS INFORMATION + - 4.7F + 4.7F - 50 TRANSMISSION LINE = 100pF AND 0.01F INTEGRATED INTO ONE CASE 3mil NOMINAL GAP 4.7F = 100F + - - + 13738-035 = 0.01F 4.7F 1mil GOLD WIRE Figure 36. Assembly Diagram 0.01F + ACG1 100pF 4.7F VDD 3 VGG2 4.7F ACG2 2 + 0.01F 4 100pF 5 RFOUT 6 RFIN ACG3 7 1 8 100pF ACG4 0.01F VGG1 100pF 0.01F + 4.7F 13738-036 + 4.7F Figure 37. Application Circuit BIASING PROCEDURES Capacitive bypassing is required for both VGG1 and VGG2, as shown in Figure 37. The capacitors to ground required for the ACG1 through ACG4 pads act as low frequency terminations; this helps flatten the overall frequency response by diminishing the gain at low frequencies. The recommended biasing sequence during power-up is as follows: 1. 2. 3. 4. 5. 6. Connect to GND. Set VGG1 to -2 V to pinch off the drain current. Set VDD to 10 V (the drain current is pinched off). Set VGG2 to 3.5 V (the drain current is pinched off). Adjust VGG1 in a positive direction until a quiescent current (IDD) of 175 mA is obtained. Apply the RF signal. The recommended biasing sequence during power-down is as follows: 1. 2. 3. 4. 5. Turn off the RF signal. Set VGG1 to -2 V to pinch off the drain current. Set VGG2 to 0 V. Set VDD to 0 V. Set VGG1 to 0 V. All measurements for the HMC930A are taken using the typical application circuit (see Figure 37) configured as shown Figure 36. The bias conditions shown in the Electrical Specifications section are the operating points recommended to optimize the overall performance. Unless otherwise noted, the data shown is taken using the recommended bias conditions. Operation of the HMC930A at different bias conditions may provide performance that differs from what is shown in the Typical Performance Characteristics section. Rev. A | Page 14 of 16 Data Sheet HMC930A Handling Precautions MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Attach the die directly to the ground plane eutectically or with conductive epoxy (see the Handling Precautions section, the Mounting section, and the Wire Bonding section). Microstrip, 50 , transmission lines on 0.127 mm (5 mil) thick alumina, thin film substrates are recommended for bringing the radio frequency to and from the chip (see Figure 38). When using 0.254 mm (10 mil) thick alumina thin film substrates, raise the die 0.150 mm (6 mils) to ensure that the surface of the die is coplanar with the surface of the substrate. One way to accomplish this is to attach the 0.102 mm (4 mil) thick die to a 0.150 mm (6 mil) thick, molybdenum (Mo) heat spreader (moly tab), which is then attached to the ground plane (see Figure 38). To avoid permanent damage, follow these storage, cleanliness, static sensitivity, transient, and general handling precautions: * * * * * 0.102mm (0.004") THICK GaAs MMIC WIRE BOND 0.076mm (0.003") Place all bare die in either waffle or gel-based ESD protective containers and then seal the die in an ESD protective bag for shipment. Once the sealed ESD protective bag is opened, store all die in a dry nitrogen environment. Handle the chips in a clean environment. Do not attempt to clean the chip using liquid cleaning systems. Follow ESD precautions to protect against ESD strikes. While bias is applied, suppress instrument and bias supply transients. Use shielded signal and bias cables to minimize inductive pick up. Handle the chip along the edges with a vacuum collet or with a sharp pair of bent tweezers. The surface of the chip may have fragile air bridges and must not be touched with vacuum collet, tweezers, or fingers. Mounting The chip is back metallized and can be die mounted with AuSn eutectic preforms or with electrically conductive epoxy. Ensure that the mounting surface is clean and flat. RF GROUND PLANE 13738-037 0.127mm (0.005") THICK ALUMINA THIN FILM SUBSTRATE When attaching eutectic die, an 80/20 gold tin preform is recommended with a work surface temperature of 255C and a tool temperature of 265C. When hot 90/10 nitrogen/hydrogen gas is applied, ensure that tool tip temperature is 290C. Do not expose the chip to a temperature greater than 320C for more than 20 seconds. For attachment, no more than 3 seconds of scrubbing is required. Figure 38. Die Without the Moly Tab When attaching epoxy die, apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip once it is placed into position. Cure epoxy per the schedule of the manufacturer. 0.102mm (0.004") THICK GaAs MMIC WIRE BOND 0.076mm (0.003") Wire Bonding RF bonds made with two 1 mil wires are recommended. Ensure that these bonds are thermosonically bonded with a force of 40 grams to 60 grams. DC bonds of a 0.001" (0.025 mm) diameter, thermosonically bonded, are recommended. Make ball bonds with a force of 40 grams to 50 grams and wedge bonds with a force of 18 grams to 22 grams. Make all bonds with a nominal stage temperature of 150C. Apply a minimum amount of ultrasonic energy to achieve reliable bonds. Make all bonds as short as possible, less than 12 mils (0.31 mm). RF GROUND PLANE 0.254mm (0.010") THICK ALUMINA THIN FILM SUBSTRATE 13738-038 0.150mm (0.005") THICK MOLY TAB Figure 39. Die With the Moly Tab Place microstrip substrates as close to the die as possible to minimize bond wire length. Typical die to substrate spacing is 0.076 mm to 0.152 mm (3 mil to 6 mil). Rev. A | Page 15 of 16 HMC930A Data Sheet OUTLINE DIMENSIONS 2.820 0.100 0.154 0.086 0.100 x 0.100 3 4 0.199 0.511 5 0.199 2 0.187 1.500 0.208 0.742 1 0.199 0.155 7 6 1.733 SIDE VIEW (CIRCUIT SIDE) 0.150 0.150 0.206 0.382 10-21-2015-A 8 TOP VIEW 0.097 Figure 40. 8-Pad Bare Die [CHIP] (C-8-6) Dimensions shown in millimeter DIE PACKAGING INFORMATION Standard GP-2 (Gel Pack) Alternate Packaging For alternate packaging information, contact Analog Devices, Inc. ORDERING GUIDE Model HMC930A Temperature Range -55C to +85C Package Description 8-Pad Bare Die [CHIP] (c)2015-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13738-0-3/20(A) Rev. A | Page 16 of 16 Package Option C-8-6