GaAs, pHEMT, MMIC,
0.25 W Power Amplifier, DC to 40 GHz
Data Sheet
HMC930A
Rev. A Document Feedback
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FEATURES
High output power for 1 dB compression (P1dB): 22 dBm
High saturated output power (PSAT): 24 dBm
High gain: 13 dB
High output third-order intercept (IP3): 33.5 dBm
Supply voltage: 10 V at 175 mA
50 Ω matched input/output
Die size: 2.82 mm × 1.50 mm × 0.1 mm
APPLICATIONS
Test instrumentation
Microwave radios and VSATs
Military and space
Telecommunications infrastructure
Fiber optics
FUNCTIONAL BLOCK DIAGRAM
1
2
3 4
5
67
8
VGG1
VGG2
RFIN
ACG4
ACG3
ACG1
ACG2
RFOUT/VDD
HMC930A
13738-001
Figure 1.
GENERAL DESCRIPTION
The HMC930A is a gallium arsenide (GaAs), pseudomorphic,
high electron mobility transfer (pHEMT), monolithic microwave
integrated circuit (MMIC), distributed power amplifier that
operates from dc to 40 GHz. The HMC930A provides 13 dB of
gain, 33.5 dBm output IP3, and 22 dBm of output power at
1 dB gain compression, requiring 175 mA from a 10 V supply.
The HMC930A exhibits a slightly positive gain slope from
8 GHz to 32 GHz, making it ideal for electronic warfare (EW),
electronic countermeasures (ECM), radar, and test equipment
applications. The HMC930A amplifier inputs/outputs (I/Os) are
internally matched to 50 Ω, facilitating integration into multichip
modules (MCMs). All data is taken with the chip connected via
two 0.025 mm (1 mil) wire bonds of minimal length at 0.31 mm
(12 mils).
HMC930A Data Sheet
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Electrical Specifications ................................................................... 3
DC to 12 GHz Frequency Range ................................................ 3
12 GHz to 32 GHz Frequency Range ........................................ 3
32 GHz to 40 GHz Frequency Range ........................................ 4
Total Supply Current by VDD ...................................................... 4
Absolute Maximum Ratings ........................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions .............................6
Interface Schematics .....................................................................7
Typical Performance Characteristics .............................................8
Theory of Operation ...................................................................... 13
Applications Information ............................................................. 14
Biasing Procedures ..................................................................... 14
Mounting and Bonding Techniques for Millimeterwave
GaAs MMICs .............................................................................. 15
Outline Dimensions ....................................................................... 16
Die Packaging Information ...................................................... 16
Ordering Guide .............................................................................. 16
REVISION HISTORY
3/2020—Rev. 0 to Rev. A
Changes to Channel Temperature Parameter and Continuous
Power Dissipation, PDISS (TA = 85°C, Derate 32.1 mW/°C Above
85°C) Parameter, Table 5 ................................................................ 5
12/2015—Revision 0: Initial Version
Data Sheet HMC930A
Rev. A | Page 3 of 16
ELECTRICAL SPECIFICATIONS
DC TO 12 GHz FREQUENCY RANGE
TA = 25°C, VDD = 10 V, VGG2 = 3.5 V, IDD = 175 mA. Adjust VGG1 between −2 V to 0 V to achieve IDD = 175 mA, typical.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE DC 12 GHz
GAIN 11.5 13.5 dB
Gain Flatness ±0.5 dB
Gain Variation Over Temperature 0.01 dB/°C
RETURN LOSS
Input 18 dB
Output 28 dB
OUTPUT
Output Power for 1 dB Compression P1dB 21 23 dBm
Saturated Output Power PSAT 25 dBm
Output Third-Order Intercept
IP3
36
dBm
NOISE FIGURE 4.5 dB
SUPPLY CURRENT IDD VDD = 10 V, VGG1 = −0.8 V, typical 175 mA
12 GHz TO 32 GHz FREQUENCY RANGE
TA = 25°C, VDD = 10 V, VGG2 = 3.5 V, IDD = 175 mA. Adjust VGG1 between −2 V to 0 V to achieve IDD = 175 mA, typical.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 12 32 GHz
GAIN 11 13 dB
Gain Flatness ±0.3 dB
Gain Variation Over Temperature 0.017 dB/°C
RETURN LOSS
Input 16 dB
Output 20 dB
OUTPUT
Output Power for 1 dB Compression P1dB 22 dBm
Saturated Output Power PSAT 24 dBm
Output Third-Order Intercept IP3 33.5 dBm
NOISE FIGURE 5 dB
SUPPLY CURRENT IDD VDD = 10 V, VGG1 = −0.8 V, typical 175 mA
HMC930A Data Sheet
Rev. A | Page 4 of 16
32 GHz TO 40 GHz FREQUENCY RANGE
TA = 25°C, VDD = 10 V, VGG2 = 3.5 V, IDD = 175 mA. Adjust VGG1 between −2 V to 0 V to achieve IDD = 175 mA, typical.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 32 40 GHz
GAIN 10 12 dB
Gain Flatness ±1.0 dB
Gain Variation Over Temperature 0.032 dB/°C
RETURN LOSS
Input 15 dB
Output 20 dB
OUTPUT
Output Power for 1 dB Compression P1dB 20 dBm
Saturated Output Power PSAT 23 dBm
Output Third-Order Intercept IP3 29 dBm
NOISE FIGURE 7.5 dB
SUPPLY CURRENT IDD VDD = 10 V, VGG1 = −0.8 V, typical 175 mA
TOTAL SUPPLY CURRENT BY VDD
Table 4.
Parameter Symbol Min Typ Max Unit
SUPPLY CURRENT IDD
VDD = 9 V 175 mA
VDD = 10 V 175 mA
VDD = 11 V 175 mA
Data Sheet HMC930A
Rev. A | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Drain Bias Voltage (VDD) 13 V
Gate Bias Voltage
VGG1 −3 V to 0 V dc
VGG2
VDD = 12 V VGG2 = 5.5 V, IDD >145 mA
VDD = 8.5 V to 11 V VGG2 = (VDD − 6.5 V) up to
4.5 V
VDD < 8.5 V VGG2 must remain > 2 V
RF Input Power (RFIN) 22 dBm
Channel Temperature 175°C
Continuous Power Dissipation, PDISS
(TA = 85°C, Derate 32.1 mW/°C
Above 85°C)
2.89 W
Thermal Resistance
(Channel to Die Bottom)
31.1°C/W
Output Power into Voltage Standing
Wave Ratio (VSWR) > 7:1
24 dBm
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −55°C to +85°C
ESD Sensitivity, Human Body Model
(HBM)
Class 1A, passed 250 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
ESD CAUTION
HMC930A Data Sheet
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3 4
5
678
V
GG
1
V
GG
2
RFIN
ACG4
ACG3
ACG1
ACG2
RFOUT/V
DD
HMC930A
TOP VIEW
(No t t o Scal e)
NOTES
1. DI E BOT TOM M US T BE CONNECT E D TO RF/DC GRO UND.
13738-002
Figure 2. Pad Configuration
Table 6. Pad Function Descriptions
Pad No. Mnemonic Description
1 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. A blocking capacitor is required on this pin.
2 VGG2 Gate Control 2 for the Amplifier. Attach bypass capacitors as shown in Figure 37. For nominal operation,
apply 3.5 V to VGG2.
3 ACG1 Low Frequency Termination 1. Attach bypass capacitors as shown in Figure 37.
4 ACG2 Low Frequency Termination 2. Attach bypass capacitors as shown in Figure 37.
5 RFOUT/VDD1 RF Output for the Amplifier (RFOUT).
DC Bias (V
DD
). Connect V
DD
to the bias tee network to provide the drain current (I
DD
). See Figure 37.
6 ACG3 Low Frequency Termination 3. Attach bypass capacitors as shown in Figure 37.
7 ACG4 Low Frequency Termination 4. Attach bypass capacitors as shown in Figure 37.
8 VGG1 Gate Control 1 for the Amplifier. Attach bypass capacitors as shown in Figure 37. Follow the procedures
described in the Biasing Procedures section.
Die Bottom GND Die bottom must be connected to RF/dc ground.
1 RFOUT/VDD is a multifunction pad.
Data Sheet HMC930A
Rev. A | Page 7 of 16
INTERFACE SCHEMATICS
RFIN
13738-003
Figure 3. RFIN Interface Schematic
V
GG
2
13738-004
Figure 4. VGG2 Interface Schematic
ACG1 RFOUT/V
DD
13738-005
Figure 5. ACG1 and RFOUT/VDD Interface Schematic
IN ACG3
13738-006
Figure 6. ACG3 Interface Schematic
V
GG
1
13738-007
Figure 7. VGG1 Interface Schematic
GND
13738-008
Figure 8. GND Interface Schematic
HMC930A Data Sheet
Rev. A | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
20
–40
–30
–20
–10
0
10
0 5 1510 20 25 30 35 40 45 50
RESPONSE (dB)
FRE Q UE NCY ( GHz)
S11
S21
S22
13738-009
Figure 9. Gain and Return Loss
0
–40
–30
–20
–10
0 4 12816 20 24 28 32 36 4440
RETURN LO S S ( dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–55°C
13738-010
Figure 10. Input Return Loss vs. Frequency for Various Temperatures
20
–50
–30
–10
10
–40
–20
0
0.00001 0.0001 0.010.001 0.1 110
RESPONSE (dB)
FRE Q UE NCY ( GHz)
S11
S21
S22
13738-011
Figure 11. Low Frequency Gain and Return Loss
18
6
8
10
12
14
16
0 4 12816 20 24 28 32 36 4440
GAI N (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–55°C
13738-012
Figure 12. Gain vs. Frequency for Various Temperatures
0
–40
–30
–20
–10
0 4 12816 20 24 28 32 36 4440
RET URN LOS S ( dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–55°C
13738-013
Figure 13. Output Return Loss vs. Frequency for Various Temperatures
10
0
4
8
2
6
03632282420161284 40
NOISE FIGURE (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–55°C
13738-014
Figure 14. Noise Figure vs. Frequency for Various Temperatures
Data Sheet HMC930A
Rev. A | Page 9 of 16
30
16
20
28
18
24
26
22
03632282420161284 40
P1dB (dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–55°C
13738-015
Figure 15. P1dB vs. Frequency for Various Temperatures
30
18
20
28
24
26
22
03632
282420161284 40
P
SAT
(d Bm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–55°C
13738-016
Figure 16. PSAT vs. Frequency for Various Temperatures
30
16
18
20
28
24
26
22
03632282420161284 40
P1d B ( dBm)
FRE Q UE NCY ( GHz)
125mA
175mA
13738-017
Figure 17. P1dB vs. Frequency and Supply Current
30
16
20
28
18
24
26
22
03632282420161284 40
P1dB (dBm)
FRE Q UE NCY ( GHz)
8V
10V
11V
13738-018
Figure 18. P1dB vs. Frequency for Various Supply Voltages
30
18
20
28
24
26
22
03632282420161284 40
P
SAT
(d Bm)
FRE Q UE NCY ( GHz)
8V
10V
11V
13738-019
Figure 19. PSAT vs. Frequency for Various Supply Voltages
30
16
18
20
28
24
26
22
03632282420161284 40
P
SAT
(d Bm)
FRE Q UE NCY ( GHz)
125mA
175mA
13738-020
Figure 20. PSAT vs. Frequency and Supply Current
HMC930A Data Sheet
Rev. A | Page 10 of 16
42
24
26
40
32
36
38
30
34
28
03632282420161284 40
IP3 (dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–55°C
13738-021
Figure 21. Output IP3 vs. Frequency for Various Temperatures at
POUT = 14 dBm/Tone
42
24
26
40
32
36
38
30
34
28
03632282420161284 40
IP3 (dBm)
FRE Q UE NCY ( GHz)
125mA
175mA
13738-022
Figure 22. Output IP3 vs. Frequency and Supply Current at
POUT = 14 dBm/Tone
80
0
70
30
50
60
20
40
10
01412108642 16
IM 3 ( dBc)
POUT/TONE (dBm)
2GHz
8GHz
14GHz
20GHz
28GHz
34GHz
40GHz
13738-023
Figure 23. Output Third-Order Intermodulation Tone (IM3) at VDD = 10 V
42
24
26
40
32
36
38
30
34
28
03632282420161284 40
IP3 (dBm)
FRE Q UE NCY ( GHz)
8V
10V
11V
13738-024
Figure 24. Output IP3 vs. Frequency for Various Supply Voltages at
POUT = 14 dBm/Tone
80
0
70
30
50
60
20
40
10
0141210
8642 16
IM 3 ( dBc)
POUT/TONE (dBm)
2GHz
8GHz
14GHz
20GHz
28GHz
34GHz
40GHz
13738-025
Figure 25. Output IM3 at VDD = 8 V
80
0
70
30
50
60
20
40
10
0141210864
216
IM 3 ( dBc)
POUT/TONE (dBm)
2GHz
8GHz
14GHz
20GHz
28GHz
34GHz
40GHz
13738-026
Figure 26. Output IM3 at VDD = 11 V
Data Sheet HMC930A
Rev. A | Page 11 of 16
0
–80
–10
–50
–30
–20
–60
–40
–70
03224 362820161284 4440
ISOLATION (dB)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–55°C
13738-027
Figure 27. Reverse Isolation vs. Frequency for Various Temperatures
35
10
30
20
25
15
125 165155145135 175
GAI N (dB) , P1d B ( dBm), P
SAT
(d Bm)
I
DD
(mA)
GAIN
P1dB
P
SAT
13738-028
Figure 28. Gain and Power (P1dB and PSAT) vs. Supply Current (IDD) at 20 GHz
3
0
2
1
0 93 12615
POWER DISSIPATI O N (W)
INPUT POWE R ( dBm)
4GHz
10GHz
20GHz
30GHz
40GHz
13738-029
Figure 29. Power Dissipation
30
0
25
5
15
20
10
250
160
235
175
205
220
190
016
12 14108642 18
P
OUT
(d Bm) , GAIN (d B), P AE ( %)
I
DD
(mA)
INPUT POWE R ( dBm)
P
OUT
GAIN
PAE
I
DD
13738-030
Figure 30. Power Compression at 20 GHz
35
10
30
20
25
15
810911
GAI N (dB) , P1d B ( dBm), PSAT (dBm)
VDD (V)
GAIN
P1dB
PSAT
13738-031
Figure 31. Gain and Power (P1dB and PSAT) vs. Supply Voltage (VDD) at 20 GHz
70
0
10
50
30
20
60
40
020161284 24
SECO ND HARM ONI C ( dBc)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
13738-032
Figure 32. Second-Order Harmonic vs. Frequency for Various Temperatures
at POUT = 14 dBm, VDD = 10 V, VGG = 3.5 V, and IDD = 175 mA
HMC930A Data Sheet
Rev. A | Page 12 of 16
70
0
10
50
30
20
60
40
020161284 24
SECO ND- ORDER HARM ONIC ( dBc)
FRE Q UE NCY ( GHz)
4dBm
6dBm
8dBm
10dBm
12dBm
14dBm
13738-033
Figure 33. Second-Order Harmonic vs. Frequency for Various POUT Values,
VDD = 10 V, VGG = 3.5 V, and IDD = 175 mA
70
0
10
50
30
20
60
40
020161284 24
SECO ND- ORDER HARM ONIC ( dBc)
FRE Q UE NCY ( GHz)
8V
10V
11V
13738-034
Figure 34. Second-Order Harmonic vs. Frequency for Various VDD Values
at POUT = 14 dBm and IDD = 175 mA
Data Sheet HMC930A
Rev. A | Page 13 of 16
THEORY OF OPERATION
The HMC930A is a GaAs, pHEMT, MMIC, cascaded, distributed
power amplifier. The cascade distributed architecture uses a
fundamental cell consisting of a stack of two field effect trans-
istors (FETs) connected from source to drain. The basic schematic
for a fundamental cell is shown in Figure 35. The fundamental
cell is duplicated several times, with transmission lines connecting
the drains of the top devices and the gates of the bottom devices,
respectively. Additional circuit design techniques around each
cell optimize the overall response. The major benefit of this
architecture is that acceptable gain is maintained across a
bandwidth that is far greater than what is typically provided
by a single instance of the fundamental cell.
13738-039
RFOUT
V
GG
2
V
GG
1
RFIN
V
DD
Figure 35. Fundamental Cell Schematic
To obtain the best performance from the HMC930A and to
avoid damaging the device, follow the recommended biasing
sequences described in the Biasing Procedures section.
HMC930A Data Sheet
Rev. A | Page 14 of 16
APPLICATIONS INFORMATION
4.7µF
= 100pF AND 0. 01µ F
INT E GRAT E D INTO O NE CAS E
50Ω
TRANSMISSION
LINE
1mil
GOLD WIRE
3mil
NOM I NAL G AP
++ –
+ –
–
+–
= 0.01µF
= 100µF
4.7µF
4.7µF
4.7µF
13738-035
Figure 36. Assembly Diagram
+ 4.7µF
+
4.7µF
+
4.7µ F
+ 4.7µF
0.01µF
0.01µF
0.01µF
0.01µF100pF
100pF
100pF
100pF
ACG4
ACG1
1
2
3
45
6
7
8
ACG2
V
DD
RFOUT
V
GG
1
RFIN
V
GG
2
ACG3
13738-036
Figure 37. Application Circuit
BIASING PROCEDURES
Capacitive bypassing is required for both VGG1 and VGG2, as
shown in Figure 37. The capacitors to ground required for the
ACG1 through ACG4 pads act as low frequency terminations;
this helps flatten the overall frequency response by diminishing
the gain at low frequencies.
The recommended biasing sequence during power-up is as
follows:
1. Connect to GND.
2. Set VGG1 to −2 V to pinch off the drain current.
3. Set VDD to 10 V (the drain current is pinched off).
4. Set VGG2 to 3.5 V (the drain current is pinched off).
5. Adjust VGG1 in a positive direction until a quiescent
current (IDD) of 175 mA is obtained.
6. Apply the RF signal.
The recommended biasing sequence during power-down is as
follows:
1. Turn off the RF signal.
2. Set VGG1 to −2 V to pinch off the drain current.
3. Set VGG2 to 0 V.
4. Set VDD to 0 V.
5. Set VGG1 to 0 V.
All measurements for the HMC930A are taken using the typical
application circuit (see Figure 37) configured as shown Figure 36.
The bias conditions shown in the Electrical Specifications section
are the operating points recommended to optimize the overall
performance. Unless otherwise noted, the data shown is taken
using the recommended bias conditions. Operation of the
HMC930A at different bias conditions may provide performance
that differs from what is shown in the Typical Performance
Characteristics section.
Data Sheet HMC930A
Rev. A | Page 15 of 16
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETERWAVE GaAs MMICS
Attach the die directly to the ground plane eutectically or with
conductive epoxy (see the Handling Precautions section, the
Mounting section, and the Wire Bonding section).
Microstrip, 50 Ω, transmission lines on 0.127 mm (5 mil) thick
alumina, thin film substrates are recommended for bringing the
radio frequency to and from the chip (see Figure 38). When
using 0.254 mm (10 mil) thick alumina thin film substrates,
raise the die 0.150 mm (6 mils) to ensure that the surface of the
die is coplanar with the surface of the substrate. One way to
accomplish this is to attach the 0.102 mm (4 mil) thick die to a
0.150 mm (6 mil) thick, molybdenum (Mo) heat spreader
(moly tab), which is then attached to the ground plane (see
Figure 38).
0.102mm ( 0. 004") THI CK GaAs MMIC
WIRE BO ND
RF G ROUND PLANE
0.127mm ( 0. 005") THI CK ALUMINA
THIN FILM SUBSTRATE
0.076mm
(0.003")
13738-037
Figure 38. Die Without the Moly Tab
0.254mm ( 0. 010") THI CK ALUMINA
THIN FILM SUBSTRATE
0.150mm ( 0. 005") THI CK
MOLY TAB
0.102mm ( 0. 004") THI CK GaAs MMIC
WIRE BO ND
0.076mm
(0.003")
RF GROUND P LANE
13738-038
Figure 39. Die With the Moly Tab
Place microstrip substrates as close to the die as possible to
minimize bond wire length. Typical die to substrate spacing is
0.076 mm to 0.152 mm (3 mil to 6 mil).
Handling Precautions
To avoid permanent damage, follow these storage, cleanliness,
static sensitivity, transient, and general handling precautions:
• Place all bare die in either waffle or gel-based ESD
protective containers and then seal the die in an ESD
protective bag for shipment. Once the sealed ESD
protective bag is opened, store all die in a dry nitrogen
environment.
• Handle the chips in a clean environment. Do not attempt
to clean the chip using liquid cleaning systems.
• Follow ESD precautions to protect against ESD strikes.
• While bias is applied, suppress instrument and bias supply
transients. Use shielded signal and bias cables to minimize
inductive pick up.
• Handle the chip along the edges with a vacuum collet or
with a sharp pair of bent tweezers. The surface of the chip
may have fragile air bridges and must not be touched with
vacuum collet, tweezers, or fingers.
Mounting
The chip is back metallized and can be die mounted with AuSn
eutectic preforms or with electrically conductive epoxy. Ensure
that the mounting surface is clean and flat.
When attaching eutectic die, an 80/20 gold tin preform is
recommended with a work surface temperature of 255°C and a
tool temperature of 265°C. When hot 90/10 nitrogen/hydrogen
gas is applied, ensure that tool tip temperature is 290°C. Do not
expose the chip to a temperature greater than 320°C for more
than 20 seconds. For attachment, no more than 3 seconds of
scrubbing is required.
When attaching epoxy die, apply a minimum amount of epoxy
to the mounting surface so that a thin epoxy fillet is observed
around the perimeter of the chip once it is placed into position.
Cure epoxy per the schedule of the manufacturer.
Wire Bonding
RF bonds made with two 1 mil wires are recommended. Ensure
that these bonds are thermosonically bonded with a force of
40 grams to 60 grams. DC bonds of a 0.001” (0.025 mm)
diameter, thermosonically bonded, are recommended. Make
ball bonds with a force of 40 grams to 50 grams and wedge
bonds with a force of 18 grams to 22 grams. Make all bonds
with a nominal stage temperature of 150°C. Apply a minimum
amount of ultrasonic energy to achieve reliable bonds. Make all
bonds as short as possible, less than 12 mils (0.31 mm).
HMC930A Data Sheet
Rev. A | Page 16 of 16
OUTLINE DIMENSIONS
10-21-2015-A
TOP VIEW
(CIRCUI T SIDE)
SIDE VIEW
1.500
2.820
1.733
0.199
0.199
0.742
1
5
2
34
6
7
8
0.382
0.2060.150
0.150
0.155
0.199
0.208
0.187
0.097
0.511
0.086 0.154
0.100
0.100 ×0.100
Figure 40. 8-Pad Bare Die [CHIP]
(C-8-6)
Dimensions shown in millimeter
DIE PACKAGING INFORMATION
Standard Alternate Packaging
GP-2 (Gel Pack) For alternate packaging information, contact Analog Devices, Inc.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
HMC930A −55°C to +85°C 8-Pad Bare Die [CHIP] C-8-6
©2015–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13738-0-3/20(A)
