NCP1030DMR2G - ON Semiconductor

Semiconductor Components Industries, LLC, 2010

December, 2010 -- Rev. 10

1Publication Order Number:

NCP1030/D

NCP1030, NCP1031

Low Power PWM Controller

with On--Chip Power Switch

and Startup Circuits for

48 V Telecom Systems

The NCP1030 and NCP1031 are a family of miniature high--voltage

monolithic switching regulators with on--chip Power Switch and Startup

Circuits. The NCP103x family incorporates in a single IC all the active

power, control logic and protection circuitry required to implement, with

minimal external components, several switching regulator applications,

such as a secondary side bias supply or a low power dc--dc converter.

This controller family is ideally suited for 48 V telecom, 42 V automotive

and 12 V input applications. The NCP103x can be configured in any

single--ended topology such as forward or flyback. The NCP1030 is

targeted for applications requiring up to 3 W, and the NCP1031 is

targeted for applications requiring up to 6 W.

The internal error amplifier allows the NCP103x family to be easily

configured for secondary or primary side regulation operation in

isolated and non--isolated configurations. The fixed frequency oscillator

is optimized for operation up to 1 MHz and is capable of external

frequency synchronization, providing additional design flexibility. In

addition, the NCP103x incorporates individual line undervoltage and

overvoltage detectors, cycle by cycle current limit and thermal

shutdown to protect the controller under fault conditions. The preset

current limit thresholds eliminate the need for external sensing

components.

Features

On Chip High 200 V Power Switch Circuit and Startup Circuit

Internal Startup Regulator with Auxiliary Winding Override

Operationupto1MHz

External Frequency Synchronization Capability

Frequency Fold--down Under Fault Conditions

Trimmed 2% Internal Reference

Line Undervoltage and Overvoltage Detectors

Cycle by Cycle Current Limit Using SENSEFET

Active LEB Circuit

Overtemperature Protection

Internal Error Amplifier

Pb--Free Packages are Available

Typical Applications

POE (Power Over Ethernet)/PD. Refer to Application Note AND8247.

Secondary Side Bias Supply for Isolated dc--dc Converters

Stand Alone Low Power dc--dc Converter

Low Power Bias Supply

Low Power Boost Converter

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SO--8

D SUFFIX

CASE 751

MARKING

DIAGRAMS

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb--Free Package

Micro8t

DM SUFFIX

CASE 846A

1030

AYWG

GND 2

CT3

VFB 4

COMP

VCC

VDRAIN

(Top View)

PIN CONNECTIONS

N1031

ALYW

(Note: Microdot may be in either location)

See detailed ordering and shipping information in the package

dimensions section on page 16 of this data sheet.

ORDERING INFORMATION

DFN--8

MN SUFFIX

CASE 488AF

NCP

1031

ALYW G

(Top View)

EP Flag

GND

VFB

COMP

VCC

VDRAIN

NCP1030, NCP1031

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Figure 1. NCP1030/31 Functional Block Diagram

Thermal

Shutdown

One Shot

Pulse

Reset

Dominant

Latch

7.5V/10V

10 V

6.5 V

2.5 V

LEB

Reset

Dominant

Latch

50 mV

2.5 V

Internal Bias

16 V

10 V

GND

VFB

COMP

Disable

3.0 V/3.5 V

PWM Latch

PWM Comparator

Error Amplifier

Current Limit

Comparator

VDRAIN

RSENSE

10 V

VCC

I2=3I

CTRamp

2kΩ

4.5 V

ISTART

FUNCTIONAL PIN DESCRIPTION

Pin Name Function Description

1GND Ground Ground reference pin for the circuit.

2 CTOscillator Frequency

Selection

An external capacitor connected to this pin sets the oscillator frequency up to 1 MHz.

The oscillator can be synchronized to a higher frequency by charging or discharging

CTto trip the internal 3.0 V/3.5 V comparator. If a fault condition exists, the power

switch is disabled and the frequency is reduced by a factor of 7.

3 VFB Feedback Input The regulated voltage is scaled down to 2.5 V by means of a resistor divider.

Regulation is achieved by comparing the scaled voltage to an internal 2.5 V reference.

4COMP Error Amplifier Compensation Requires external compensation network between COMP and VFB pins. This pin is

effectively grounded if faults are present.

5OV Line Overvoltage Shutdown Line voltage (Vin) is scaled down using an external resistor divider such that the OV

voltage reaches 2.5 V when line voltage reaches its maximum operating voltage.

6UV Line Undervoltage Shutdown Line voltage is scaled down using an external resistor divider such that the UV

voltage reaches 2.5 V when line voltage reaches its minimum operating voltage.

7 VCC Supply Voltage This pin is connected to an external capacitor for energy storage. During Turn--On, the

startup circuit sources current to charge the capacitor connected to this pin. When the

supply voltage reaches VCC(on), the startup circuit turns OFF and the power switch is

enabled if no faults are present. An external winding is used to supply power after

initial startup to reduce power dissipation. VCC should not exceed 16 V.

8 VDRAIN Power Switch and

Startup Circuits

This pin directly connects the Power Switch and Startup Circuits to one of the

transformer windings. The internal High Voltage Power Switch Circuit is connected

between this pin and ground. VDRAIN should not exceed 200 V.

NCP1030, NCP1031

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Figure 2. Pulse Width Modulation Timing Diagram

CTRamp

CTCharge

Signal

PWM

Comparator

Output

PWM Latch

Output

Power Switch

Circuit Gate Drive

Leading Edge

Blanking Output

COMP Voltage

Current Limit

Propagation Delay

Current Limit

Threshold

Normal PWM Operating Range Output Overload

Figure 3. Auxiliary Winding Operation with Output Overload Timing Diagram

VCC(on)

VCC(off)

VCC(reset)

0mA

ISTART

VDRAIN

VFB

Normal Operation

Power--up &

standby Operation

Output Overload

2.5 V

VUV

3.0 V

NCP1030, NCP1031

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MAXIMUM RATINGS

Rating Symbol Value Unit

Power Switch and Startup Circuits Voltage VDRAIN --0.3 to 200 V

Power Switch and Startup Circuits Input Current

-- NCP1030

-- NCP1031

IDRAIN 1.0

2.0

VCC Voltage Range VCC --0.3to16 V

All Other Inputs/Outputs Voltage Range VIO --0.3to10 V

VCC and All Other Inputs/Outputs Current IIO 100 mA

Operating Junction Temperature TJ--40 to 150 C

Storage Temperature Tstg --55 to 150 C

Power Dissipation (TJ=25C, 2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad)

DM Suffix, Plastic Package Case 846A

D Suffix, Plastic Package Case 751

MN Suffix, Plastic Package Case 488AF

0.582

0.893

1.453

Thermal Resistance, Junction to Air (2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad)

DM Suffix, Plastic Package Case 846A

D Suffix, Plastic Package Case 751

MN Suffix, Plastic Package Case 488AF

RθJA 172

112

C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

A. This device contains ESD protection circuitry and exceeds the following tests:

Pins 1--7: Human Body Model 2000V per MIL--STD--883, Method 3015.

Pins 1--7: Machine Model Method 200 V.

Pin 8 is connected to the High Voltage Startup and Power Switch Circuits and rated only to the maximum voltage rating of the part, or 200 V.

B. This device contains Latchup protection and exceeds ±100 mA per JEDEC Standard JESD78.

NCP1030, NCP1031

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DC ELECTRICAL CHARACTERISTICS (VDRAIN =48V,V

CC =12V,C

T= 560 pF, VUV =3V,V

OV =2V,V

FB =2.3V,

VCOMP =2.5V,T

J=--40C to 125C, typical values shown are for TJ=25C unless otherwise noted.) (Note 1)

Characteristics Symbol Min Typ Max Unit

STARTUP CONTROL

Startup Circuit Output Current (VFB =V

COMP)

NCP1030

TJ=25C

VCC =0V

VCC =V

CC(on) -- 0 . 2 V

TJ=--40C to 125C

VCC =0V

VCC =V

CC(on) -- 0 . 2 V

NCP1031

TJ=25C

VCC =0V

VCC =V

CC(on) -- 0 . 2 V

TJ=--40C to 125C

VCC =0V

VCC =V

CC(on) -- 0 . 2 V

ISTART

6.0

8.0

2.0

8.0

4.0

12.5

8.6

VCC Supply Monitor (VFB =2.7V)

Startup Threshold Voltage (VCC Increasing)

Minimum Operating VCC After Turn--on (VCC Increasing)

Hysteresis Voltage

VCC(on)

VCC(off)

VCC(hys)

9.6

7.0

10.2

7.6

2.6

10.6

8.0

Undervoltage Lockout Threshold Voltage, VCC Decreasing (VFB =V

COMP) VCC(reset) 6.0 6.6 7.0 V

Minimum Startup Voltage (Pin 8)

ISTART =0.5mA,V

CC =VCC(on) -- 0 . 2 V

VSTART(min) -- 16.8 18.5

ERROR AMPLIFIER

Reference Voltage (VCOMP =V

FB, Follower Mode)

TJ=25C

TJ=--40C to 125C

VREF 2.45

2.40

2.5

2.55

2.60

Line Regulation (VCC =8Vto16V,T

J=25C) REGLINE -- 1.0 5.0 mV

Input Bias Current (VFB =2.3V) IVFB -- 0.1 1.0 mA

COMP Source Current ISRC 80 110 140 mA

COMP Sink Current (VFB =2.7V) ISNK 200 550 900 mA

COMP Maximum Voltage (ISRC =0mA) VC(max) 4.5 -- -- V

COMP Minimum Voltage (ISNK =0mA, VFB =2.7V) VC(min) -- -- 1.0 V

Open Loop Voltage Gain AVOL -- 80 -- dB

Gain Bandwidth Product GBW -- 1.0 -- MHz

LINE UNDER/OVERVOLTAGE DETECTOR

Undervoltage Lockout (VFB =V

COMP)

Voltage Threshold (Vin Increasing)

Voltage Hysteresis

Input Bias Current

VUV

VUV(hys)

IUV

2.400

0.075

2.550

0.175

2.700

0.275

1.0

Overvoltage Lockout (VFB =V

COMP)

Voltage Threshold (Vin Increasing)

Voltage Hysteresis

Input Bias Current

VOV

VOV(hys)

IOV

2.400

0.075

2.550

0.175

2.700

0.275

1.0

1. Production testing for NCP1030DMR2 is performed at 25C only; limits at --40C and 125C are guaranteed by design.

NCP1030, NCP1031

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DC ELECTRICAL CHARACTERISTICS (VDRAIN =48V,V

CC =12V,C

T= 560 pF, VUV =3V,V

OV =2V,V

FB =2.3V,

VCOMP =2.5V,T

J=--40C to 125C, typical values shown are for TJ=25C unless otherwise noted.) (Note 2)

Characteristics Symbol Min Typ Max Unit

OSCILLATOR

Frequency (CT= 560 pF, Note 3)

TJ=25C

TJ=--40C to 125C

fOSC1 275

260

300

325

kHz

Frequency (CT= 100 pF) fOSC2 -- 800 -- kHz

Charge Current (VCT =3.25V) ICT(C) -- 215 -- mA

Discharge Current (VCT =3.25V) ICT(D) -- 645 -- mA

Oscillator Ramp

Peak

Valley

Vrpk

Vrvly

3.5

3.0

PWM COMPARATOR

Maximum Duty Cycle DCMAX 70 75 80 %

POWER SWITCH CIRCUIT

Power Switch Circuit On--State Resistance (ID= 100 mA)

NCP1030

TJ=25C

TJ= 125C

NCP1031

TJ=25C

TJ= 125C

RDS(on)

4.1

6.0

2.1

3.5

7.0

3.0

6.0

Power Switch Circuit and Startup Circuit Breakdown Voltage

(ID= 100 mA, TJ=25C)

V(BR)DS 200 -- --

Power Switch Circuit and Startup Circuit Off--State Leakage Current

(VDRAIN = 200 V, VUV =2.0V)

TJ=25C

TJ=--40to125C

IDS(off)

Switching Characteristics (VDS =48V,R

L= 100 Ω)

Rise Time

Fall Time

CURRENT LIMIT AND OVER TEMPERATURE PROTECTION

Current Limit Threshold (TJ=25C)

NCP1030 (di/dt = 0.5 A/ms)

NCP1031 (di/dt = 1.0 A/ms)

ILIM 350

700

515

1050

680

1360

Propagation Delay, Current Limit Threshold to Power Switch Circuit Output

(Leading Edge Blanking plus Current Limit Delay)

tPLH -- 100 --

Thermal Protection (Note 4)

Shutdown Threshold (TJIncreasing)

Hysteresis

TSHDN

THYS

150

C

TOTAL DEVICE

Supply Current After UV Turn--On

Power Switch Enabled

Power Switch Disabled

Non--Fault condition (VFB =2.7V)

Fault Condition (VFB =2.7V,V

UV =2.0V)

ICC1

ICC2

ICC3

2.0

3.0

1.5

0.65

4.0

2.0

1.2

2. Production testing for NCP1030DMR2 is performed at 25C only; limits at --40C and 125C are guaranteed by design.

3. Oscillator frequency can be externally synchronized to the maximum frequency of the device.

4. Guaranteed by design only.

NCP1030, NCP1031

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TYPICAL CHARACTERISTICS

VCC, SUPPLY VOLTAGE (V)

13.0

12.5

12.0

11.5

8.0

8.5

9.0

9.5

11.0

10.5

10.0

24 6810

ISTART

, STARTUP CURRENT (mA)

NCP1030

VDRAIN =48V

TJ=25C

Figure 4. NCP1030 Startup Current vs. Supply

Voltage

ISTART

, STARTUP CURRENT (mA)

NCP1030

VDRAIN =48V

--50 --25 0 25 50 150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. NCP1031 Startup Current vs. Supply

Voltage

75 100 125

VCC =0V

VCC =V

CC(on) -- 0 . 2 V

VDRAIN, DRAIN VOLTAGE (V)

25 50 75 100 200

ISTART

, STARTUP CURRENT (mA)

Figure 6. NCP1030 Startup Current vs.

Junction Temperature

125 150 175

TJ=25C

VCC =V

CC(on) -- 0 . 2 V

Figure 7. NCP1031 Startup Current vs.

Junction Temperature

Figure 8. NCP1030 Startup Current vs. Drain

Voltage

Figure 9. NCP1031 Startup Current vs. Drain

Voltage

TJ=--40C

TJ= 125C

VCC, SUPPLY VOLTAGE (V)

24 6810

ISTART

, STARTUP CURRENT (mA)

NCP1031

VDRAIN =48V

TJ=25C

ISTART

, STARTUP CURRENT (mA)

NCP1031

VDRAIN =48V

--50 --25 0 25 50 150

TJ, JUNCTION TEMPERATURE (C)

75 100 125

VCC =0V

VCC =V

CC(on) -- 0 . 2 V

VDRAIN, DRAIN VOLTAGE (V)

25 50 75 100 200

ISTART

, STARTUP CURRENT (mA)

125 150 175

TJ=25C

TJ=--40C

TJ= 125C

NCP1030 NCP1031

VCC =V

CC(on) -- 0 . 2 V

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TYPICAL CHARACTERISTICS

Figure 10. Supply Voltage Thresholds vs.

Junction Temperature

Figure 11. Undervoltage Lockout Threshold

vs. Junction Temperature

Figure 12. Minimum Startup Voltage vs.

Junction Temperature

11.0

10.5

10.0

9.5

6.0

6.5

7.0

7.5

9.0

8.5

8.0

VCC, SUPPLY VOLTAGE (V)

--50 --25 0 50 150

TJ, JUNCTION TEMPERATURE (C)

Figure 13. Reference Voltage vs. Junction

Temperature

75 100 12525

Startup Threshold

Minimum Operating Threshold

TJ, JUNCTION TEMPERATURE (C)

Figure 14. COMP Source Current vs. Junction

Temperature

Figure 15. COMP Sink Current vs. Junction

Temperature

-- 5 0 -- 2 5 0 2 5 5 0 1 5

75 100 125

6.80

6.75

6.70

6.65

6.30

6.35

6.40

6.45

6.60

6.55

6.50

VCC(reset), UNDERVOLTAGE LOCKOUT

THRESHOLD (V)

2.70

2.65

2.60

2.55

2.20

2.25

2.30

2.35

2.50

2.45

2.40

VREF

, REFERENCE VOLTAGE (V)

-- 2 5

TJ, JUNCTION TEMPERATURE (C)

--50 0 25 50 75 100 125 150

VCC =12V

20.0

19.5

19.0

18.5

15.0

15.5

16.0

16.5

18.0

17.5

17.0

VSTART(min), MINIMUM STARTUP VOLTAGE (V)

-- 2 5

TJ, JUNCTION TEMPERATURE (C)

--50 0 25 50 75 100 125 150

VCC =V

CC(on) -- 0 . 2 V

ISTART =0.5mA

VCC =12V

VCOMP =2.5V

VFB =2.3V

145

140

135

130

100

105

110

125

120

115

ISRC, COMP SOURCE CURRENT (mA)

-- 2 5

TJ, JUNCTION TEMPERATURE (C)

--50 0 25 50 75 100 125 150

840

790

740

690

390

440

490

640

590

540

ISNK, COMP SINK CURRENT (mA)

340

-- 2 5

TJ, JUNCTION TEMPERATURE (C)

--50 0 25 50 75 100 125 150

VCC =12V

VCOMP =2.5V

VFB =2.7V

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TYPICAL CHARACTERISTICS

Figure 16. Line Under/Overvoltage Thresholds

vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (C)

--50 --25 0 50 15075 100 12525

2.600

2.575

2.550

2.525

2.350

2.375

2.400

2.425

2.500

2.475

2.450

VUV/OV, LINE UNDER/OVERVOLTAGE THRESHOLDS (V)

200

190

180

170

120

130

160

150

140

VUV/OV(hys), UNDER/OVERVOLTAGE

HYSTERESIS (mV)

-- 2 5

TJ, JUNCTION TEMPERATURE (C)

--50 0 25 50 75 100 125 150

210

220

Figure 17. Line Under/Overvoltage Hysteresis

vs. Junction Temperature

Figure 18. Oscillator Frequency vs. Timing

Capacitor

Figure 19. Oscillator Frequency vs. Junction

Temperature

1000

900

800

700

100

200

300

600

500

400

fOSC, OSCILLATOR FREQUENCY (kHz)

, TIMING CAPACITOR (pF)

Figure 20. Maximum Duty Cycle vs. Junction

Temperature

0 200 400 600 800 1000

VCC =12V

TJ=25C

TJ, JUNCTION TEMPERATURE (C)

Figure 21. Power Switch Circuit On Resistance

vs. Junction Temperature

VCC =12V

1100

1000

900

800

100

200

400

700

600

500

fOSC, OSCILLATOR FREQUENCY (kHz)

--50 --25 0 25 15050 75 100 125

300

CT=47pF

CT= 220 pF

CT= 1000 pF

77.0

76.5

76.0

75.5

72.0

72.5

73.0

73.5

75.0

74.5

74.0

DCMAX, MAXIMUM DUTY CYCLE (%)

-- 5 0 -- 2 5 0 2 5 5 0 7 5

TJ, JUNCTION TEMPERATURE (C)

100 125 150

fOSC = 1000 kHz

fOSC = 200 kHz

VCC =12V

RDS(on), POWER SWITCH CIRCUIT

ON RESISTANCE (Ω)

-- 5 0 -- 2 5 0 2 5 5 0 7 5

TJ, JUNCTION TEMPERATURE (C)

100 125 150

VCC =12V

ID= 100 mA NCP1030

NCP1031

NCP1030, NCP1031

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TYPICAL CHARACTERISTICS

Figure 22. Power Switch Circuit Output

Capacitance vs. Drain Voltage

COUT

, OUTPUT CAPACITANCE (pF)

Figure 23. Power Switch Circuit and Startup

Circuit Leakage Current vs. Drain Voltage

1000

100

Figure 24. NCP1030 Current Limit Threshold

vs. Junction Temperature

0 40 80 120 160 200

VDRAIN, DRAIN VOLTAGE (V)

IDS(off), POWER SWITCH AND STARTUP

CIRCUITS LEAKAGE CURRENT (mA)

Figure 25. NCP1031 Current Limit Threshold

vs. Junction Temperature

0 50 100 150

VDRAIN, DRAIN VOLTAGE (V)

200 250 300

TJ=--40C

TJ=25C

TJ= 125C

VCC =12V

NCP1030

NCP1031

600

575

550

525

350

375

500

475

400

ILIM, CURRENT LIMIT THRESHOLD (mA)

TJ, JUNCTION TEMPERATURE (C)

--50 --25 0 25 50 75

TJ=25C

100 125 150

425

450

600

575

550

525

350

375

500

475

400

ILIM, CURRENT LIMIT THRESHOLD (mA)

CURRENT SLEW RATE (mA/mS)

375 400 425 450 475 500

425

450

Current Slew Rate = 500 mA/ms

Figure 26. NCP1030 Current Limit Threshold

vs. Current Slew Rate

Figure 27. NCP1031 Current Limit Threshold

vs. Current Slew Rate

1200

1150

1100

1050

700

750

1000

950

800

ILIM, CURRENT LIMIT THRESHOLD (mA)

TJ, JUNCTION TEMPERATURE (C)

--50 --25 0 25 50 75

TJ=25C

100 125 150

850

900

1200

1150

1100

1050

700

750

1000

950

800

ILIM, CURRENT LIMIT THRESHOLD (mA)

CURRENT SLEW RATE (mA/mS)

750 800 850 900 950 1000

850

900

Current Slew Rate = 1 A/ms

NCP1030

NCP1031

NCP1030, NCP1031

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TYPICAL CHARACTERISTICS

Figure 28. Operating Supply Current vs.

Supply Voltage

Figure 29. Supply Current vs. Junction

Temperature

4.1

3.9

3.3

2.5

3.1

2.7

ICC1, OPERATING SUPPLY CURRENT (mA)

VCC, SUPPLY VOLTAGE (V)

Figure 30. Operating Supply Current vs.

Oscillator Frequency

10 11 12 13 14 15 16

2.9

VDRAIN =48V

TJ=25C

CT= 560 pF

4.0

2.5

2.0

1.5

0.5

ICC, SUPPLY CURRENT (mA)

TJ, JUNCTION TEMPERATURE (C)

--50 --25 0 25 50 75 100

1.0

VCC =12V

CT= 560 pF

125 150

VUV =3.0V,V

FB =2.3V

VUV =3.0V,V

FB =2.7V

VUV =2.0V

3.0

3.7

3.5

ICC, POWER SUPPLY CURRENT (mA)

fOSC, OSCILLATOR FREQUENCY (kHz)

200 300 400 500 600 700 800

900 1000

TJ=25C

NCP1030

NCP1031

NCP1030, NCP1031

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Figure 31. Secondary Side Bias Supply Configuration

GND

COMP

Vin

VBIAS GND

SECONDARY

SIDE CONTROL

VCC

VDRAIN

VFB

Vout

NCP103x

Figure 32. Boost Circuit Configuration

GND

COMP

Vout

VCC

VDRAIN

VFB

Vin

NCP103x

VCC

NCP1030, NCP1031

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OPERATING DESCRIPTION

Introduction

The NCP1030 and NCP1031 are a family of miniature

monolithic voltage--mode switching regulators designed for

isolated and non--isolated bias supply applications. The

internal startup circuit and the MOSFET are rated at 200 V,

making them ideal for 48 V telecom and 42 V automotive

applications. In addition, the NCP103x family can operate

from an existing 12 V supply. This controller family is

optimized for operation up to 1 MHz.

The NCP103x family incorporates in a single IC all the

active power, control logic and protection circuitry required

to implement, with a minimum of external components,

several switching regulator applications, such as a

secondary side bias supply or a low power dc--dc converter.

The NCP1030 is available in the space saving Micro8t

package and is targeted for applications requiring up to 3 W.

The NCP1031 is targeted for applications up to 6 W and is

available in the SO--8 package.

The NCP103x includes an extensive set of features

including over temperature protection, cycle by cycle

current limit, individual line under and overvoltage

detection comparators with hysteresis, and regulator output

undervoltage lockout with hysteresis, providing full

protection during fault conditions. A description of each of

the functional blocks is given below, and the representative

block diagram is shown in Figure 2.

Startup Circuit and Undervoltage Lockout

The NCP103x contains an internal 200 V startup regulator

that eliminates the need for external startup components.

The startup regulator consists of a constant current source

that supplies current from the input line (Vin) to the capacitor

on the VCC pin (CCC). Once the VCC voltage reaches

approximately 10 V, the startup circuit is disabled and the

Power Switch Circuit is enabled if no faults are present.

During this self--bias mode, power to the NCP103x is

supplied by the VCC capacitor. The startup regulator turns

ON again once VCC reaches 7.5 V. This “7.5--10” mode of

operation is known as Dynamic Self Supply (DSS). The

NCP1030 and NCP1031 startup currents are 12 mA and 16

mA, respectively.

If VCC falls below 7.5 V, the device enters a re--start mode.

While in the re--start mode, the VCC capacitor is allowed to

discharge to 6.5 V while the Power Switch is enabled. Once

the 6.5 V threshold is reached, the Power Switch Circuit is

disabled and the startup regulator is enabled to charge the

VCC capacitor. The Power Switch is enabled again once the

VCC voltage reaches 10 V. Therefore, the external VCC

capacitor must be sized such that a voltage greater than 7.5

V is maintained on the VCC capacitor while the converter

output reaches regulation. Otherwise, the converter will

enter the re--start mode. Equation (1) provides a guideline

for the selection of the VCC capacitor for a forward

converter;

Forward:

(eq. 1)

CCC =cos-- 1 1−VOUT⋅NP

DC⋅Vin⋅NS×LOUTCOUT

⋅Ibias

2.6

where, Ibias is the bias current supplied by the VCC capacitor

including the IC bias current (ICC1) and any additional

current used to bias the feedback resistors (if used).

After initial startup, the VCC pin should be biased above

VCC(off) using an auxiliary winding. This will prevent the

startup regulator from turning ON and reduce power

dissipation. Also, the load should not be directly connected

to the VCC capacitor. Otherwise, the load may override the

startup circuit. Figure 33 shows the recommended

configuration for a non--isolated flyback converter.

Figure 33. Non--Isolated Bias Supply Configuration

GND

COMP

Vin

VCC

VDRAIN

VFB

NCP103x

Vout

The maximum voltage rating of the startup circuit is

200 V. Power dissipation should be observed to avoid

exceeding the maximum power dissipation of the package.

Error Amplifier

The internal error amplifier (EA) regulates the output

voltage of the bias supply. It compares a scaled output

voltage signal to an internal 2.5 V reference (VREF)

connected to its non--inverting input. The scaled signal is fed

into the feedback pin (VFB) which is the inverting input of the

error amplifier.

The output of the error amplifier is available for frequency

compensation and connection to the PWM comparator

through the COMP pin. To insure normal operation, the EA

compensation should be selected such that the EA frequency

response crosses 0 dB below 80 kHz.

The error amplifier input bias current is less than 1 mA

over the operating range. The output source and sink

currents are typically 110 mA and 550 mA, respectively.

Under load transient conditions, COMP may need to

move from the bottom to the top of the CTRamp. A large

current is required to complete the COMP swing if small

resistors or large capacitors are used to implement the

compensation network. In which case, the COMP swing will

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be limited by the EA sink current, typically 110 mA.

Optimum transient response is obtained if the compensation

components allow COMP to swing across its operating

range in 1 cycle.

Line Under and Overvoltage Detector

The NCP103x incorporates individual line undervoltage

(UV) and overvoltage (OV) shutdown circuits. The UV and

OV thresholds are 2.5 V. A fault is present if the UV is below

2.5 V or if the OV voltage is above 2.5 V. The UV/OV

detectors incorporate 175 mV hysteresis to prevent noise

from triggering the shutdown circuits.

The UV/OV circuits can be biased using an external

resistor divider from the input line as shown in Figure 34.

The UV/OV pins should be bypassed using a capacitor to

prevent triggering the UV or OV circuits during normal

switching operation.

Figure 34. UV/OV Resistor Divider

from the Input Line

Vin

VUV

VOV

The resistor divider must be sized to enable the controller

once Vin is within the required operating range. While a UV

or OV fault is present, switching is not allowed and the

COMP pin is effectively grounded.

Either of these comparators can be used for a different

function if UV or OV functions are not needed. For example,

the UV/OV detectors can be used to implement an enable or

disable function. If positive logic is used, the enable signal

is applied to the UV pin while the OV pin is grounded. If

negative logic is used, the disable signal is applied to the OV

pin while biasing the UV pin from VCC using a resistor

divider.

Oscillator

The oscillator is optimized for operation up to 1 MHz and

its frequency is set by the external timing capacitor (CT)

connected to the CTpin. The oscillator has two modes of

operation, free running and synchronized (sync). While in

free running mode, an internal current source sequentially

charges and discharges CTgenerating a voltage ramp

between 3.0 V and 3.5 V. Under normal operating

conditions, the charge (ICT(C)) and discharge (ICT(D))

currents are typically 215 mA and 645 mA, respectively. The

charge:discharge current ratio of 1:3 discharges CTin 25 %

of the total period. The Power Switch is disabled while CT

is discharging, guaranteeing a maximum duty cycle of 75 %

as shown in Figure 35.

25 %

Max

Duty Cycle

COMP

75%

Figure 35. Maximum Duty Cycle vs COMP

CTRamp

Power Switch

Enabled

CTCharge

Signal

Figure 18 shows the relationship between the operating

frequency and CT. If an UV fault is present, both ICT(C) and

ICT(D) are reduced by a factor of 7, thus reducing the

operating frequency by the same factor.

The oscillator can be synchronized to a higher frequency

by capacitively coupling a synchronization pulse into the CT

pin. In sync mode, the voltage on the CTpin needs to be

driven above 3.5 V to trigger the internal comparator and

complete the CTcharging period. However, pulsing the CT

pin before it reaches 3.5 V will reduce the p--p amplitude of

the CTRamp as shown in Figure 36.

Figure 36. External Frequency Synchronization

Waveforms

3.0 V

3.5 V

Sync Pulse 3.0 V/3.5

Comparator

Reset

Free Running

Mode Sync Mode

T1 (f1) T2 (f2)

T2 (f2)

Ramp CTVoltage

Range in Sync

The oscillator frequency should be set no more that 25%

below the target sync frequency to maintain an adequate

voltage range and provide good noise immunity. A possible

circuit to synchronize the oscillator is shown in Figure 37.

R1 R2

Figure 37. External Frequency Synchronization

Circuit.

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PWM Comparator and Latch

The Pulse Width Modulator (PWM) Comparator

compares the error amplifier output (COMP) to the CT

Ramp and generates a proportional duty cycle. The Power

Switch is enabled while the CTRamp is below COMP as

shown in Figure 35. Once the CTRamp reaches COMP, the

Power Switch is disabled. If COMP is at the bottom of the

CTRamp, the converter operates at minimum duty cycle.

While COMP increases, the duty cycle increases, until

COMP reaches the peak of the CTRamp, at which point the

controller operates at maximum duty cycle.

The CTCharge Signal is filtered through a One Shot Pulse

Generator to set the PWM Latch and enable switching at the

beginning of each period. Switching is allowed while the CT

Ramp is below COMP and a current limit fault is not present.

The PWM Latch and Comparator propagation delay is

typically 150 ns. If the system is designed to operate with a

minimum ON time less than 150 ns, the converter will skip

pulses. Skipping pulses is usually not a problem, unless

operating at a frequency close to the audible range. Skipping

pulses is more likely when operating at high frequencies

during high line and minimum load condition.

A series resistor is included for ESD protection between the

EA output and the COMP pin. Under normal operation, a 220

mV offset is observed between the CTRamp and the COMP

crossing points. This is not a problem as the series resistor

does not interact with the error amplifier transfer function.

Current Limit Comparator and Power Switch Circuit

The NCP103x monolithically integrates a 200 V Power

Switch Circuit with control logic circuitry. The Power

Switch Circuit is designed to directly drive the converter

transformer. The characteristics of the Power Switch Circuit

are well known. Therefore, the gate drive is tailored to

control switching transitions and help limit electromagnetic

interference (EMI). The Power Switch Circuit is capable of

switching 200 V.

The Power Switch Circuit incorporates SENSEFET

technology to monitor the drain current. A sense voltage is

generated by driving a sense element, RSENSE, with a current

proportional to the drain current. The sense voltage is

compared to an internal reference voltage on the

non--inverting input of the Current Limit Comparator. If the

sense voltage exceeds the reference level, the comparator

resets the PWM Latch and switching is terminated. The

NCP1030 and NCP1031 drain current limit thresholds are

0.5 A and 1.0 A, respectively.

Each time the Power Switch Circuit turns ON, a narrow

voltage spike appears across RSENSE. The spike is due to the

Power Switch Circuit gate to source capacitance,

transformer interwinding capacitance, and output rectifier

recovery time. This spike can cause a premature reset of the

PWM Latch. A proprietary active Leading Edge Blanking

(LEB) Circuit masks the current signal to prevent the

voltage spike from resetting the PWM Latch. The active

LEB masks the current signal until the Power Switch turn

ON transition is complete. The adaptive LEB period

provides better current limit control compared to a fixed

blanking period.

The current limit propagation delay time is typically

100 ns. This time is measured from when an overcurrent

fault appears at the Power Switch Circuit drain, to the start

of the turn--off transition. Propagation delay must be

factored in the transformer design to avoid transformer

saturation.

Thermal Shutdown

Internal Thermal Shutdown circuitry is provided to

protect the integrated circuit in the event the maximum

junction temperature is exceeded. When activated, typically

at 150_C, the Power Switch Circuit is disabled. Once the

junction temperature falls below 105_C, the NCP103x is

allowed to resume normal operation. This feature is

provided to prevent catastrophic failures from accidental

device overheating. It is not intended to be used as a

substitute for proper heatsinking.

Application Considerations

A 2 W bias supply for a 48 V telecom system was designed

using the NCP1030. The bias supply generates an isolated

12 V output. The circuit schematic is shown in Figure 38.

Application Note AND8119/D describes the design of the

bias supply.

Figure 38. 2 W Isolated Bias Supply Schematic

GND

COMP

35--76V

VCC

VDRAIN

VFB

MBRA160T3

2.2

4k99

1k30

10k

0.033

680p

0.01

2.2

1:2.78

45k3

34k

12V

NCP1030

0.022

100 p

MURA110T3

499

NCP1030, NCP1031

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ORDERING INFORMATION

Device Package Shipping†

NCP1030DMR2 Micro8 4000 / Tape & Reel

NCP1030DMR2G Micro8

(Pb--Free) 4000 / Tape & Reel

NCP1031DR2 SOIC--8 2500 / Tape & Reel

NCP1031DR2G SOIC--8

(Pb--Free) 2500 / Tape & Reel

NCP1031MNTXG DFN8

(Pb--Free) 4000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NCP1030, NCP1031

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PACKAGE DIMENSIONS

8 PIN DFN, 4x4

CASE 488AF--01

ISSUE C

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. DETAILS A AND B SHOW OPTIONAL

CONSTRUCTIONS FOR TERMINALS.

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.25 0.35

D4.00 BSC

D2 1.91 2.21

E4.00 BSC

E2 2.09 2.39

e0.80 BSC

K0 . 2 0 -- -- --

L0.30 0.50

C0.15

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

SEATING

PLANE

C0.08

C0.10

8X L

NOTE 3

0.10 C

0.05 C

PIN ONE

REFERENCE

*For additional information on our Pb--Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.63

2.21

2.39

0.80

PITCH

4.30

0.35

DETAIL A

OPTIONAL

CONSTRUCTIONS

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTIONS

L1 -- -- -- 0 . 1 5

DETAIL B

NOTE 4

DETAIL A

DIMENSIONS: MILLIMETERS

PACKAGE

OUTLINE

NCP1030, NCP1031

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PACKAGE DIMENSIONS

Micro8t

CASE 846A--02

ISSUE H

0.08 (0.003) A S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. 846A--01 OBSOLETE, NEW STANDARD 846A--02.

PIN 1 ID

8PL

0.038 (0.0015)

-- T -- SEATING

PLANE

A1 cL

*For additional information on our Pb--Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

8X 8X

6X mm

inches

SCALE 8:1

1.04

0.041

0.38

0.015

5.28

0.208

4.24

0.167

3.20

0.126

0.65

0.0256

DIM

MIN NOM MAX MIN

MILLIMETERS

-- -- -- -- 1 . 1 0 -- --

INCHES

A1 0.05 0.08 0.15 0.002

b0.25 0.33 0.40 0.010

c0.13 0.18 0.23 0.005

D2.90 3.00 3.10 0.114

E2.90 3.00 3.10 0.114

e0.65 BSC

L0.40 0.55 0.70 0.016

-- -- 0 . 0 4 3

0.003 0.006

0.013 0.016

0.007 0.009

0.118 0.122

0.026 BSC

0.021 0.028

NOM MAX

4.75 4.90 5.05 0.187 0.193 0.199

NCP1030, NCP1031

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PACKAGE DIMENSIONS

SOIC--8 NB

CASE 751--07

ISSUE AJ

SEATING

PLANE

X45

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751--01 THRU 751--06 ARE OBSOLETE. NEW

STANDARD IS 751--07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0808

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

-- X --

-- Y --

0.25 (0.010)

-- Z --

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

mm

inches

SCALE 6:1

*For additional information on our Pb--Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application,Buyer shall indemnify and hold SCILLC and itsofficers,employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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Phone: 81--3--5773--3850

NCP1030/D

Micro8 is a trademark of International Rectifier.

SENSEFET is a registered trademark of Semiconductor Components Industries, LLC.

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