M29W800DT90N1 - STMicroelectronics

1/41April 2004

M29W800DT

M29W800DB

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

■SUPPLY VOLTAGE

–V

CC = 2.7V to 3.6V for Program, Erase

and Read

■ACCESS TIME: 70, 90ns

■PROGRAMMING TIME

– 10µs per Byte/Word typical

■19 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location)

– 2 Parameter and 16 Main Blocks

■PROGRAM/ERASE CONTROLLER

– Embedded Byte/Word Program

algorithms

■ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Susp e nd

■UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■TEMPORARY BLOCK UNPROTECTION

MODE

■COMMON FLASH INTERFACE

– 64 bit Security Code

■LOW POWER CONSUMPTION

– Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ELECTRONIC SIGNATURE

– Manufactu rer Code : 0020h

– Top Device Code M29W800DT: 22D7h

– Bottom Device Code M29W800DB:

225Bh

Figure 1. Packages

TSOP48 (N)

12 x 20mm

TFBGA48 (ZA)

6 x 9 mm

FBGA

SO44 (M)

TFBGA48 (ZE)

6 x 8mm

FBGA

M29W800DT, M29W800DB

2/41

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 5. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write En abl e (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Special Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 2. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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M29W800DT, M29W800DB

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Commands, 8-b it mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 14

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 13.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 15.Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16.SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline . . . . . . . . 24

Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data 24

Figure 17.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline. . . . . . . . . 25

Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 25

Figure 18.TFBGA48 6x9mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline. . . . 26

M29W800DT, M29W800DB

4/41

Table 18. TFBGA48 6x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data. . 26

Figure 19.TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline. . . . 27

Table 19. TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data. . 27

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. Top Boot Block Addresses, M29W800DT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 22. Bottom Boot Block Addresses, M29W800DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 23. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 24. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 25. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 26. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 27. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 28. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 29. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 20.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 22.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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M29W800DT, M29W800DB

SUMMARY D ESCRIPTION

The M29W800D is a 8 Mbit (1Mb x8 or 512Kb x16)

non-volatile memory that can be read, erased and

reprogrammed. These operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode where it can be read in the same way

as a ROM or EPROM.

The memory is divided into blocks that can be

erased independen tly s o it is po ss i ble to p re se rve

valid data while old data is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. Prog ram and Er ase comma nds are writ-

ten to the C ommand Interface o f the memo ry. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

The blocks in the memory are asymmet rically ar-

ranged, see Figures 6 and 7, Block Addresses.

The first or la st 64 Kbytes have been divided into

four additional blocks. The 16 Kbyte Boot Block

can be used for small initialization code to start the

microprocessor, the two 8 Kbyte Parameter

Blocks can be used for parameter storage and the

remaining 32K is a small Main Block where the ap-

plication may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in SO44, TSOP48 (12 x

20mm), TFBGA48 6 x 9mm (0.8mm pitch) and

TFBGA4 8 6 x 8mm (0.8mm pit ch) packages. T he

memory is sup plied with all the bits eras ed (set to

’1’).

Figure 2. Logic Diagram Table 1. Signal Names

AI05470B

A0-A18

DQ0-DQ14

VCC

M29W800DT

M29W800DB

VSS

DQ15A–1

BYTE

A0-A18 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/B lo ck Tempora ry Unpr ote ct

RB Ready/Busy Output

(not available on SO44 package)

BYTE Byte/Word Organization Select

VCC Supply Voltage

VSS Ground

NC Not Conn ect ed Inter na lly

M29W800DT, M29W800DB

6/41

Figure 3. SO Connections Figure 4. TSOP Connections

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A–1

DQ5DQ2

DQ3 VCC

DQ11 DQ4

DQ14

AI05462b

M29W800DT

M29W800DB

2322

17DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10 21 DQ12

A17 A8

A18

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI05461

M29W800DT

M29W800DB

24 25

DQ8

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

7/41

M29W800DT, M29W800DB

Figure 5. TFBGA Connections (Top view through package)

AI00656

4321

DQ15

A–1

DQ10DQ8E

DQ13DQ11

DQ9

VSS

DQ6DQ1VSS

DQ14

A12

NCA17

A14A10NCA18A6A2

RP A8

DQ4

DQ3

VCC

DQ12

BYTE

A15A11NCA1

A16DQ7DQ5DQ2A0

DQ0

RB W A13

M29W800DT, M29W800DB

8/41

Figure 6. Block Addresses (x8)

Note: Also see Appendix A, Tables 21 and 22 for a fu ll listing of the Block Addresses.

AI05463

16 KByte

FFFFFh

FC000h

64 KByte

1FFFFh

10000h

64 KByte

0FFFFh

00000h

M29W800DT

Top Boot Block Addresses (x8)

32 KByte

F7FFFh

F0000h

64 KByte

E0000h

EFFFFh

Total of 15

64 KByte Blocks

16 KByte

FFFFFh

F0000h 64 KByte

64 KByte

03FFFh

00000h

M29W800DB

Bottom Boot Block Addresses (x8)

32 KByte

EFFFFh

1FFFFh 64 KByte

E0000h

10000h

Total of 15

64 KByte Blocks

0FFFFh

08000h

8 KByte

FBFFFh

FA000h

F9FFFh

F8000h

8 KByte

07FFFh

06000h

05FFFh

04000h

9/41

M29W800DT, M29W800DB

Figure 7. Block Addresses (x16)

Note: Also see Appendix A, Tables 21 and 22 for a fu ll listing of the Block Addresses.

AI05464

8 KWord

7FFFFh

7E000h

32 KWord

0FFFFh

08000h

32 KWord

07FFFh

00000h

M29W800DT

Top Boot Block Addresses (x16)

16 KWord

7BFFFh

78000h

32 KWord

70000h

77FFFh

Total of 15

32 KWord Blocks

8 KWord

7FFFFh

78000h 32 KWord

32 KWord

01FFFh

00000h

M29W800DB

Bottom Boot Block Addresses (x16)

16 KWord

77FFFh

0FFFFh 32 KWord

70000h

08000h

Total of 15

32 KWord Blocks

07FFFh

04000h

4 KWord

7DFFFh

7D000h

7CFFFh

7C000h

4 KWord

03FFFh

03000h

02FFFh

02000h

M29W800DT, M29W800DB

10/41

SIGNAL DESCRIPTIONS

See Figu re 2, L ogi c Di ag ra m, an d Tab le 1 , Si gn al

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A18). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Data Inputs/Outputs (DQ8-DQ14). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation when BYTE

is High, VIH. When BYTE is Low, VIL, these pins

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bits. Wh en readin g the Statu s Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A-

1). When BYTE is High , VIH, this pin beh aves as

a Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the Word

on the other addresses, DQ15A–1 High will select

the MSB. Throughout the text consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to inc lude this pin when BYT E is Low exc ept

when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Writ e En a bl e, W , controls

the Bus Write operation of the memory’s Com-

mand Interface.

Reset/Block Temporary Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

us ed t o ap p ly a Ha r d wa r e R es et t o t he m e mo r y or

to tempora rily un prote ct a ll Bl oc k s that h av e be en

protected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High , VIH, the memory will be ready for Bu s

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/Busy

Output section, Table 15 and Figure 15, Reset/

Tem porary Unprotect AC Characteristics for more

details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

operation. During Program or Erase operations

Ready/Busy is Low, VOL. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode

and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes hi gh -impe dance. S ee Tabl e 15 an d F igur e

15, Reset/Temporary Unprotect AC Characteris-

tics.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch between the 8-bit and 16-bit Bus modes of

the memory. When Byte/Word Organization Se-

lect is Low, VIL, the memory is in 8-bit mode, when

it is High, VIH, the memory is in 16-bit mode.

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the VCC Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, ICC3.

Vss Ground. The VSS Ground is the reference

for all voltage measurements.

11/41

M29W800DT, M29W800DB

BUS OPERATIONS

There are five standard bus operations that control

the device. Thes e are Bus Read, Bus Writ e, Out -

put Disable, Standby and Automatic Standby. See

Tables 2 and 3, Bus Operations, for a summary.

Typicall y gl itc he s of less than 5ns on C hip Enab le

or Write Enable are ignored by the memory and do

not affect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, ap plyi ng a Low signal , V IL, to C h ip E nab le

and Output Enable and keeping Write Enable

High, VIH. The Data Inputs /Outp uts wil l outpu t the

value, see Figure 12, Read Mode AC Waveforms,

and Table 12, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inpu ts/Ou tputs are l atched by the Com -

mand Interfa ce on the rising ed ge of Chip Enab le

or Write Enable, whichever occurs first. Output En-

able must rema in High , VIH, duri ng the whol e Bu s

Write operation. See Figures 13 and 14, Write AC

Waveforms, and Tables 13 and 14, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, ICC2, Chip Enable should

be held within VCC ± 0.2V. For the Standby current

level see Table 11, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC3, for Program or Erase operations un-

til the operation completes.

Automatic Standby. If CMOS levels (VCC ± 0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, ICC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operations. Additional bus opera-

tions can be performed to read the Electronic Sig-

nature and also to apply and remove Block

Protection. These bus operations are intended for

use by programming equipment an d are not u su-

ally used in applications. They require VID to be

applied to some pins.

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These cod es can b e read b y apply ing the s ignals

listed in Tables 2 and 3, Bus Operations.

Block Protection and Blocks Unprotection.

Each block can be separately protected against

accidental Program or Erase. Protected blocks

can be unprotected to allow data to be changed.

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. Blo ck P ro tect a nd Chi p Un pr otect operation s

are described in Appendix C.

Table 2. Bus Operations, BYTE = VIL

Note: X = VIL or VIH.

Operation E G W Add res s Inp uts

DQ15 A– 1, A0 -A1 8 Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL VIH Cell Addre ss Hi-Z Data Outpu t

Bus Write VIL VIH VIL Command Address Hi-Z Data In put

Output Dis ab le X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH Hi-Z 20h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,

Others VIL or VIH Hi-Z D7h (M29W800DT)

5Bh (M29W800DB)

M29W800DT, M29W800DB

12/41

Table 3. Bus Operations, BYTE = VIH

Note: X = VIL or VIH.

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the memory is in 16-bit or 8-

bit mode. S ee either Table 4, or 5, depending on

the configuration that is being used, for a summary

of the commands.

Read/Reset Command. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM, unless other-

wise stated. It also resets the error s in the Status

can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mod e. On ce th e progr am or erase oper ation

has started the Read/Reset command is no longer

accepted. The Read/Reset command will not

abort an Erase operation when issued while in

Erase Suspend.

Auto Select Command. The Auto Select com-

mand is u sed to read the M anufac turer Co de, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until a Read/Reset

command is issued. Read CFI Query and Read/

Reset commands are accepted in Auto Select

mode, all other co mma nds are ignor ed.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A0 = VIL and A1 = VIL. The other address bits

may be set to either VIL or VIH. The Manufacturer

Code for STMicroelectronics is 0020h.

The Device Code ca n be read using a Bus Read

operation with A0 = VIH and A1 = VIL. The other

address bits may be set to either VIL or VIH. The

Device Code for the M29W800DT is 22D7h and

for the M29W800DB is 225Bh.

The Block Protection Status of each block can be

read using a Bus Read operation with A0 = VIL,

A1 = VIH, and A12-A18 specifying the address of

the block. The other address bits may be set to ei-

ther VIL or VIH. If the addressed block is protect-

ed then 01h is output on Data Inputs/Outputs

DQ0-DQ7, otherwise 0 0h is output.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data in the internal

state machine and starts the Program/Erase Con-

troller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the p rogr am operation the me mory will ig-

nore all com mands . It is no t possib le to iss ue any

command to abort or pause the operation. Typical

program times are given in Table 6. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

Operation E G W Add res s Inp uts

A0-A18 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Addre ss Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Dis ab le X VIH VIH XHi-Z

Standby VIH XXX Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,

Others VIL or VIH 22D7h (M29W800DT)

225Bh (M29W800DB)

13/41

M29W800DT, M29W800DB

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

Note that the Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program command to program the memo-

ry. When the access time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass command.

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

Unlock Bypass Program Command. The Un-

lock Bypass Program command can be used to

program one address in memory at a time. The

command requires two Bus Write operations, the

final wr ite op erati on lat ches the addr ess and d ata

in the internal state machine and starts the Pro-

gram/Erase Controller.

The Program operation using the Unlock Bypass

Program command behaves identically to the Pro-

gram operation using the Program command. A

protected block cannot be pr og rammed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

comma nd, which leaves the de vice in Unloc k By-

pass Mode. See the Program command for details

on the behavior.

Unlock Bypass Reset Command. The Unlock

Bypass Reset co mmand ca n be use d to retu rn to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlock Bypass Reset command. Read/Reset

command does not exit from Unlock Bypass

Mode.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

pears to start but will terminate within about 100µs,

leaving the da ta unc hanged . No err or con dition is

given when protected blocks are ignored.

During the erase operation the memory will ignore

all commands. It is not possible to issue any com-

mand to abort the operation. Typical chip erase

times are given in Table 6. All Bus Read opera-

tions during the Chip Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the C hip Erase o per at ion has co m ple ted the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Write operation using the address of the

additiona l blo ck . The Bl oc k Er ase operation st ar ts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer restarts when an additional block is selected.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register for

details on how to identify if the Program/Erase

Controller has started the Block Erase operation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blo cks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, leaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Bl ock Er ase o per at ion the memory wil l

ignore all commands except the Erase Suspend

command. Typical block erase times are given in

Table 6. All Bus Read operations during the Block

Erase operation will output the Status Register on

the Data Inputs/Outputs. See the section on the

Status Register for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selected blocks to ’1’. All previous

data in the selected blocks is lost.

M29W800DT, M29W800DB

14/41

Erase Susp e nd Com m and . The Eras e S u sp end

Command may be used to tempor arily suspend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

The Progra m/Erase Controlle r will suspen d with in

the Erase Suspend Latency Time (refer to Table 6

for value) of the Eras e Suspend Com mand being

issued. Once the Program/Erase Controller has

stopped the memory will be set to Read mode and

the Erase will be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase i s su spended i mme di atel y and wil l sta rt im -

mediately when the Erase Resume Command is

issued. It is not possible to select any further

blocks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these b locks. I f any attempt is mad e to

program in a protected bl ock or in the s uspended

block then the Program command is ignored and

the data remains unchanged. The Status Register

is not r ead and no error condit ion is given. Read -

ing from blocks that are being erased will output

the Status Register.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass comman ds during

an Erase Suspend. The Read/Reset command

must be issued to return the device to Read Array

mode before the Resume command will be ac-

cepted.

Erase Resume Command. The Erase Resume

command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase

can be suspended and resumed more than once.

Read CFI Query Command. The Read CFI

Query Command is used to read data from the

Com mon Fl ash Inte rface (CFI ) Memo ry Are a. Th is

comma nd is val id when the devi ce is in the Re ad

Array mode, or when the device is in Autoselected

mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subs equent Bus Read operatio ns read fr om

the Common Flash Interface Memory Area.

The Read/Reset command must b e issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Autoselected mode). A second Read/

Reset com mand wo uld be needed if the d evice i s

to be put in the Read Array mode from Autoselect-

ed mode.

See Appendix B, Tables 23, 24, 25, 26, 27 and for

details on the information contained in the Com-

mon Flash Interface (CFI) memory area.

Block Protect and

Chip Unprotect Commands.

Each block can be separately protected against

acciden tal Progr am or Eras e. The wh ole chi p can

be unprote cte d to a llow th e da ta inside the blocks

to be changed.

Block Protect and Chip Unprotect operations are

described in Appendix C.

15/41

M29W800DT, M29W800DB

Table 4. Commands, 16-bit mode, BYTE = VIH

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Bloc k.

All values in the table are in hexadec imal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3555 AA2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 55 98

M29W800DT, M29W800DB

16/41

Table 5. Commands, 8-bit mode, BYTE = VIL

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Bloc k.

All values in the table are in hexadec imal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

Note: 1. Typical values meas ured at room temperature and nominal voltages.

2. Sam pl e d , but not 100 % tes t ed .

3. Maximum value measu r ed at worst case condit i ons for both temperature and VCC after 100,00 program/eras e cycles.

4. Maximum value measu r ed at worst case condit i ons for both temperature and VCC.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass

Program 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 AA 98

Parameter Min Typ (1, 2) Max(2) Unit

Chip Erase 12 60(3) s

Block Erase (64 Kbytes) 0.8 6(4) s

Erase Suspend Latency Time 15 25(3) µs

Program (Byte or Word) 10 200(3) µs

Chip Prog ram (Byte by Byte) 12 60(3) s

Chip Prog ram (Word by Word) 6 30(4) s

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years

17/41

M29W800DT, M29W800DB

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is accessed.

The bits in the S t atu s R egi st er ar e s umm ariz ed in

Table 7, Status Register Bits.

Data Polling Bit (DQ7). The Data P olling B it can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. Afte r succe ssfu l com pleti on o f th e Era se op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Rea d operation within a

block being erased. The Data Polling Bit will

change from a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 8, Data Polling Flowchart, gives an exam -

ple of how to use the Dat a Polling Bit. A Va li d Ad -

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Prog ram a nd Eras e oper ations the Togg le

Bit change s from ’0’ to ’1’ to ’ 0’, etc. , with suc ces-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

If any attemp t is mad e to e ra se a protec te d bl oc k,

the operati on is aborted, n o error is signal led and

DQ6 toggles for approximately 100µs. If any at-

tempt is made to program a protected block or a

suspende d block, the opera tion is ab orted, no er -

ror is signalled and DQ6 toggles for approximately

1µs.

Figure 9, Data Toggl e Flowchart, gives an ex am-

ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Res et comm and mus t be issu ed

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dress w il l show the bi t is s ti ll ‘0 ’. On e of the Er as e

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’

Erase Ti m er B it (D Q3). The Erase T imer B it can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is s et to ’0’ a nd additiona l block s to be eras ed

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase con troller d uring Erase o perations. T he Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Rea d operations from addresse s

within the bl ocks being eras ed. A protected bl ock

is treated the same as a block not being erased.

Once the operation completes the memory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks be ing erased . Bus Read ope rations to ad -

dresses wi thi n b lock s not b eing e ra se d will out put

the memory cell data as if in Read mode.

After an E r ase o peration th at ca us es th e Err or Bit

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. Th e Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

M29W800DT, M29W800DB

18/41

Table 7. Status Register Bits

Note: Unspecified data bits should be ignored.

Figure 8. Data Polling Flowchart Figure 9. Data Toggle Flowchart

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 – – 0

Program During Erase

Suspend Any Address DQ7 Toggle 0 – – 0

Program Error Any Address DQ7 Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Blo ck Addr ess 0 To gg le 1 1 Toggle 0

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI03598

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI01370C

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

19/41

M29W800DT, M29W800DB

MAXIMUM RATING

Stressing the dev ice above the ratin g lis ted in the

Absolute Maximum Ratin gs table ma y cause pe r-

manent damage to the device. Ex posur e to Ab so -

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of th e device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during tran sitions.

2. Maximum voltage may overshoot to VCC +2V durin g transiti on and for less than 20ns during transitions.

Symbol Parameter Min Max Unit

TBIAS Temperature Under Bias –50 125 °C

TSTG Storage Temperature –65 150 °C

VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V

VCC Supply Voltage –0.6 4 V

VID Identification Voltage –0.6 13.5 V

M29W800DT, M29W800DB

20/41

DC AND AC PARA METERS

This section summarizes the operating measure-

ment condi tions, an d the DC and AC characteri s-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 9, Operating and

AC Measurement Conditions. Designers should

check that the operating conditions in their circuit

match the operating conditions when relying on

the quoted parameters.

Table 9. Operating and AC Measurement Conditions

Figure 10. AC Measurement I/O Waveform Figure 11. AC Measurement Load Circuit

Table 10. Device Capacitance

Note: Sampled only, no t 100% tested .

Parameter

M29W800D

Unit70 90

Min Max Min Max

VCC Supply Voltage 2.7 3.6 2.7 3.6 V

Ambient Operating Temperature (range 6) –40 85 –40 85 °C

Ambient Operating Temperature (range 1) 0 70 0 70

Load Capacitance (CL)30 100 pF

Input Rise and Fall Times 10 10 ns

Input Pulse Voltages 0 to VCC 0 to VCC V

Input and Output Timing Ref. Voltages VCC/2 VCC/2 V

AI04498

VCC

VCC/2

AI04499

CL includes JIG capacitance

DEVICE

UNDER

TEST

25kΩ

VCC

25kΩ

VCC

0.1µF

Symb ol Parame te r Te st Co nd itio n Min Max Uni t

CIN Input Capacitance VIN = 0V 6pF

COUT Output Capacitance VOUT = 0V 12 pF

21/41

M29W800DT, M29W800DB

Table 11. DC Characteristics

Note: 1. Sampled only, not 100% test ed.

Figure 12. Read Mode AC Waveforms

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Le ak age Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Cu rre nt (Re ad ) E = VIL, G = VIH,

f = 6MHz 10 mA

ICC2 Supply Cu rre nt (Stand by) E = VCC ±0.2V,

RP = VCC ±0.2V 100 µA

ICC3 (1) Su pp ly Cu rre nt (Pr og ram /E ra se) Program/Erase

Control ler ac tive 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7VCC VCC +0.3 V

VOL Output Lo w Voltage IOL = 1.8mA 0.45 V

VOH Output Hig h Voltage IOH = –100µAVCC –0. 4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO Prog ram /E ra se Lo cko ut Supp ly

Voltage 1.8 2.3 V

AI05448

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

M29W800DT, M29W800DB

22/41

Table 12. Read AC Characteristics

Note: 1. Sampled only, not 100% test ed.

Symbol Alt Parameter Test Condition M29W800D Unit

70 90

tAVAV tRC Address Valid to Next Address Valid E = VIL,

G = VIL Min 70 90 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max 70 90 ns

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 90 ns

tGLQX (1) tOLZ Output Enable Low to Output

Transition E = VIL Min 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 35 ns

tEHQZ (1) tHZ Chip Enab le Hig h to Ou tpu t Hi-Z G = VIL Max 25 30 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 30 ns

tEHQX

tGHQX

tAXQX tOH Chip Enable, Output Enable or

Address Transition to Output Transition Min 0 0 ns

tELBL

tELBH tELFL

tELFH Chip Enab le to BY TE Low or High Max 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns

23/41

M29W800DT, M29W800DB

Figure 13. Write AC Waveforms, Write Enable Controlled

Table 13. Write AC Characteristics, Write Enable Controlled

Note: 1. Sampled only, not 100% test ed.

Symbol Alt Parameter M29W800D Unit

70 90

tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 50 ns

tDVWH tDS Input V alid to Write Enable High Min 45 50 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 45 50 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

AI05449

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

M29W800DT, M29W800DB

24/41

Figure 14. Write AC Waveforms, Chip Enable Controlled

Table 14. Write AC Characteristics, Chip Enable Controlled

Note: 1. Sampled only, not 100% test ed.

Symbol Alt Parameter M29W800D Unit

70 90

tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns

tWLEL tWS Write Enable Low to Ch ip En ab le Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 50 ns

tDVEH tDS Input V alid to Chip Enable High Min 45 50 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 45 50 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

AI05450

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

25/41

M29W800DT, M29W800DB

Figure 15. Reset/Block Temporary Unprotect AC Waveforms

Table 15. Reset/Block Temporary Unprotect AC Characteristics

Note: 1. Sampled only, not 100% test ed.

Symbol Alt Parameter M29W800D Unit

70 90

tPHWL (1)

tPHEL

tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 0 0 ns

tPLPX tRP RP Pulse Width Min 50 0 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs

tPHPHH (1) tVIDR RP Ris e Time to VID Min 500 500 ns

AI06870

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

M29W800DT, M29W800DB

26/41

PACKAGE MECHANICAL

Figure 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline

Note: Drawing is not to scale.

Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.80 0.1102

A1 0.10 0.0039

A2 2.30 2.20 2.40 0.0906 0.0866 0.0945

b 0.40 0.35 0.50 0.0157 0.0138 0.0197

C 0.15 0.10 0.20 0.0059 0.0039 0.0079

CP 0.08 0.0030

D 28.20 28.00 28.40 1.1102 1.1024 1.1181

E 13.30 13.20 13.50 0.5236 0.5197 0.5315

EH 16.00 15.75 16.25 0.6299 0.6201 0.6398

e 1.27 – – 0.0500 – –

L 0.80 0.0315

a8 8

N44 44

SO-d

LA1 α

eCP

27/41

M29W800DT, M29W800DB

Figure 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

Note: Drawing is not to scale.

Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.080 0.0031

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

a305305

TSOP-G

DIE

LA1 α

M29W800DT, M29W800DB

28/41

Figure 18. TFBGA48 6x9mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline

Note: Drawing is not to scale.

Table 18. TFBGA48 6x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.200 0.0079

A2 1.000 0.0394

b 0.400 0.350 0.450 0.0157 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 9.000 8.900 9.100 0.3543 0.3504 0.3583

e 0.800 – – 0.0315 – –

E1 5.600 – – 0.2205 – –

FD 1.000 – – 0.0394 – –

FE 1.700 – – 0.0669 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

E1E

ebA2

BGA-Z00

ddd

FE SD

BALL "A1"

29/41

M29W800DT, M29W800DB

Figure 19. TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline

Note: Drawing is not to scale.

Table 19. TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.260 0.0102

A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 8.000 7.900 8.100 0.3150 0.3110 0.3189

E1 5.600 – – 0.2205 – –

e 0.800 – – 0.0315 – –

FD 1.000 – – 0.0394 – –

FE 1.200 – – 0.0472 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

E1E

BGA-Z32

ddd

FE SD

BALL "A1"

M29W800DT, M29W800DB

30/41

PART NUMBERING

Table 20. Ordering Information Scheme

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact your nearest ST Sales Office.

Example: M29W800DB 90 N 6 T

Device Type

M29

Operatin g Voltage

W = VCC = 2.7 to 3.6V

Device Function

800D = 8 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

90 = 90 ns

Package

M = SO44

N = TSOP48: 12 x 20 mm

ZA = TFBGA48: 6x9mm, 0.80mm pitch

ZE = TFBGA48: 6x8mm, 0.80mm pitch

Temperature Range

6 = –40 to 85 °C

1 = 0 to 70 °C

Option

T = Tape & Reel Packing

E = Lead-free Package, Standard Packing

F = Lead-free Package, Tape & Reel Packing

31/41

M29W800DT, M29W800DB

APPENDIX A. BLOCK ADDRESS TABLE

Table 21. Top Boot Block Addresses,

M29W800DT Table 22. Bottom Boot Block Addresses,

M29W800DB

#Size

(Kbytes) Address Range

(x8) Address Range

(x16)

18 16 FC000h-FFFFFh 7E000h-7FFFFh

17 8 FA000h-FBFFFh 7D000h-7DFFFh

16 8 F8000h-F9FFFh 7C000h-7CFFFh

15 32 F0000h-F7FFFh 78000h-7BFFFh

14 64 E0000h-EFFFFh 70000h-77FFFh

13 64 D0000h-DFFFFh 68000h-6FFFFh

12 64 C0000h-CFFFFh 60000h-67FFFh

11 64 B0000h-BFFFFh 58000h-5FFFFh

10 64 A0000h-AFFFFh 50000h-57FFFh

9 64 90000h-9FFFFh 48000h-4FFFFh

8 64 80000h-8FFFFh 40000h-47FFFh

7 64 70000h-7FFFFh 38000h-3FFFFh

6 64 60000h-6FFFFh 30000h-37FFFh

5 64 50000h-5FFFFh 28000h-2FFFFh

4 64 40000h-4FFFFh 20000h-27FFFh

3 64 30000h-3FFFFh 18000h-1FFFFh

2 64 20000h-2FFFFh 10000h-17FFFh

1 64 10000h-1FFFFh 08000h-0FFFFh

0 64 00000h-0FFFFh 00000h-07FFFh

#Size

(Kbytes) Address Range

(x8) Address Range

(x16)

18 64 F0000h-FFFFFh 78000h-7FFFFh

17 64 E0000h-EFFFFh 70000h-77FFFh

16 64 D0000h-DFFFFh 68000h-6FFFFh

15 64 C0000h-CFFFFh 60000h-67FFFh

14 64 B0000h-BFFFFh 58000h-5FFFFh

13 64 A0000h-AFFFFh 50000h-57FFFh

12 64 90000h-9FFFFh 48000h-4FFFFh

11 64 80000h-8FFFFh 40000h-47FFFh

10 64 70000h-7FFFFh 38000h-3FFFFh

9 64 60000h-6FFFFh 30000h-37FFFh

8 64 50000h-5FFFFh 28000h-2FFFFh

7 64 40000h-4FFFFh 20000h-27FFFh

6 64 30000h-3FFFFh 18000h-1FFFFh

5 64 20000h-2FFFFh 10000h-17FFFh

4 64 10000h-1FFFFh 08000h-0FFFFh

3 32 08000h-0FFFFh 04000h-07FFFh

2 8 06000h-07FFFh 03000h-03FFFh

1 8 04000h-05FFFh 02000h-02FFFh

0 16 00000h-03FFFh 00000h-01FFFh

M29W800DT, M29W800DB

32/41

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system so ftware to quer y the device to determine

various electrical and timing parameters, density

informati on and functions su pported by the mem-

ory. The system can interface easily with the de-

vice, en abl ing the software to upgrade itself wh en

necessary.

When the CF I Query Command is issued the de -

vice enters CFI Query mode and the data structure

is read from the memory. Tables 23, 24, 25, 26, 27

and 27 show the addresses used to retrieve the

data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table , Security Code area). This area

can be accessed only in Read mode by the final

user. It is impo ssible to chang e the sec urity num -

ber after it has been written by ST. Issue a Read

command to return to Read mode.

Table 23. Query Structure Overview

Note: Query data are alway s presented on the lowes t order data outputs.

Tab le 24. CFI Query Identification String

Note: Query data are alway s presented on the lowest order data outputs (DQ7-DQ0 ) only. DQ8-DQ15 are ‘0’.

Address Sub-section Name Description

x16 x8

10h 20h CFI Query Identification String Command set ID and algorithm data offset

1Bh 36h System Interface Information Device timing & voltage information

27h 4Eh Device Geometry Definition Flash device layout

40h 80h Primary Algorithm-specific Extended

Query table Additional information specific to the Primary

Algorithm (optional)

61h C2h Security Code Area 64 bit unique device number

Address Data Description Value

x16 x8

10h 20h 0051h "Q"

11h 22h 0052h Query Unique ASCII String "QRY" "R"

12h 24h 0059h "Y"

13h 26h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algorithm AMD

Compatible

14h 28h 0000h

15h 2Ah 0040h Address for Primary Algorithm extended Query table (see Table 26) P = 40h

16h 2Ch 0000h

17h 2Eh 0000h Alternate Vendor Co mmand Set and Control Interface ID Code second

vendor - specified algorit hm supported NA

18h 30h 0000h

19h 32h 0000h Address for Alternate Algorithm extended Query table NA

1Ah 34h 0000h

33/41

M29W800DT, M29W800DB

Table 25. CFI Query System Interface Information

Note: 1. Not supported in the CFI

Table 26. Device Geometry Definition

Address Data Description Value

x16 x8

1Bh 36h 0027h VCC Logic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV 2.7V

1Ch 38h 0036h VCC Logic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV 3.6V

1Dh 3Ah 0000h VPP [Programming] Supply Minimum Program/Erase voltage NA

1Eh 3Ch 0000h VPP [Programming] Supply Maximum Program/Erase voltage NA

1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs

20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs NA

21h 42h 000Ah Typical timeout per individual block erase = 2n ms 1s

22h 44h 0000h Typical timeout for full chip erase = 2n ms see note (1)

23h 46h 0004h Maximum timeout for byte/word program = 2n times typical 256µs

24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA

25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 8s

26h 4Ch 0000h Maximum timeo ut for chip era se = 2n times typical see note (1)

Address Data Description Value

x16 x8

27h 4Eh 0014h Device Size = 2n in number of byt es 1 MByte

28h

29h 50h

52h 0002h

0000h Flash Device Interface Code description x8, x16

Async.

2Ah

2Bh 54h

56h 0000h

0000h Maximum number of bytes in multi-byte program or page = 2n NA

2Ch 58h 0004h Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing

contiguous Erase Blocks of the same size. 4

2Dh

2Eh 5Ah

5Ch 0000h

0000h Region 1 Infor mation

Number of identical size erase block = 0000h+1 1

2Fh

30h 5Eh

60h 0040h

0000h Region 1 Infor mation

Block size in Region 1 = 0040h * 256 byte 16 Kbyte

31h

32h 62h

64h 0001h

0000h Region 2 Infor mation

Number of identical size erase block = 0001h+1 2

33h

34h 66h

68h 0020h

0000h Region 2 Infor mation

Block size in Region 2 = 0020h * 256 byte 8 Kbyte

35h

36h 6Ah

6Ch 0000h

0000h Region 3 Infor mation

Number of identical size erase block = 0000h+1 1

M29W800DT, M29W800DB

34/41

Table 27. Primary Algorithm-Specific Extended Query Table

Table 28. Security Code Area

37h

38h 6Eh

70h 0080h

0000h Region 3 Infor mation

Block size in Region 3 = 0080h * 256 byte 32 Kbyte

39h

3Ah 72h

74h 000Eh

0000h Region 4 Infor mation

Number of identical-size erase block = 000Eh+1 15

3Bh

3Ch 76h

78h 0000h

0001h Region 4 Infor mation

Block size in Region 4 = 0100h * 256 byte 64 Kbyte

Address Data Description Value

x16 x8

40h 80h 0050h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

41h 82h 0052h "R"

42h 84h 0049h "I"

43h 86h 0031h Major version number, ASCII "1"

44h 88h 0030h Minor version number, ASCII "0"

45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

Yes

46h 8Ch 0002h Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write 2

47h 8Eh 0001h Block Protection

00 = not supported, x = number of sectors in per group 1

48h 90h 0001h Temporary Block Unprotect

00 = not supported, 01 = supported Yes

49h 92h 0004h Block Protect /Unprotect

04 = M29W400B 4

4Ah 94h 0000h Simultaneous Operations, 00 = not supported No

4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No

4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No

Address Data Description

x16 x8

61h C3h, C2h XXXX

64 bit: unique device number

62h C5h, C4h XXXX

63h C7h, C6h XXXX

64h C9h, C8h XXXX

Address Data Description Value

x16 x8

35/41

M29W800DT, M29W800DB

APPENDIX C. BLOCK PROT ECTION

Block protection can be used to prevent any oper-

ation f rom modify ing the da ta stored in the Fl ash.

Each Block can be protected individually. Once

protected, Program and Erase operations on the

block fail to change the data.

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In-System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pi n, RP ; thi s is d es cribed i n th e Si gna l De -

scriptions section.

Unlike the Command Interface of the Program/

Erase Controller, the techniques for protecting and

unprotecting blocks change between different

Flash memory suppliers. For example, the tech-

niques for AMD parts will not work on STMicro-

electronics parts. Care should be taken when

changing drivers for one part to work on another.

Programmer Technique

The Programmer technique uses high (VID) volt-

age levels on some of the bus pins. These cannot

be achieved using a standard microprocessor bus,

therefore the technique is recommended only for

use in Progra mming Equipment.

To protect a block follow the flowchart in Figure 20,

Programmer Equipment Block Protect Flowchart.

To u npr o tect the wh ol e chi p i t i s ne ce ss ar y to pr o-

tect all of the blocks first, then all blocks can be un-

protected at the sam e time . To u nprotect the ch ip

follow Figure 21, Programmer Equipment Chip

Unprotect Flowchart. Table 29, Programmer

Technique Bus Operations, gives a summary of

each operation.

The timing on these flowcharts is critical. Care

should be tak en to ensure that, wh ere a pause is

specifi ed, it is followe d as closely as possibl e. Do

not abort the procedure before reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

pin, RP. This can be achieved without violating the

maximum ratings of the components on the micro-

processor bus, therefore this technique is suitable

for use after the Flas h has been fitted to t he sys-

tem.

To protect a block follow the flowchart in Figure 22,

In-System Block Protect Flowchart. To unprotect

the whole c hip it is nec essary to prote ct all of the

blocks first, then all the blocks can be unprotected

at the same time. To unprotect the chip follow Fig-

ure 23, In-System Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care

should be tak en to ensure that, wh ere a pause is

specifi ed, it is followe d as closely as possibl e. Do

not allow the mi croproce ssor to service interr upts

that will upset the timing and do not abor t the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

Table 29. Programmer Technique Bus Operations, BYTE = VIH or VIL

Operation E G W Address Inputs

A0-A18 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Block Protect VIL VID VIL Pulse A9 = VID, A12-A18 Block Address

Others = X X

Chip Unpro te ct VID VID VIL Pulse A9 = VID, A12 = VIH, A1 5 = VIH

Others = X X

Block Protection

Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,

A12-A18 Block Address

Others = X

Pass = XX01h

Retry = XX00h

Block Unprotection

Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,

A12-A18 Block Address

Others = X

Retry = XX01h

Pass = XX00h

M29W800DT, M29W800DB

36/41

Figure 20. Programmer Equipment Block Protect Flowchart

ADDRESS = BLOCK ADDRESS

AI03469

G, A9 = VID,

E = VIL

n = 0

Wait 4µs

Wait 100µs

W = VIL

W = VIH

E, G = VIH,

A0, A6 = VIL,

A1 = VIH

A9 = VIH

E, G = VIH

++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

W = VIH

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

Verify Protect Set-upEnd

A9 = VIH

E, G = VIH

37/41

M29W800DT, M29W800DB

Figure 21. Programmer Equipment Chip Unprotect Flowchart

PROTECT ALL BLOCKS

AI03470

A6, A12, A15 = VIH(1)

E, G, A9 = VID

DATA

W = VIH

E, G = VIH

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1, A6 = VIH

Wait 10ms

00h

INCREMENT

CURRENT BLOCK

n = 0

CURRENT BLOCK = 0

Wait 4µs

W = VIL

++n

= 1000

START

YES

YESNO

NO LAST

BLOCK

YES

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

FAIL PASS

Verify Unprotect Set-upEnd

A9 = VIH

E, G = VIH A9 = VIH

E, G = VIH

M29W800DT, M29W800DB

38/41

Figure 22. In-System Equipment Bloc k Protect Flowchart

AI03471

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

n = 0

Wait 100µs

WRITE 40h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VIH ++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

RP = VIH

Wait 4µs

Verify Protect Set-upEnd

READ DATA

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

39/41

M29W800DT, M29W800DB

Figure 23. In-System Equipment Chip Unpr otect Flowchart

AI03472

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

n = 0

CURRENT BLOCK = 0

Wait 10ms

WRITE 40h

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VIH

++n

= 1000

START

FAIL PASS

YES

DATA

00h

YESNO

RP = VIH

Wait 4µs

READ DATA

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PROTECT ALL BLOCKS

INCREMENT

CURRENT BLOCK

LAST

BLOCK

YES

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

Verify Unprotect Set-upEnd

M29W800DT, M29W800DB

40/41

REVISION HISTORY

Table 30. Document Revision History

Version Revision Details

August 2001 1.0 First Issue

03-Dec-2001 2.0 Block Protection Appendix added, SO44 drawing and package mechanical data updated,

CFI Table 26, address 39h/72h data clarified, Read/Reset operation during Erase

Suspend cl arified

01-Mar-2002 3.0 Des crip tion of R e ady /B us y sign al cla rifie d (an d Fig ure 15 mod ifie d)

Clarified allowable commands during block erase

Clarified the mode the device returns to in the CFI Read Query command section

11-Apr-2002 4.0 Temperature range 1 added

Document promoted from Preliminary Data to full Data Sheet

31-Mar-2003 4.1

Erase Suspend Latency Time (typical and maximum) and Data Retention parameters

added to Table 6, Program, Erase Times and Program, Erase Endurance Cycles, and

Typical after 100k W/E Cycles column removed. Minimum voltage corrected for 70ns

Speed Cla ss in Table 9, Oper atin g an d AC Me as ure m ent Cond itions.

Logic Diagram and Data Toggle Flowchart corrected.

Lead-free package options E and F added to Table 20, Ordering Information Scheme.

13-Feb-2004 5.0 TSOP48 package Outline and Mechanical Data updated.

TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch added.

Table 9.Operating and AC Measurement Conditions updated for 70ns speed option.

23-Apr-2004 6.0 Figure 3., SO Connections updated.

41/41

M29W800DT, M29W800DB

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