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DATA SHEE

T

SURFACE-MOUNT CERAMIC

MULTILAYER CAPACITORS

Ultra small: NP0/X5R/X7R/Y5V

(Pb Free & RoHS compliant)

6.3 V TO 50 V

1 pF to 100 nF

Product specification – Apr 19, 2006 V.2

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

2

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

SCOPE

This specification describes ultra

small NP0/X5R/X7R/Y5V series

chip capacitors with lead-free

terminations.

FEATURES

z High capacitance per unit

volume

z Supplied in bulk case or in tape

on reel.

APPLICATIONS

z Mobile phones

z Digital cameras

z Camcorders

z Tuners

ORDERING INFORMATION

Components may be ordered by using either a Phycomp’s unique 12NC or Phycomp clear text code.

2 2 X X X X X X X X X X

Carrier type

22

38

50

54

55

blister

paper

blister Ur ≤ 6.3 V

bulk

paper Ur ≤ 6.3 V

Rated voltage

20

24

78

91

58

6.3 V

10 V

16 V

25 V

50 V

Size

8 0201

Capacitance value

Tolerance

4

5

6

7

8

See conversion table

(1)

±2%

±5%

±10%

±20%

−20/+80%

Packaging(2)

1

5

4

reel: ∅180 mm; 7"

reel: ∅330 mm; 13"

bulk case

Temperature characteristic

1

3

5

9

NP0 25 V only

X5R

X7R

Y5V

SCM043

2 2 X X X X X X X X X X

Carrier type

Voltage

Size

38

54

paper

bulk

86 50 V

8 0201

Capacitance value

Tolerance

Packing

SCM044

4

1

7

4

reel: ∅180 mm; 7"

reel: ∅330 mm; 13"

bulk case

See conversion table (1)

±0.1 pF for 0.47 pF ≤ C < 5 pF

±0.25 pF for 5 pF ≤ C < 10 pF

±2% for C ≥ 10 pF

±0.25 pF for C < 5 pF

±0.5 pF for 5 pF ≤ C < 10 pF

±5% for C ≥ 10 pF

5

(1) Refer to “Conversion table of capacitance & last 2/3 digits of 12NC”

(2) Quantity on reel depends on thickness classification; see section “Thickness classification and packing quantities”

P

PH

HY

YC

CO

OM

MP

P

O

OR

RD

DE

ER

RI

IN

NG

G

C

CO

OD

DE

E

12NC CODE

For NP0 25V / X5R / X7R / Y5V

For NP0 50V

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

3

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

CAP.

(nF)

LAST 2 DIGITS

OF 12NC

CAP.

(nF)

LAST 2 DIGITS

OF 12NC

CAP.

(nF)

LAST 2 DIGITS

OF 12NC

CAP.

(nF)

LAST 2 DIGITS

OF 12NC

27 28 39 31 56 33 82 35

33 29 47 32 68 34 100 36

Conversion table of capacitance & last 2/3 digits of 12NC -

NP0 25

V

CAP.

(nF)

LAST 3 DIGITS OF

12NC

CAP.

(nF)

LAST 3 DIGITS OF

12NC

CAP.

(nF)

LAST 3 DIGITS OF

12NC

1.0 108 3.3 338 10 109

1.2 128 3.9 398 12 129

1.5 158 4.7 478 15 159

1.8 188 5.6 568 18 189

2.2 228 6.8 688 22 229

2.7 278 8.2 33

Conversion table of capacitance & last 2/3 digits of 12NC -

NP0 50

V

Conversion table of capacitance & last 2/3 digits of 12NC -

X5R/X7R/Y5

V

CAP.

(nF)

LAST 2 DIGITS OF

12NC

CAP.

(nF)

LAST 2 DIGITS OF

12NC

CAP.

(nF)

LAST 2 DIGITS OF

12NC

0.047 05 0.68 21 10 36

0.068 07 1.0 23 15 38

0.10 09 1.5 25 22 41

0.15 12 2.2 27 33 43

0.22 14 3.3 29 47 45

0.33 16 4.7 32 68 47

0.47 18 6.8 34 100 49

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

4

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

CTC CODE

Ä Example: 02012R102K8B20D

0201 2R 102 K 8 B 2 0 D

Size

code

Temp.

Char.

Capacitance

in pF

Tolerance Rated

voltage

Termination

Packing Marking Range

identifier

0201

0402

0603

0805

1206

1210

1808

1812

0306

0508

0612

CG = NP0

2B = X5R

2R = X7R

2F = Y5V

2E = Z5U

102 = 1,000 pF;

the third digit

signifies the

multiplying factor:

8 = × 0.01

9 = × 0.1

0 = × 1

1 = × 10

2 = × 100

3 = × 1,000

4 = × 10,000

5 = × 100,000

6 = × 1000,000

7 = × 10,000,000

B = ±0.1 pF

C = ±0.25 pF

D = ±0.5 pF

F = ±1%

G = ±2%

J = ±5%

K = ±10%

M = ±20%

Z = –20%~+80%

5 = 6.3 V

6 = 10 V

7 = 16 V

8 = 25 V

9 = 50 V

0 = 100 V

B = 200 V

C = 250 V

D = 500 V

E = 1 KV

F = 2 KV

G = 3 KV

H = 4 KV

B = NiSn 2 = 180 mm; 7” paper

3 = 330 mm; 13” paper

B = 180 mm; 7” blister

F = 330 mm; 13” blister

P = Bulk case

0 = no marking

0 = conv.

ceramic

D = BME

L = low

inductance

M = microwave

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

5

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

CONSTRUCTION

The capacitor consists of a

rectangular block of ceramic

dielectric in which a number of

interleaved metal electrodes are

contained. This structure gives

rise to a high capacitance per

unit volume.

The inner electrodes are

connected to the two end

terminations and finally covered

with a layer of plated tin (NiSn).

The terminations are lead-free. A

cross section of the structure is

shown in Fig.1.

MLB457

terminations

electrodes

ceramic material

Fig. 1

Surface mounted multilayer ceramic capacito

r

construction

MBB211

T

L4

L1

L2L3

W

Fig. 2 Surface mounted multilayer

ceramic capacitor dimension

For dimension see Table 1

DIMENSION

Table 1

TYPE L1 (mm) W (mm) T (mm) L2/L3 (mm) L4 (mm)

min. max. min.

CC0201 0.6 ±0.03 0.3 ±0.03 0.3 ±0.03 0.10 0.20 0.20

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

6

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

Table 2

CAPACITANCE RANGE & THICKNESS FOR SIZE 0201 OF NP0 25/50 V

CAPACITANCE 0201

0201

(pF) 25 V

50 V

1.0

0.3 ±0.03

1.2

1.5

1.8

2.2

2.7

3.3

3.9

4.7

5.6

6.8

8.2

10

12

15

18

22

27 0.3 ±0.03

33

39

47

56

68

82

100

NOTE

1. Values in shaded cells indicate thickness class in mm.

2. Capacitance range < 1 pF is on request.

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

7

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

Table 3

CAPACITANCE RANGE & THICKNESS FOR SIZE 0201 OF X5R/X7R/Y5V/ 6.3/10/16/25/50 V

CAPACITANCE X5R X7R

Y5V

(nF) 6.3 V 10 V

16 V

25 V

50 V 6.3 V

0.047

0.3 ±0.03

0.068

0.10

0.15

0.22

0.33

0.47

0.68

0.3 ±0.03

1.0 0.3 ±0.03

0.3 ±0.03

1.5

2.2

3.3

4.7

6.8

10

15

22

33

47

68

100 0.3 ±0.03

0.3 ±0.03

NOTE

1. Values in shaded cells indicate thickness class in mm.

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

8

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

Table 4

THICKNESS CLASSES AND PACKING QUANTITY

8 mm TAPE WIDTH/AMOUNT PER REEL

Ø180 mm, 7”

Ø330 mm, 13”

12 mm TAPE WIDTH

/AMOUNT PER REEL

DESCRIPTION SIZE

CODE

THICKNESS

CLASSIFICATION

(mm) Paper

Blister

Paper

Blister

Ø180 mm, 7” Blister

A

MOUNT

PER

BULK CASE

0201 0.3 ±0.03 15,000 --- 50,000 --- --- ---

0402 0.5 ±0.05 10,000 --- 50,000 --- --- 50,000

0603 0.8 ±0.07 4,000 --- 15,000 --- --- 15,000

0805 0.6 ±0.10 4,000 --- 20,000 --- --- 10,000

0.85 ±0.1 4,000 --- 15,000 --- --- 8,000

1.25 ±0.10 --- 3,000 --- 10,000 --- 5,000

1206 0.6 ±0.10 4,000 --- 20,000 --- --- ---

0.85 ±0.10 4,000 --- 15,000 --- --- ---

1.00 / 1.15 ±0.10 --- 3,000 --- 10,000 --- ---

1.6 ±0.15 --- 2 500 --- 10,000 --- ---

1.6 ±0.20 --- 2,000 --- 10,000 --- ---

1210 0.6 / 0.7 ±0.10 --- 4,000 --- 15,000 --- ---

0.85 ±0.10 --- 4,000 --- 10,000 --- ---

1.15 ±0.10 --- 3,000 --- 10,000 --- ---

1.15 ±0.15 --- 3,000 --- 10,000 --- ---

1.5 ±0.10 --- 2,000 --- --- --- ---

1.6 / 1.9 ±0.20 --- 2,000 --- --- --- ---

2.5 ±0.20 --- 1,000 --- --- --- ---

1808 1.15 ±0.15 --- --- --- --- 1 500 ---

1.35 ±0.15 --- --- --- --- 1,000 ---

1.5 ±0.10 --- --- --- --- 1,000 ---

1812 0.6 / 0.85 ±0.10 --- --- --- --- 2,000 ---

1.15 ±0.10 --- --- --- --- 1,500 ---

1.15 ±0.15 --- --- --- --- 1,500 ---

1.35 ±0.15 --- --- --- --- 1,000 ---

1.5 ±0.1 --- --- --- --- 1,000 ---

Discrete

capacitors

1.6 ±0.2 --- --- --- --- 1,000 ---

0508 0.6 ±0.10 4,000 --- --- --- --- ---

0.85 ±0.10 4,000 --- --- --- --- ---

0612 0.8 ±0.10 4,000 --- --- --- --- ---

Arrays

1.2 ±0.10 --- 3,000 --- --- --- ---

NOTE

1. For bulk case, tape and reel specification/dimensions, please see the special data sheet “Packing” document.

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

9

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

ELECTRICAL CHARACTERISTICS

N

NP

P0

0/

/X

X5

5R

R/

/X

X7

7R

R/

/Y

Y5

5V

V

D

DI

IE

EL

LE

EC

CT

TR

RI

IC

C

CA

AP

PA

AC

CI

IT

TO

OR

RS

S;

;

N

NI

IS

SN

N

T

TE

ER

RM

MI

IN

NA

AT

TI

IO

ON

NS

S

Unless otherwise stated all electrical values apply at an ambient temperature of 20±1 °C, an atmospheric

pressure of 86 to 106 kPa, and a relative humidity of 63 to 67%.

Table 5

DESCRIPTION VALUE

Capacitance range (1) :

NP0

X5R/Y5V

X7R

1 pF to 100 pF

100 nF

47 pF to 10 nF

RATED VOLTAGE Ur (DC):

NP0

X5R/Y5V

X7R

25/50 V

6.3 V

10/16/25/50 V

Capacitance tolerance (1):

NP0

X5R

X7R

Y5V

C <10 pF: ±0.25 pF, ±0.50 pF; C ≥10 pF: ±5%

±10%

–20% ~ +80%

Dissipation factor (D.F.) (1) (max.):

NP0

X5R

X7R

Y5V

C ≤10 pF:

C 100

7C 30

D.F.

×

+

=or 0.3%; whichever is smallest; C >10 pF: 0.1%

10%

10 V: 5%; 16 V: 3.5%; 25/50 V: 2.5%

15%

Insulation resistance after 1 minute at Ur (DC) Rins ≥ 10 GΩ or Rins × C ≥ 500 seconds whichever is less

Maximum capacitance change as a function of

temperature (temperature

characteristic/coefficient):

NP0

X5R/X7R

Y5V

±30 ppm/°C

±15%

+22% ~ –82%

Operating temperature range:

NP0/X7R

X5R

Y5V

–55 °C to +125 °C

–55 °C to +85 °C

–30 °C to +85 °C

NOTE

1. f=1 KHz for C ≤ 10 µF; measuring at voltage 1 Vrms; f=120 Hz for C > 10 µF; measuring at voltage 0.5 Vrms.

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

10

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

TEST TEST METHOD PROCEDURE REQUIREMENTS

Mounting IEC 60384-

21/22

4.3 The capacitors may be mounted on printed-circuit boards or

ceramic substrates

No visible damage

Visual

inspection and

dimension

chec

k

4.4

Any applicable method using × 10 magnification In accordance with

specification

Capacitance 4.5.1

NP0:

f = 1 MHz for C ≤ 1 nF, measuring at voltage 1 Vrms at 20 °C;

f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C

X5R/X7R/Y5V:

f = 1 KHz for C ≤ 10 µF, measuring at voltage 1 Vrms at 20 °C

Within specified tolerance

Dissipation

factor (D.F.)

4.5.2

NP0:

f = 1 MHz for C ≤ 1 nF, measuring at voltage 1 Vrms at 20 °C;

f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C

X5R/X7R/Y5V:

f = 1 KHz for C ≤ 10 µF, measuring at voltage 1 Vrms at 20 °C

In accordance with

specification

Insulation

resistance

4.5.3

At Ur (DC) for 1 minute In accordance with

specification

Voltage proo

f

4.5.4.2

Test voltage (DC) applied for 1 minute

Ur ≤ 100 V: 2.5 × Ur applied to NP0/X5R/X7R/Y5V series

100 V < Ur ≤ 200 V: 1.5 × Ur +100 V applied to NP0/X7R series

200 V < Ur ≤ 500 V: 1.3 × Ur +100 V applied to NP0/X7R series

Ur > 500 V: 1.3 × Ur applied to NP0/X7R series

I: 7.5 mA

No breakdown or

flashover

Temperature

characteristic

4.6

Between minimum and maximum temperature NP0: ΔC/C: ±30 ppm/°C

X5R/X7R: ΔC/C: ±15%

Y5V: ΔC/C: +22%~

–82%

Adhesion 4.15

A force applied for 10 seconds to the line joining the terminations

and in a plane parallel to the substrate

for size ≥ 0603: a force of 5 N applied

for size 0402: a force of 2.5 N applied

for size 0201: a force of 1 N applied

No visible damage

Table 6 Test condition, procedure and requirements

TESTS AND REQUIREMENTS

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

11

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

TEST TEST METHOD PROCEDURE REQUIREMENTS

Mounting in accordance with IEC 60384-22 paragraph

4.3

No visible damage

Bond strength

of plating on

end face

IEC 60384-

21/22

4.8

Conditions: bending 1 mm at a rate of 1 mm/s, radius jig

340 mm

NP0: lΔC/Cl: ≤ 1% or 0.5 pF

whichever is greater

X5R/X7R/Y5V: lΔC/Cl: ≤ 10%

Resistance to

soldering heat

4.9

Precondition: 150 +0/–10 °C for 1 hour, then keep for

24 ±1 hours at room temperature

Preheating: for size ≤ 1206: 120 to 150 °C for 1 minute

Preheating: for size >1206: 100 to 120 °C for 1 minute

and 170 to 200 °C for 1 minute

Solder bath temperature: 260 ±5 °C

Dipping time: 10 ±0.5 seconds

Recovery time: 24 ±2 hours.

The termination shall be well tinned

NP0: lΔC/Cl: ≤ 0.5% or 0.5 pF

whichever is greater

X5R/X7R: lΔC/Cl: ≤ 10%

Y5V: lΔC/Cl: ≤ 20%

D.F.: within initial specified value

Rins: within initial specified value

Solderabilit

y

4.10

Unmounted chips completely immersed in a solder bath

at 235 ±5 °C

Dipping time: 2 ±0.5 seconds

Depth of immersion: 10 mm

The termination shall be well

tinned.

Preconditioning;

150 +0/–10 °C for 1 hour, then keep for 24 ±1 hours

a

t

room temperature

5 cycles with following detail:

30 minutes at lower category temperature;

30 minutes at upper category temperature

Rapid change

o

f

temperature

4.11

Recovery time 24 ±2 hours.

No visual damage

NP0: lΔC/Cl: ≤ 1% or 1 pF

whichever is greater

X5R/X7R: lΔC/Cl: ≤ 15%

Y5V: lΔC/Cl: ≤ 20%

D.F.: within initial specified value

Rins: within initial specified value

Damp heat,

with Ur load

4.13

Initial measurements; after 150 +0/-10 °C for 1 hour,

then keep for 24 ±1 hours at room temperature

Duration and conditions: 500 ±12 hours at 40 ±2 °C;

90 to 95% RH; Ur applied

Final measurement: perform a heat treatment at

150 +0/–10 °C for 1 hour, final measurements shall be

carried out 24 ±1 hours after recovery at room

temperature without load.

NP0: lΔC/Cl: ≤ 2% or 1 pF

whichever is greater

X5R/X7R: lΔC/Cl: ≤ 20%

Y5V: lΔC/Cl: ≤ 30%

NP0/X5R/X7R/Y5V: D.F.: 2 × initial

value max.

NP0: Rins ≥ 2,500 MΩ or Rins × Cr

≥ 25 seconds, whichever is less

X5R/X7R/Y5V: Rins ≥ 500 MΩ or

Rins × Cr ≥ 25 seconds, whichever

is less

Table 6 Test condition, procedure and requirements

(continued)

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

12

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

TEST TEST METHOD PROCEDURE REQUIREMENTS

Endurance IEC 60384-

21/22

4.14 Preconditioning;

Initial measurements; after 150 +0/-10 °C for 1 hour,

then keep for 24 ±1 hours at room temperature

Duration and conditions: 1,000 ±12 hours at upper

category temperature with 1.5 × Ur voltage applied

Final measurement: perform a heat treatment at 150

+0/–10 °C for 1 hour, final measurements shall be

carried out 24 ±1 hours after recovery at room

temperature without load.

NP0: lΔC/Cl: ≤ 2% or 1 pF whichever

is greater

X5R/X7R: lΔC/Cl: ≤ 20%

Y5V: lΔC/Cl: ≤ 30%

NP0/X5R/X7R/Y5V: D.F.: 2 × initial

value max.

NP0: Rins ≥ 4,000 MΩ or Rins × Cr ≥

40 seconds, whichever is less

X5R/X7R/Y5V: Rins ≥ 1,000 MΩ or

Rins × Cr ≥ 50 seconds, whichever is

less

Table 6 Test condition, procedure and requirements

(con

t

inued)

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Apr 19, 2006 V.2

Surface-Mount Ceramic Multilayer Capacitors

13

Product specification

Ultra small

NP0/X5R/X7R/Y5V

6.3 V to 50 V

REVISION HISTORY

REVISION DATE CHANGE NOTIFICATION DESCRIPTION

Version 2 Apr 19, 2006 - - New datasheet for ultra small NP0/X5R/X7R/Y5V series chip capacitors

with lead-free terminations

- Test method and procedure updated

Version 1 Mar 22, 2004 - -

Version 0 Mar 18, 2004 - -