1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
CS SCLK
VADOUT
AGND DIN
IN0 VD
IN1 DGND
IN2 IN7
IN3 IN6
IN4 IN5
ADC128S102
ADC128S102
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SNAS298F –AUGUST 2005–REVISED MAY 2013
ADC128S102 8-Channel, 500 ksps to 1 Msps, 12-Bit A/D Converter
Check for Samples: ADC128S102
1FEATURES DESCRIPTION
The ADC128S102 is a low-power, eight-channel
234• Eight Input Channels CMOS 12-bit analog-to-digital converter specified for
• Variable Power Management conversion throughput rates of 500 ksps to 1 MSPS.
• Independent Analog and Digital Supplies The converter is based on a successive-
approximation register architecture with an internal
• SPI™/ QSPI™/ MICROWIRE™/DSP Compatible track-and-hold circuit. It can be configured to accept
• Packaged in 16-Lead TSSOP up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is
APPLICATIONS compatible with several standards, such as SPI™,
• Automotive Navigation QSPI™, MICROWIRE™, and many common DSP
• Portable Systems serial interfaces.
• Medical Instruments The ADC128S102 may be operated with independent
• Mobile Communications analog and digital supplies. The analog supply (VA)
can range from +2.7V to +5.25V, and the digital
• Instrumentation and Control Systems supply (VD) can range from +2.7V to VA. Normal
power consumption using a +3V or +5V supply is 2.3
KEY SPECIFICATIONS mW and 10.7 mW, respectively. The power-down
• Conversion Rate 500 ksps to 1 MSPS feature reduces the power consumption to 0.06 µW
using a +3V supply and 0.25 µW using a +5V supply.
• DNL (VA= VD= 5.0 V) +1.5 / −0.9 The ADC128S102 is packaged in a 16-lead TSSOP
• LSB (max) INL (VA= VD= 5.0 V) ±1.2 LSB (max) package. Operation over the extended industrial
• Power Consumption temperature range of −40°C to +105°C is ensured.
– 3V Supply 2.3 mW (typ)
– 5V Supply 10.7 mW (typ)
Connection Diagram
Figure 1. TSSOP Package
See Package Number PW0016A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2MICROWIRE is a trademark of Texas Instruments.
3SPI, QSPI are trademarks of Motorola, Inc..
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
IN0
IN7
MUX T/H
ADC128S102 SCLK
VA
AGND
DGND
VD
CS
DIN
DOUT
CONTROL
LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
.
.
.
AGND
ADC128S102
SNAS298F –AUGUST 2005–REVISED MAY 2013
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Block Diagram
Pin Descriptions
Pin No. Name Description
ANALOG I/O
4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to VREF.
DIGITAL I/O
Digital clock input. The ensured performance range of frequencies for this input is 8 MHz to 16 MHz.
16 SCLK This clock directly controls the conversion and readout processes.
15 DOUT Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin.
Digital data input. The ADC128S102's Control Register is loaded through this pin on rising edges of the
14 DIN SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as
1 CS CS is held low.
POWER SUPPLY
Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be
2 VAconnected to a quiet +2.7V to +5.25V source and bypassed to GND with 1 µF and 0.1 µF monolithic
ceramic capacitors located within 1 cm of the power pin.
Positive digital supply pin. This pin should be connected to a +2.7V to VAsupply, and bypassed to
13 VDGND with a 0.1 µF monolithic ceramic capacitor located within 1 cm of the power pin.
3 AGND The ground return for the analog supply and signals.
12 DGND The ground return for the digital supply and signals.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1)(2)
Analog Supply Voltage VA−0.3V to 6.5V
Digital Supply Voltage VD−0.3V to VA+ 0.3V, max 6.5V
Voltage on Any Pin to GND −0.3V to VA+0.3V
Input Current at Any Pin (3) ±10 mA
Package Input Current(3) ±20 mA
Power Dissipation at TA= 25°C See (4)
ESD Susceptibility (5) Human Body Model 2500V
Machine Model 250V
For soldering specifications: see product folder at www.ti.com and http://www.ti.com/lit/SNOA549
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VAor VD), the current at that pin should be
limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 10 mA to two.
(4) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax −TA)/θJA. In the 16-pin TSSOP, θJA is 96°C/W, so PDMAX = 1,200 mW at 25°C and 625 mW at the maximum
operating ambient temperature of 105°C. Note that the power consumption of this device under normal operation is a maximum of 12
mW. The values for maximum power dissipation listed above will be reached only when the ADC128S102 is operated in a severe fault
condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
(5) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through ZERO ohms
Operating Ratings (1)(2)
Operating Temperature −40°C ≤TA≤+105°C
VASupply Voltage +2.7V to +5.25V
VDSupply Voltage +2.7V to VA
Digital Input Voltage 0V to VA
Analog Input Voltage 0V to VA
Clock Frequency 8 MHz to 16 MHz
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance
Package θJA
16-lead TSSOP on 4-layer, 2 oz. PCB 96°C / W
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ADC128S102 Converter Electrical Characteristics (1)
The following specifications apply for AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 MSPS, CL=
50pF, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.
Limits
Parameter Test Conditions Typical Units
(2)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits
VA= VD= +3.0V ±0.4 ±1 LSB (max)
Integral Non-Linearity (End Point
INL Method) VA= VD= +5.0V ±0.5 ±1.2 LSB (max)
+0.4 +0.9 LSB (max)
VA= VD= +3.0V −0.2 −0.7 LSB (min)
DNL Differential Non-Linearity +0.7 +1.5 LSB (max)
VA= VD= +5.0V −0.4 −0.9 LSB (min)
VA= VD= +3.0V +0.8 ±2.3 LSB (max)
VOFF Offset Error VA= VD= +5.0V +1.1 ±2.3 LSB (max)
VA= VD= +3.0V ±0.1 ±1.5 LSB (max)
OEM Offset Error Match VA= VD= +5.0V ±0.3 ±1.5 LSB (max)
VA= VD= +3.0V +0.8 ±2.0 LSB (max)
FSE Full Scale Error VA= VD= +5.0V +0.3 ±2.0 LSB (max)
VA= VD= +3.0V ±0.1 ±1.5 LSB (max)
FSEM Full Scale Error Match VA= VD= +5.0V ±0.3 ±1.5 LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
VA= VD= +3.0V 8 MHz
FPBW Full Power Bandwidth (−3dB) VA= VD= +5.0V 11 MHz
VA= VD= +3.0V, 73 70 dB (min)
fIN = 40.2 kHz, −0.02 dBFS
SINAD Signal-to-Noise Plus Distortion Ratio VA= VD= +5.0V, 73 70 dB (min)
fIN = 40.2 kHz, −0.02 dBFS
VA= VD= +3.0V, 73 70.8 dB (min)
fIN = 40.2 kHz, −0.02 dBFS
SNR Signal-to-Noise Ratio VA= VD= +5.0V, 73 70.8 dB (min)
fIN = 40.2 kHz, −0.02 dBFS
VA= VD= +3.0V, −88 −74 dB (max)
fIN = 40.2 kHz, −0.02 dBFS
THD Total Harmonic Distortion VA= VD= +5.0V, −90 −74 dB (max)
fIN = 40.2 kHz, −0.02 dBFS
VA= VD= +3.0V, 91 75 dB (min)
fIN = 40.2 kHz, −0.02 dBFS
SFDR Spurious-Free Dynamic Range VA= VD= +5.0V, 92 75 dB (min)
fIN = 40.2 kHz, −0.02 dBFS
VA= VD= +3.0V, 11.8 11.3 Bits (min)
fIN = 40.2 kHz
ENOB Effective Number of Bits VA= VD= +5.0V, 11.8 11.3 Bits (min)
fIN = 40.2 kHz, −0.02 dBFS
VA= VD= +3.0V, 82 dB
fIN = 20 kHz
ISO Channel-to-Channel Isolation VA= VD= +5.0V, 84 dB
fIN = 20 kHz, −0.02 dBFS
(1) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
(2) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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ADC128S102 Converter Electrical Characteristics (1) (continued)
The following specifications apply for AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 MSPS, CL=
50pF, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.
Limits
Parameter Test Conditions Typical Units
(2)
VA= VD= +3.0V, −89 dB
fa= 19.5 kHz, fb= 20.5 kHz
Intermodulation Distortion, Second
Order Terms VA= VD= +5.0V, −91 dB
fa= 19.5 kHz, fb= 20.5 kHz
IMD VA= VD= +3.0V, −88 dB
fa= 19.5 kHz, fb= 20.5 kHz
Intermodulation Distortion, Third Order
Terms VA= VD= +5.0V, −88 dB
fa= 19.5 kHz, fb= 20.5 kHz
ANALOG INPUT CHARACTERISTICS
VIN Input Range 0 to VAV
IDCL DC Leakage Current ±1 µA (max)
Track Mode 33 pF
CINA Input Capacitance Hold Mode 3 pF
DIGITAL INPUT CHARACTERISTICS
VA= VD= +2.7V to +3.6V 2.1 V (min)
VIH Input High Voltage VA= VD= +4.75V to +5.25V 2.4 V (min)
VIL Input Low Voltage VA= VD= +2.7V to +5.25V 0.8 V (max)
IIN Input Current VIN = 0V or VD±0.01 ±1 µA (max)
CIND Digital Input Capacitance 2 4pF (max)
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA,
VOH Output High Voltage VD−0.5 V (min)
VA= VD= +2.7V to +5.25V
ISINK = 200 µA to 1.0 mA,
VOL Output Low Voltage 0.4 V (max)
VA= VD= +2.7V to +5.25V
IOZH, IOZL Hi-Impedance Output Leakage Current VA= VD= +2.7V to +5.25V ±1 µA (max)
COUT Hi-Impedance Output Capacitance (3) 24pF (max)
Output Coding Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL= 10 pF)
2.7 V (min)
VA, VDAnalog and Digital Supply Voltages VA≥VD5.25 V (max)
VA= VD= +2.7V to +3.6V, 0.76 1.5 mA (max)
fSAMPLE = 1 MSPS, fIN = 40 kHz
Total Supply Current
Normal Mode ( CS low) VA= VD= +4.75V to +5.25V, 2.13 3.1 mA (max)
fSAMPLE = 1 MSPS, fIN = 40 kHz
IA+ IDVA= VD= +2.7V to +3.6V, 20 nA
fSCLK = 0 ksps
Total Supply Current
Shutdown Mode (CS high) VA= VD= +4.75V to +5.25V, 50 nA
fSCLK = 0 ksps
VA= VD= +3.0V 2.3 4.5 mW (max)
fSAMPLE = 1 MSPS, fIN = 40 kHz
Power Consumption
Normal Mode ( CS low) VA= VD= +5.0V 10.7 15.5 mW (max)
fSAMPLE = 1 MSPS, fIN = 40 kHz
PCVA= VD= +3.0V 0.06 µW
fSCLK = 0 ksps
Power Consumption
Shutdown Mode (CS high) VA= VD= +5.0V 0.25 µW
fSCLK = 0 ksps
(3) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
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ADC128S102 Converter Electrical Characteristics (1) (continued)
The following specifications apply for AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 MSPS, CL=
50pF, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.
Limits
Parameter Test Conditions Typical Units
(2)
AC ELECTRICAL CHARACTERISTICS
fSCLKMIN Minimum Clock Frequency VA= VD= +2.7V to +5.25V 0.8 8MHz (min)
fSCLK Maximum Clock Frequency VA= VD= +2.7V to +5.25V 16 MHz (max)
50 500 ksps (min)
Sample Rate
fSVA= VD= +2.7V to +5.25V
Continuous Mode 1MSPS (max)
tCONVERT Conversion (Hold) Time VA= VD= +2.7V to +5.25V 13 SCLK cycles
30 40 % (min)
DC SCLK Duty Cycle VA= VD= +2.7V to +5.25V 70 60 % (max)
tACQ Acquisition (Track) Time VA= VD= +2.7V to +5.25V 3SCLK cycles
Acquisition Time + Conversion Time
Throughput Time 16 SCLK cycles
VA= VD= +2.7V to +5.25V
tAD Aperture Delay VA= VD= +2.7V to +5.25V 4 ns
ADC128S102 Timing Specifications
The following specifications apply for VA= VD= +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE =
500 ksps to 1 MSPS, and CL= 50pF. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.
Limits
Parameter Test Conditions Typical Units
(1)
tCSH CS Hold Time after SCLK Rising Edge 0 10 ns (min)
tCSS CS Setup Time prior to SCLK Rising Edge 4.5 10 ns (min)
tEN CS Falling Edge to DOUT enabled 5 30 ns (max)
tDACC DOUT Access Time after SCLK Falling Edge 17 27 ns (max)
tDHLD DOUT Hold Time after SCLK Falling Edge 4 ns (typ)
tDS DIN Setup Time prior to SCLK Rising Edge 3 10 ns (min)
tDH DIN Hold Time after SCLK Rising Edge 3 10 ns (min)
0.4 x
tCH SCLK High Time ns (min)
tSCLK
0.4 x
tCL SCLK Low Time ns (min)
tSCLK
DOUT falling 2.4 20 ns (max)
tDIS CS Rising Edge to DOUT High-Impedance DOUT rising 0.9 20 ns (max)
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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tCSH
SCLK
CS
tCSS
CS
tCONVERT
tACQ tCH
tCL tDACC
tEN
tDH
tDS
FOUR ZEROS DB10
DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
DB11 DB9 DB8 DB1
1687654321
DB0
DIN
DOUT
SCLK
CS
tDIS
tDHLD
8 9 10 11 12 13 14 15 16
Track Hold
Power Up
ADD2 ADD1 ADD0
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DIN
DOUT
SCLK
CS
Control register
1 2 3 4 5 6 7
1 2 3 4 5 6 7
ADD2 ADD1 ADD0
8
DB11 DB10 DB9
Power
Down
Power Up
Track Hold
FOUR ZEROS FOUR ZEROS
DB1 DB0
ADC128S102
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SNAS298F –AUGUST 2005–REVISED MAY 2013
TIMING DIAGRAMS
Figure 2. ADC128S102 Operational Timing Diagram
Figure 3. ADC128S102 Serial Timing Diagram
Figure 4. SCLK and CS Timing Parameters
Specification Definitions
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold
capacitor is charged by the input voltage.
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is
internally acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another
channel.
CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-to-
Channel Isolation, except for the sign of the data.
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2
f1
2
f10
2
f2
10
‡A
A++A
logTHD = 20
ADC128S102
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DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below
VREF+and is defined as:
VFSE = Vmax + 1.5 LSB – VREF+(1)
where Vmax is the voltage at which the transition to the maximum code occurs. FSE can be expressed in Volts,
LSB or percent of full scale range.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as the ratio of the
power in both the second or the third order intermodulation products to the power in one of the original
frequencies. Second order products are fa± fb, where faand fbare the two sine wave input frequencies. Third
order products are (2fa± fb) and (fa± 2fb). IMD is usually expressed in dB.
MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be
reached with any input value. The ADC128S102 is ensured not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including d.c. or
the harmonics included in THD.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is
any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic
components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated
as:
(2)
where Af1 is the RMS power of the input frequency at the output and Af2 through Af10 are the RMS power in the
first 9 harmonic frequencies.
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the
acquisition time plus the conversion and read out times. In the case of the ADC128S102, this is 16 SCLK
periods.
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Typical Performance Characteristics
TA= +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
DNL DNL
Figure 5. Figure 6.
INL INL
Figure 7. Figure 8.
DNL INL
vs. vs.
Supply Supply
Figure 9. Figure 10.
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Typical Performance Characteristics (continued)
TA= +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
SNR THD
vs. vs.
Supply Supply
Figure 11. Figure 12.
ENOB DNL
vs. vs.
Supply VDwith VA= 5.0 V
Figure 13. Figure 14.
INL DNL
vs. vs.
VDwith VA= 5.0 V SCLK Duty Cycle
Figure 15. Figure 16.
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Typical Performance Characteristics (continued)
TA= +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
INL SNR
vs. vs.
SCLK Duty Cycle SCLK Duty Cycle
Figure 17. Figure 18.
THD ENOB
vs. vs.
SCLK Duty Cycle SCLK Duty Cycle
Figure 19. Figure 20.
DNL INL
vs. vs.
SCLK SCLK
Figure 21. Figure 22.
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Typical Performance Characteristics (continued)
TA= +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
SNR THD
vs. vs.
SCLK SCLK
Figure 23. Figure 24.
ENOB DNL
vs. vs.
SCLK Temperature
Figure 25. Figure 26.
INL SNR
vs. vs.
Temperature Temperature
Figure 27. Figure 28.
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Typical Performance Characteristics (continued)
TA= +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
THD ENOB
vs. vs.
Temperature Temperature
Figure 29. Figure 30.
SNR THD
vs. vs.
Input Frequency Input Frequency
Figure 31. Figure 32.
ENOB Power Consumption
vs. vs.
Input Frequency SCLK
Figure 33. Figure 34.
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IN0
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
IN7
VA/2
IN0
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+CONTRO
L
LOGI
C
CHARGE
REDISTRIBUTION
DAC
VA/2
SW2
IN7
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FUNCTIONAL DESCRIPTION
The ADC128S102 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter.
ADC128S102 OPERATION
Simplified schematics of the ADC128S102 in both track and hold operation are shown in Figure 35 and Figure 36
respectively. In Figure 35, the ADC128S102 is in track mode: switch SW1 connects the sampling capacitor to
one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC128S102 is in this state for the first three SCLK cycles after CS is brought low.
Figure 36 shows the ADC128S102 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC128S102 is in this state for the last thirteen SCLK cycles
after CS is brought low.
Figure 35. ADC128S102 in Track Mode
Figure 36. ADC128S102 in Hold Mode
SERIAL INTERFACE
An operational timing diagram and a serial interface timing diagram for the ADC128S102 are shown in the
Timing Diagrams section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial
clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin,
where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC128S102's
Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high
and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS
is brought high.
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ADC128S102
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SNAS298F –AUGUST 2005–REVISED MAY 2013
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock
out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than
one conversion in a frame (continuous conversion mode), the ADC will re-enter the track mode on the falling
edge of SCLK after the N*16th rising edge of SCLK and re-enter the hold/convert mode on the N*16+4th falling
edge of SCLK. "N" is an integer value.
The ADC128S102 enters track mode under three different conditions. In Figure 2, CS goes low with SCLK high
and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as
the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters
track mode. While there is no timing restriction with respect to the rising edges of CS and SCLK, see Figure 4 for
setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
While a conversion is in progress, the address of the next input for conversion is clocked into a control register
through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. See Table 1,Table 2, and Table 3.
There is no need to incorporate a power-up delay or dummy conversions as the ADC128S102 is able to acquire
the input signal to full resolution in the first conversion immediately following power-up. The first conversion result
after power-up will be that of IN0.
Table 1. Control Register Bits
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
Table 2. Control Register Bit Descriptions
Bit No: Symbol: Description
7, 6, 2, 1, 0 DONTC Don't care. The values of these bits do not affect the device.
5 ADD2 These three bits determine which input channel will be sampled and converted at the next
conversion cycle. The mapping between codes and channels is shown in Table 3.
4 ADD1
3 ADD0
Table 3. Input Channel Selection
ADD2 ADD1 ADD0 Input Channel
0 0 0 IN0 (Default)
0 0 1 IN1
0 1 0 IN2
0 1 1 IN3
1 0 0 IN4
1 0 1 IN5
1 1 0 IN6
1 1 1 IN7
ADC128S102 TRANSFER FUNCTION
The output format of the ADC128S102 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC128S102 is VA/ 4096. The ideal transfer characteristic is shown
in Figure 37. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB,
or a voltage of VA/ 8192. Other code transitions occur at steps of one LSB.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: ADC128S102
|
|
|
0V +VA - 1.5LSB
0.5LSB ANALOG INPUT
1LSB = VA/4096
ADC CODE
111...111
111...110
111...000
011...111
000...010
000...001
000...000
ADC128S102
SNAS298F –AUGUST 2005–REVISED MAY 2013
www.ti.com
Figure 37. Ideal Transfer Characteristic
ANALOG INPUTS
An equivalent circuit for one of the ADC128S102's input channels is shown in Figure 38. Diodes D1 and D2
provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going
beyond this range will cause the ESD diodes to conduct and result in erratic operation.
The capacitor C1 in Figure 38 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1
is the on resistance of the multiplexer and track / hold switch and is typically 500 ohms. Capacitor C2 is the
ADC128S102 sampling capacitor, and is typically 30 pF. The ADC128S102 will deliver best performance when
driven by a low-impedance source (less than 100 ohms). This is especially important when using the
ADC128S102 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or low-
pass filter which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing
filters.
Figure 38. Equivalent Input Circuit
DIGITAL INPUTS AND OUTPUTS
The ADC128S102's digital inputs (SCLK, CS, and DIN) have an operating range of 0 V to VA. They are not prone
to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output (DOUT)
operating range is controlled by VD. The output high voltage is VD- 0.5V (min) while the output low voltage is
0.4V (max).
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Product Folder Links: ADC128S102
S
SN
S
N
SN
N
CP
tt t
P
tt t
P++
=xx
+
IN0
IN7
.
.
.MICROPROCESSOR
DSP
SCLK
CS
DIN
DOUT
AGND
VA
VD
ADC128S102
LP2950 5V
0.1 PF1.0 PF0.1 PF1 PF0.1 PF
DGND
1.0 PF
51:
22:
INPUT
1 nF
ADC128S102
www.ti.com
SNAS298F –AUGUST 2005–REVISED MAY 2013
Applications Information
TYPICAL APPLICATION CIRCUIT
A typical application is shown in Figure 39. The split analog and digital supply pins are both powered in this
example by the TI LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor
network located close to the ADC128S102. The digital supply is separated from the analog supply by an isolation
resistor and bypassed with additional capacitors. The ADC128S102 uses the analog supply (VA) as its reference
voltage, so it is very important that VAbe kept as clean as possible. Due to the low power requirements of the
ADC128S102, it is also possible to use a precision reference as a power supply.
Figure 39. Typical Application Circuit
POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this product: power supply sequencing, power management,
and the effect of digital supply noise on the analog supply.
Power Supply Sequence
The ADC128S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised
to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital
supply (VD) cannot exceed the analog supply (VA) by more than 300 mV. Therefore, VAmust ramp up before or
concurrently with VD.
Power Management
The ADC128S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with
one exception. If operating in continuous conversion mode, the ADC128S102 automatically enters power-down
mode between SCLK's 16th falling edge of a conversion and SCLK's 1st falling edge of the subsequent
conversion (see Figure 2).
In continuous conversion mode, the ADC128S102 can perform multiple conversions back to back. Each
conversion requires 16 SCLK cycles and the ADC128S102 will perform conversions continuously as long as CS
is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per
unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this
technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical
specifications. The Power Consumption vs. SCLK curve in the Typical Performance Characteristics section
shows the typical power consumption of the ADC128S102. To calculate the power consumption (PC), simply
multiply the fraction of time spent in the normal mode (tN) by the normal mode power consumption (PN), and add
the fraction of time spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as
shown in Equation 3.
(3)
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ADC128S102
ADC128S102
SNAS298F –AUGUST 2005–REVISED MAY 2013
www.ti.com
Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, VD. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If
these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if
the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly
into the analog supply, causing greater performance degradation than would noise on the digital supply alone.
Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will
dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise
in the substrate that will degrade noise performance if that current is large enough. The larger the output
capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog
channel.
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies
from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load
capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 Ωseries resistor at
the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge
current of the output capacitance and improve noise performance. Since the series resistor and the load
capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.
LAYOUT AND GROUNDING
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise generated could have
significant impact upon system noise performance. To avoid performance degradation of the ADC128S102 due
to supply noise, do not use the same supply for the ADC128S102 that is used for digital logic.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes
should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be
placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal
chain that are connected to ground should be connected together with short traces and enter the analog ground
plane at a single, quiet point.
18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
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ADC128S102
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SNAS298F –AUGUST 2005–REVISED MAY 2013
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: ADC128S102
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADC128S102CIMT NRND TSSOP PW 16 92 TBD Call TI Call TI -40 to 105 128S102
CIMT
ADC128S102CIMT/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 128S102
CIMT
ADC128S102CIMTX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 128S102
CIMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADC128S102CIMTX/NOP
BTSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADC128S102CIMTX/NOP
BTSSOP PW 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 2
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