© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 3 1Publication Order Number:
KAI−04070/D
KAI-04070
2048 (H) x 2048 (V) Interline
CCD Image Sensor
Description
The KAI−04070 Image Sensor is a 4-megapixel CCD in a 4/3 inch
optical format. Based on the TRUESENSE 7.4 micron Interline
T ransfer CCD Platform, the sensor provides very high smear rejection
and up to 82 dB linear dynamic range through the use of a unique
dual-gain amplifier. A flexible readout architecture enables use of 1, 2,
or 4 outputs for full resolution readout up to 28 frames per second,
while a vertical overflow drain structure suppresses image blooming
and enables electronic shuttering for precise exposure control.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture Interline CCD, Progressive Scan
Total Number of Pixels 2128 (H) × 2112 (V)
Number of Effective Pixels 2080 (H) × 2080 (V)
Number of Active Pixels 2048 (H) × 2048 (V)
Pixel Size 7.4 mm (H) × 7.4 mm (V)
Active Image Size 15.2 mm (H) × 15.2 mm (V),
21.4 mm (Diagonal),
4/3″ Optical Format
Aspect Ratio 1:1
Number of Outputs 1, 2, or 4
Charge Capacity 44,000 electrons
Output Sensitivity 8.7 mV/e− (Low), 33 mV/e− (High)
Quantum Efficiency
Pan (−ABA, −PBA, −QBA)
R, G, B (−CBA)
R, G, B (−FBA)
52%
38%, 42%, 43%
37%, 42%, 41%
Read Noise (f = 40 MHz) 12 e− rms
Dark Current
Photodiode
VCCD 3 e−/s
145 e−/s
Dark Current Doubling Temp.
Photodiode
VCCD 7°C
9°C
Dynamic Range
High Gain Amp (40 MHz)
Dual Amp, 2×2 Bin (40 MHz) 70 dB
82 dB
Charge Transfer Efficiency 0.999999
Blooming Suppression > 1000 X
Smear −115 dB
Image Lag < 10 electrons
Maximum Pixel Clock Speed 40 MHz
Maximum Frame Rate
Quad Output
Dual Output
Single Output
28 fps
14 fps
8 fps
Package 68 Pin PGA
Cover Glass AR Coated, 2 Sides
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
Features
•Superior Smear Rejection
•Up to 82 dB Linear Dynamic Range
•Bayer Color Pattern, TRUESENSE Sparse
Color Filter Pattern, and Monochrome
Configurations
•Progressive Scan & Flexible Readout
Architecture
•High Frame Rate
•High Sensitivity − Low Noise Architecture
•Package Pin Reserved for Device
Identification
Application
•Industrial Imaging and Inspection
•Traffic
•Surveillance
www.onsemi.com
Figure 1. KAI−04070 Interline CCD
Image Sensor
See detailed ordering and shipping information on page 2 o
f
this data sheet.
ORDERING INFORMATION
KAI−04070
www.onsemi.com
2
The sensor is available with the TRUESENSE Sparse
Color Filter Pattern, a technology which provides a 2x
improvement in light sensitivity compared to a standard
color Bayer part.
The sensor shares common pin-out and electrical
configurations with a full family of Truesense Imaging
Interline Transfer CCD image sensors, allowing a single
camera design to be leveraged in support of multiple
devices.
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−04070 IMAGE SENSOR
Part Number Description Marking Code
KAI−04070−ABA−JD−BA Monochrome, Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−04070−ABA
Serial Number
KAI−04070−ABA−JD−AE Monochrome, Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
KAI−04070−ABA−JR−BA Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−04070−ABA−JR−AE Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
11KAI−04070−FBA−JD−BA Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAI−04070−FBA
Serial Number
11KAI−04070−FBA−JD−AE Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
11KAI−04070−QBA−JD−BA Gen2 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAI−04070−QBA
Serial Number
11KAI−04070−QBA−JD−AE Gen2 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
11KAI−04070−CBA−JD−BA* Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAI−04070−CBA
Serial Number
11KAI−04070−CBA−JD−AE* Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
11KAI−04070−PBA−JD−BA* Gen1 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Standard Grade KAI−04070−PBA
Serial Number
11KAI−04070−PBA−JD−AE* Gen1 Color (TRUESENSE Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
*Note recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number Description
G2−FPGA−BD−14−40−A−GEVK FPGA Board for IT−CCD Evaluation Hardware
KAI−68PIN−HEAD−BD−A−GEVB 68 Pin Imager Board for IT−CCD Evaluation Hardware
LENS−MOUNT−KIT−A−GEVK Lens Mount Kit for IT−CCD Evaluation Hardware
KAI−68PIN−N−PROBE−CARD−A−GEVB 68 Pin Probe Card (Narrow Socket)
KAI−68PIN−W−PROBE−CARD−A−GEVB 68 Pin Probe Card (Wide Socket)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
KAI−04070
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3
DEVICE DESCRIPTION
Architecture
Figure 2. Block Diagram
16 Dark
16
V1B
16 Buffer
16
16
24
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
1024 1024
1024 1024
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sa
H1Ba
H2Sa
H2Ba
VDDa
VOUTa
GND
H1Sb
H1Bb
H2Sb
H2Bb
VDDc
VOUTc
GND
VDDd
VOUTd
GND
VDDb
VOUTb
GND
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sd
H1Bd
H2Sd
H2Bd
H1Sc
H1Bc
H2Sc
H2Bc
H2SLa
OGa
H2SLc
OGc H2SLd
OGd
H2SLb
OGb
ESD ESD
SUBSUB
8241111624111 16
824111 16 82411116
24 16
DevID
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
R1a
RDab
R2ab R1b
RDab
R2ab
R1c
RDcd
R2cd R1d
RDcd
R2cd
HLOD
HLOD
1 Dummy
1 Dummy ( Last VCCD Phase = V1 à H1S)
2048H x2048V
7.4mm x 7.4mm Pixels
Dark Reference Pixels
There are 16 dark reference rows at the top and 16 dark
rows a t the bottom of the image sensor. The 24 dark columns
on the left or right side of the image sensor should be used
as a dark reference.
Under normal circumstances use only the center
22 columns o f the 24 column dark reference due to potential
light leakage.
Dummy Pixels
Within each horizontal shift register there are 12 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
Active Buffer Pixels
16 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
These pixels are light sensitive but are not tested for defects
and non-uniformities.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
ESD Protection
Adherence to the power -up and power-down sequence is
critical. Failure to follow the proper power-up and
power-down sequences may cause damage to the sensor. See
Power -Up and Power-Down Sequence section.
KAI−04070
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4
Bayer Color Filter Pattern
Figure 3. Bayer Color Filter Pattern
16Dark
16
V1B
16Buffer
16
16
24
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
1024 1024
1024 1024
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sa
H1Ba
H2Sa
H2Ba
VDDa
VOUTa
GND
H1Sb
H1Bb
H2Sb
H2Bb
VDDc
VOUTc
GND
VDDd
VOUTd
GND
VDDb
VOUTb
GND
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sd
H1Bd
H2Sd
H2Bd
H1Sc
H1Bc
H2Sc
H2Bc
H2SLa
OGa
H2SLc
OGc H2SLd
OGd
H2SLb
OGb
ESD ESD
SUB
S
UB
8241111624111 16
824111 16 82411116
24 16
DevID
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
R1a
RDab
R2ab R1b
RDab
R2ab
R1c
RDcd
R2cd R1d
RDcd
R2cd
HLOD
HLOD
1Dummy
1Dummy
2048 (H) × 2048 (V)
7.4 mm × 7.4 mm Pixels
(Last VCCD Phase = V1 → H1S)
GB
GRGB
GR
G
B
GRG
B
GR
TRUESENSE Sparse Color Filter Pattern
Figure 4. TRUESENSE Sparse Color Filter Pattern
16Dark
16
V1B
16Buffer
16
16
24
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
1024 1024
1024 1024
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sa
H1Ba
H2Sa
H2Ba
VDDa
VOUTa
GND
H1Sb
H1Bb
H2Sb
H2Bb
VDDc
VOUTc
GND
VDDd
VOUTd
GND
VDDb
VOUTb
GND
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sd
H1Bd
H2Sd
H2Bd
H1Sc
H1Bc
H2Sc
H2Bc
H2SLa
OGa
H2SLc
OGc H2SLd
OGd
H2SLb
OGb
ESD ESD
SUB
S
UB
8241111624111 16
824111 16 82411116
24 16
DevID
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
R1a
RDab
R2ab R1b
RDab
R2ab
R1c
RDcd
R2cd R1d
RDcd
R2cd
HLOD
HLOD
1Dummy
1Dummy
2048 (H) × 2048 (V)
7.4 mm × 7.4 mm Pixels
(Last VCCD Phase = V1 → H1S)
P
G
PGP
R
PR
P
B
PBP
G
PG
P
G
PGP
R
PR
P
B
PBP
G
PG
P
G
PGP
R
PR
P
B
PBP
G
PG
P
G
PGP
R
PR
P
B
PBP
G
PG
KAI−04070
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5
Physical Description
Pin Description and Device Orientation
Figure 5. Package Pin Designations − Top View
V3B
68
ESD
67
V3T
66
65
V4T
V1T
64
63
V2T
VDDc
62
61
VOUTc
GND
60
59
RDcd
Rc
58
57
OGc
H2SLc
56
55
H2Bc
H1Bc
54
53
H1Sc
H2Sc
52
51
SUB
R2cd
50
49
H1Sd
H2Sd
48
47
H2Bd
H1Bd
46
45
OGd
H2SLd
44
43
RDcd
Rd
42
41
VOUTd
GND
40
39
V2T
VDDd
38
37
V4T
V1T
36
35
DevID
V3T
1
V3B
3
4
V1B
V4B
5
6
VDDa
V2B
7
8
GND
VOUTa
9
10
Ra
RDab
11
12
H2SLa
OGa
13
14
H1Ba
H2Ba
15
16
H2Sa
H1Sa
17
18
R2ab
SUB
19
20
H2Sb
H1Sb
21
22
H1Bb
H2Bb
23
24
H2SLb
OGb
25
26
Rb
RDab
27
28
GND
VOUTb
29
30
VDDb
V2B
31
32
V1B
V4B
33
34
ESD
Pixel (1,1)
Table 4. PACKAGE PIN DESCRIPTION
Pin Name Description
1 V3B Vertical CCD Clock, Phase 3, Bottom
3 V1B Vertical CCD Clock, Phase 1, Bottom
4 V4B Vertical CCD Clock, Phase 4, Bottom
5 VDDa Output Amplifier Supply, Quadrant a
6 V2B Vertical CCD Clock, Phase 2, Bottom
7 GND Ground
8 VOUTa Video Output, Quadrant a
9 Ra Reset Gate, Standard (High) Gain, Quadrant a
10 RDab Reset Drain, Quadrants a & b
11 H2SLa Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a
12 OGa Output Gate, Quadrant a
13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a
14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a
15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a
16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a
17 R2ab Reset Gate, Low Gain, Quadrants a & b
18 SUB Substrate
19 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b
20 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b
21 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b
KAI−04070
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6
Table 4. PACKAGE PIN DESCRIPTION (continued)
Pin DescriptionName
22 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b
23 H2SLb Horizontal CCD Clock, Phase 1, Storage, Last Phase, Quadrant b
24 OGb Output Gate, Quadrant b
25 Rb Reset Gate, Standard (High) Gain, Quadrant b
26 RDab Reset Drain, Quadrants a & b
27 GND Ground
28 VOUTb Video Output, Quadrant b
29 VDDb Output Amplifier Supply, Quadrant b
30 V2B Vertical CCD Clock, Phase 2, Bottom
31 V1B Vertical CCD Clock, Phase 1, Bottom
32 V4B Vertical CCD Clock, Phase 4, Bottom
33 V3B Vertical CCD Clock, Phase 3, Bottom
34 ESD ESD Protection Disable
35 V3T Vertical CCD Clock, Phase 3, Top
36 DevID Device Identification
37 V1T Vertical CCD Clock, Phase 1, Top
38 V4T Vertical CCD Clock, Phase 4, Top
39 VDDd Output Amplifier Supply, Quadrant d
40 V2T Vertical CCD Clock, Phase 2, Top
41 GND Ground
42 VOUTd Video Output, Quadrant d
43 Rd Reset Gate, Standard (High) Gain, Quadrant d
44 RDcd Reset Drain, Quadrants c & d
45 H2SLd Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d
46 OGd Output Gate, Quadrant d
47 H1Bd Horizontal CCD Clock, Phase 1, Barrier, Quadrant d
48 H2Bd Horizontal CCD Clock, Phase 2, Barrier, Quadrant d
49 H2Sd Horizontal CCD Clock, Phase 2, Storage, Quadrant d
50 H1Sd Horizontal CCD Clock, Phase 1, Storage, Quadrant d
51 R2cd Reset Gate, Low Gain, Quadrants c & d
52 SUB Substrate
53 H2Sc Horizontal CCD Clock, Phase 2, Storage, Quadrant c
54 H1Sc Horizontal CCD Clock, Phase 1, Storage, Quadrant c
55 H1Bc Horizontal CCD Clock, Phase 1, Barrier, Quadrant c
56 H2Bc Horizontal CCD Clock, Phase 2, Barrier, Quadrant c
57 H2SLc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c
58 OGc Output Gate, Quadrant c
59 Rc Reset Gate, Standard (High) Gain, Quadrant c
60 RDcd Reset Drain, Quadrants c & d
61 GND Ground
62 VOUTc Video Output, Quadrant c
63 VDDc Output Amplifier Supply, Quadrant c
64 V2T Vertical CCD Clock, Phase 2, Top
65 V1T Vertical CCD Clock, Phase 1, Top
66 V4T Vertical CCD Clock, Phase 4, Top
67 V3T Vertical CCD Clock, Phase 3, Top
68 ESD EDS Protection Disable
1. Liked named pins are internally connected and should have a common drive signal.
KAI−04070
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7
IMAGING PERFORMANCE
Table 5. TYPICAL OPERATIONAL CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)
Description Condition Notes
Light Source Continuous Red, Green and Blue LED Illumination 1
Operation Nominal Operating Voltages and Timing
1. For monochrome sensor, only green LED used.
Specifications
Table 6. PERFORMANCE SPECIFICATIONS
Description Symbol Min. Nom. Max. Unit Sampling
Plan
Temperature
Tested at
(5C)
ALL CONFIGURATIONS
Dark Field Global Non-Uniformity DSNU − − 2.0 mVpp Die 27, 40
Bright Field Global Non-Uniformity
(Note 1) − 2.0 5.0 % rms Die 27, 40
Bright Field Global Peak to Peak
Non-Uniformity (Note 1) PRNU − 5.0 15.0 % pp Die 27, 40
Bright Field Center Non-Uniformity
(Note 1) − 1.0 2.0 % rms Die 27, 40
Maximum Photoresponse Non-Linearity
High Gain (4,000 to 20,000 electrons)
High Gain (4,000 to 40,000 electrons)
Low Gain (8,000 to 80,000 electrons)
NL_HG1
NL_HG2
NL_LG1
−
−
−
2
3
6
−
−
−
% Design
Maximum Gain Difference between
Outputs (Note 2) DG− − 10 % Design
Horizontal CCD Charge Capacity HNe − 90 − ke−Design
Vertical CCD Charge Capacity VNe − 60 − ke−Design
Photodiode Charge Capacity (Note 3) PNe − 44 − ke−Die 27, 40
Floating Diffusion Capacity − High Gain FNe_HG 40 − − ke−Die 27, 40
Floating Diffusion Capacity − Low Gain FNe_LG 160 − − ke−Die 27, 40
Horizontal CCD Charge Transfer
Efficiency HCTE 0.999995 0.999999 − Die
Vertical CCD Charge Transfer
Efficiency VCTE 0.999995 0.999999 − Die
Photodiode Dark Current IPD − 7 70 e/p/s Die 40
Vertical CCD Dark Current IVD − 140 400 e/p/s Die 40
Image Lag Lag − − 10 e−Design
Anti-Blooming Factor XAB 1,000 − − Design
Vertical Smear Smr − −115 − dB Design
Read Noise (Note 4)
High Gain
Low Gain
ne−T −12
45
− e− rms Design
Dynamic Range, Standard (Notes 4, 5) DR − 70.5 − dB Design
Dynamic Range, Extended Linear
Dynamic Range Mode (XLDR)
(Notes 4, 5)
XLDR − 82.5 − dB Design
Output Amplifier DC Offset VODC − 9.0 − V Die 27, 40
Output Amplifier Bandwidth (Note 6) f−3db − 250 − MHz Die
Output Amplifier Impedance ROUT − 127 − WDie 27, 40
Output Amplifier Sensitivity
High Gain
Low Gain
DV/DN−
−33
8.7 −
−
mV/e−Design
KAI−04070
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8
Table 6. PERFORMANCE SPECIFICATIONS (continued)
Description
Temperature
Tested at
(5C)
Sampling
Plan
UnitMax.Nom.Min.Symbol
KAI−04070−ABA AND KAI−04070−PBA AND KAI−04070−QBA CONFIGURATIONS
Peak Quantum Efficiency QEMAX − 52 − % Design
Peak Quantum Efficiency Wavelength lQE − 500 − nm Design
KAI−04070−FBA AND KAI−04070−QBA GEN2 COLOR CONFIGURATIONS
Peak Quantum Efficiency
Blue
Green
Red
QEMAX −
−
−
41
42
37
−
−
−
% Design
Peak Quantum Efficiency Wavelength
Blue
Green
Red
lQE −
−
−
460
535
610
−
−
−
nm Design
KAI−04070−CBA AND KAI−04070−PBA GEN1 COLOR CONFIGURATIONS (Note 7)
Peak Quantum Efficiency
Blue
Green
Red
QEMAX −
−
−
43
42
38
−
−
−
% Design
Peak Quantum Efficiency Wavelength
Blue
Green
Red
lQE −
−
−
470
540
620
−
−
−
nm Design
1. Per color.
2. Value is over the range of 10% to 90% of linear signal level saturation.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is 440 mV. This value is determined while operating the device in the low gain mode. VAB value assigned
is valid for both modes; high gain or low gain.
4. At 40 MHz.
5. Uses 20LOG (PNe /n
e−T).
6. Assumes 5 pF load.
7. This color filter set configuration (Gen1) is not recommended for new designs.
Linear Signal Range
Figure 6. High Gain Linear Signal Range Figure 7. Low Gain Linear Signal Range
Output of Sensor Not Verified
40,000
0
0
Output Signal (electrons)
Light or Exposure (arbitrary)
20,000
30,000
10,000
1,320
Output Signal (mV)
990
660
330
0
4,000 132
NL_HG1 Linearity Range
NL_HG2 Linearity Range
High Gain
Output of Sensor Not Verified
160,000
0
0
Output Signal (electrons)
80,000
120,000
40,000
1,600
Output Signal (mV)
1,200
800
400
0
8,000 80
NL_LG1 Linearity Range
Low Gain
Light or Exposure (arbitrary)
KAI−04070
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10
Color (TRUESENSE Sparse CFA) with Microlens (Gen2 and Gen1 CFA)
Figure 10. Color (TRUESENSE Sparse CFA) with Microlens Quantum Efficiency
Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Monochrome with Microlens
Figure 11. Monochrome with Microlens Angular Quantum Efficiency
Angle (degrees)
Relative Quantum Efficiency (%)
−40 −30 −20 −10 0 10 20 30 40
0
10
20
30
40
50
60
70
80
90
100
Vertical
Horizontal
KAI−04070
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11
Color (Bayer RGB) with Microlens
Figure 12. Color (Bayer RGB) with Microlens Angular Quantum Efficiency
Angle (degrees)
Relative Quantum Efficiency (%)
−40 −30 −20 −10 0 10 20 30 40
0
10
20
30
40
50
60
70
80
90
100
Vertical
Horizontal
Dark Current vs. Temperature
Figure 13. Dark Current vs. Temperature
2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60
Dark Current (e/s)
1000/T (K)
Photodiode
VCCD
0.01
0.10
1.00
10.00
100.00
1,000.00
10°C
20°C
30°C
40°C
50°C
60°C
70°C
KAI−04070
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12
Power-Estimated
Power -Estimated − Full Resolution
Figure 14. Power − Full Resolution
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20 25 30 35 40
Power (W)
Power (W)
HCCD Frequency (MHz)
Single
Dual (VOUTa/VOUTb)
Quad
Power -Estimated − 1/4 Resolution − 2y2 Binning
Figure 15. Power − 1/4 Resolution − Constant HCCD
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20 25 30 35 40
Power (W)
Power (W)
HCCD Frequency (MHz)
Single
Dual (VOUTa/VOUTb)
Quad
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Power -Estimated − 1/4 Resolution − 2y2 Binning using Variable HCCD XLDR
Figure 16. Power − 1/4 Resolution − Variable HCCD XLDR
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20 25 30 35 40
Power (W)
Power (W)
HCCD Frequency (MHz)
Single
Dual (VOUTa/VOUTb)
Quad
Power -Estimated − 1/4 Resolution − 2y2 Binning using Constant HCCD XLDR
Figure 17. Power − 1/4 Resolution − Constant HCCD XLDR
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20 25 30 35 40
Power (W)
Power (W)
HCCD Frequency (MHz)
Single
Dual (VOUTa/VOUTb)
Quad
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Frame Rates
Frame Rates − Full Resolution
Frame rates are for low and high gain modes of operation.
Figure 18. Frame Rates − Full Resolution
0 5 10 15 20 25 30 35 40
HCCD Frequency (MHz)
Single
Dual (VOUTa/VOUTb)
Quad
Dual (VOUTa/VOUTc)
0 0
5 5
10 10
15 15
20 20
25 25
30 30
Frame Rate (fps)
Frame Rate (fps)
Frame Rates − 1/4 Resolution − 2y2 Binning
Frame rates are for low and high gain modes of operation.
Figure 19. Frame Rates − 1/4 Resolution − Constant HCCD
0 5 10 15 20 25 30 35 40
HCCD Frequency (MHz)
0 0
5 5
10 10
15 15
40 40
45 45
50 50
Single
Dual (VOUTa/VOUTb)
Quad
Dual (VOUTa/VOUTc)
Frame Rate (fps)
Frame Rate (fps)
20 20
25 25
30 30
35 35
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Frame Rates − 1/4 Resolution − 2y2 Binning using Variable HCCD XLDR
Frame rates for variable HCCD modes of operation.
Figure 20. Frame Rates − 1/4 Resolution − Variable HCCD XLDR
0 5 10 15 20 25 30 35 40
HCCD Frequency (MHz)
0 0
5 5
10 10
15 15
20 20
25 25
Single
Dual (VOUTa/VOUTb)
Quad
Dual (VOUTa/VOUTc)
30 30
35 35
40 40
Frame Rate (fps)
Frame Rate (fps)
Frame Rates − 1/4 Resolution − 2y2 Binning using Constant HCCD XLDR
Frame rates for a constant HCCD mode of operation.
Figure 21. Frame Rates − 1/4 Resolution − Constant HCCD XLDR
0 5 10 15 20 25 30 35 40
HCCD Frequency (MHz)
0 0
5 5
10 10
15 15
20 20
25 25
Single
Dual (VOUTa/VOUTb)
Quad
Dual (VOUTa/VOUTc)
30 30
35 35
40 40
Frame Rate (fps)
Frame Rate (fps)
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DEFECT DEFINITIONS
Table 7. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C
Description Condition Notes
Operational Mode One Output, using VOUTa, Continuous Readout
HCCD Clock Frequency 20 MHz
Pixels per Line 2,140
Lines per Frame 2,112
Line Time 115.0 ms
Frame Time 242.9 ms
Photodiode Integration Time (PD_Tint) PD_Tint = Frame Time = 242.9 ms, No Electronic Shutter Used
Temperature 40°C
Light Source Continuous Red, Green and Blue LED Illumination 1
Operation Nominal Operating Voltages and Timing
1. For monochrome sensor, only the green LED is used.
Table 8. DEFECT DEFINITIONS FOR TESTING AT 405C
Description Definition Standard Grade Notes
Major Dark Field Defective Bright Pixel Defect ≥ 83 mV 40 1
Major Bright Field Defective Pixel −12% ≥ Defect ≥ 12% 40 1
Minor Dark Field Defective Bright Pixel Defect ≥ 41 mV 400
Cluster Defect A group of 2 to 10 contiguous major defective pixels,
but no more than 2 adjacent defect horizontally. 8 2
Column Defect A group of more than 10 contiguous major defective
pixels along a single column. 0 2
1. For the color devices (KAI−04070−CBA and KAI−04070−PBA), a bright field defective pixel deviates by 12% with respect to pixels of the
same color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
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Table 9. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C
Description Condition Notes
Operational Mode One Output, Using VOUTa, Continuous Readout
HCCD Clock Frequency 20 MHz
Pixels per Line 2,140
Lines per Frame 2,112
Line Time 115 ms
Frame Time 242.9 ms
Photodiode Integration Time (PD_Tint) PD_Tint = Frame Time = 242.9 ms, No Electronic Shutter Used
Temperature 27°C
Light Source Continuous Red, Green and Blue LED Illumination 1
Operation Nominal Operating Voltages and Timing
1. For monochrome sensor, only the green LED is used.
Table 10. DEFECT DEFINITIONS FOR TESTING AT 405C
Description Definition Standard Grade Notes
Major Dark Field Defective Bright Pixel Defect ≥ 27 mV 40 1
Major Bright Field Defective Pixel −12% ≥ Defect ≥ 12% 40 1
Cluster Defect A group of 2 to 10 contiguous major defective pixels,
but no more than 2 adjacent defect horizontally. 8 2
Column Defect A group of more than 10 contiguous major defective
pixels along a single column. 0 2
1. For the color devices (KAI−04070−CBA and KAI−04070−PBA), a bright field defective pixel deviates by 12% with respect to pixels of the
same color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps. See
Figure 22 for the location of pixel 1, 1.
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TEST DEFINITIONS
Test Regions of Interest
Image Area ROI: Pixel (1, 1) to Pixel (2080, 2080)
Active Area ROI: Pixel (17, 17) to Pixel (2064, 2064)
Center ROI: Pixel (991, 991) to Pixel (1090, 1090)
Only the Active Area ROI pixels are used for performance
and defect tests.
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 22 for a pictorial representation of the regions of
interest.
Figure 22. Regions of Interest
VOUTa
1, 1
17,
Pixel
Pixel
16 Dark Rows
24 Dark Columns
16 Buffer Rows
16 Buffer Columns
16 Buffer Columns
24 Dark Columns
16 Dark Rows
16 Buffer Rows
17
2048 × 2048
Active Pixels
Tests
Dark Field Global Non-Uniformity
This test is performed under dark field conditions.
The sensor is partitioned into 256 sub regions of interest,
each o f which is 128 by 128 pixels in size. The average signal
level of each of the 256 sub regions of interest is calculated.
The signal level of each of the sub regions of interest is
calculated using the following formula:
Signal of ROI[i] +(ROI Average in Counts *
Units : mVpp (millivolts Peak to Peak)
*Horizontal Overclock Average in Counts) @
@mV per Count
where i = 1 to 256. During this calculation on the 256 sub
regions of interest, the maximum and minimum signal levels
are found. The dark field global uniformity is then calculated
as the maximum signal found minus the minimum signal
level found.
Global Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 92 4 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 1,320 mV. Global non-uniformity
is defined as
Global Non−Uniformity +100 @ǒActive Area Standard Deviation
Active Area Signal Ǔ
Active Area Signal = Active Area Average − Dark Column Average
Units : % rms
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Global Peak to Peak Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 92 4 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity o f the sensor is 1,320 mV. The sensor is partitioned
into 256 sub regions of interest, each of which is 128 by 128
pixels i n size. The average signal level of each of the 256 sub
regions of interest (ROI) is calculated. The signal level of
each of the sub regions of interest is calculated using the
following formula:
Signal of ROI[i] +(ROI Average in Counts *
*Horizontal Overclock Average in Counts) @
@mV per Count
Where i = 1 to 256. During this calculation on the 144 sub
regions of interest, the maximum and minimum signal levels
are found. The global peak to peak uniformity is then
calculated as:
Global Uniformity +100 @ǒMax. Signal *Min. Signal
Active Area Signal Ǔ
Units : % pp
Center Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 92 4 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 1,320 mV. Defects are excluded for
the calculation of this test. This test is performed on the
center 100 by 100 pixels of the sensor. Center uniformity is
defined as:
Center ROI Uniformity +100 @ǒCenter ROI Standard Deviation
Center ROI Signal Ǔ
Center ROI Signal = Center ROI Average − Dark Colum Average
Units : % rms
Dark Field Defect Test
This test is performed under dark field conditions.
The sensor is partitioned into 256 sub regions of interest,
each of which is 128 by 128 pixels in size. In each region of
interest, the median value of all pixels is found. For each
region of interest, a pixel is marked defective if it is greater
than or equal to the median value of that region of interest
plus the defect threshold specified in the “Detect
Definitions” section.
Bright Field Defect Test
This test is performed with the imager illuminated to
a level such that the output is at approximately 924 mV.
Prior to this test being performed the substrate voltage has
been set such that the charge capacity of the sensor is
1,320 mV. The average signal level of all active pixels is
found. The bright and dark thresholds are set as:
Dark Defect Threshold = Active Area Signal @Threshold
Bright Defect Threshold = Active Area Signal @Threshold
The sensor is then partitioned into 256 sub regions of
interest, each of which is 128 by 128 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
•Example for major bright field defective pixels:
•Average value of all active pixels is found to be 924 mV
•Dark defect threshold: 924 mV ⋅ 12% = 111 mV
•Bright defect threshold: 924 mV ⋅ 12% = 111 mV
•Region of interest #1 selected. This region of interest is
pixels 17, 17 to pixels 144, 144
♦Median of this region of interest is found to be
920 mV
♦Any pixel in this region of interest that is
≤ (920 − 111 mV) 809 mV in intensity will be
marked defective
♦Any pixel in this region of interest that is
≥ (920 + 111 mV) 1,031 mV in intensity will be
marked defective
•All remaining 144 sub regions of interest are analyzed
for defective pixels in the same manner
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OPERATION
Absolute Maximum Ratings
Absolute maximum rating is defined as a level or
condition that should not be exceeded at any time per the
description. If the level or the condition is exceeded,
the device will be degraded and may be damaged. Operation
at these values will reduce MTTF.
Table 11. ABSOLUTE MAXIMUM RATINGS
Description Symbol Minimum Maximum Unit Notes
Operating Temperature TOP −50 70 °C 1
Humidity RH 5 90 % 2
Output Bias Current IOUT − 60 mA 3
Off-Chip Load CL− 10 pF
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
Table 12. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Description Minimum Maximum Unit Notes
VDDa, VOUTa−0.4 17.5 V 1
RDa−0.4 15.5 V 1
V1B, V1T ESD − 0.4 ESD + 24.0 V
V2B, V2T, V3B, V3T, V4B, V4T ESD − 0.4 ESD + 14.0 V
H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, R1a, R2a, OGaESD − 0.4 ESD + 14.0 V 1
ESD −10.0 0.0 V
SUB −0.4 40.0 V 2
1. a denotes a, b, c or d.
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions
KAI−08050 Compatibility
The KAI−04070 is pin-for-pin compatible with a camera
designed for the KAI−08050 image sensor with the
following accommodations:
•To operate in accordance with a system designed for
KAI−08050, the target substrate voltage should be set
to be 2.0V higher than the value recorded on the
KAI−04070 shipping container. This setting will cause
the charge capacity to be limited to 20 ke− (or 660 mV)
•On the KAI−04070, pins 17 (R2ab) and 51 (R2cd)
should be left floating per the KAI−08050 Device
Performance Specification
•The KAI−04070 will operate in only the high gain
mode (33 mV/e−)
•All timing and voltages are taken from the KAI−08050
specification sheet
•The number of horizontal and vertical CCD clock
cycles is reduced as appropriate
In addition, if the intent is to operate the KAI−04070
image sensor in a camera designed for the KAI−08050
sensor that has been modified to accept and process the full
40,000 e− (1,320 mV) output, the following changes to the
RD bias must be made:
Table 13.
Pins Names KAI−08050 KAI−04070
10, 26, 44, 60 RDa, RDb, RDc, RDd 12.0 V per the Specification Increase to 12.6 V
To make use of the low or dual gains modes the
KAI−04070 voltages and timing specifications must be
used.
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Reset Pin, Low Gain (R2ab and R2cd)
The R2ab and R2bc (pins 17 and 51) each have an internal
circuit to bias the pins to 4.3 V. This feature assures the
device is set to operate in the high gain mode when pins 17
and 51 are not connected in the application to a clock driver
(for KAI−08050 compatibility). Typical capacitor coupled
drivers will not drive this structure.
Figure 23. Equivalent Circuit for Reset Gate, Low Gain (R2ab and R2cd)
GND
VDD
(+15 V) R2
4.3 V
VDD
(+15 V)
27 kW
20 kW
68 kW
GND
27 kW
20 kW
68 kW
Power-Up and Power-Down Sequence
Adherence to the power -up and power-down sequence is
critical. Failure to follow the proper power-up and
power -down sequences may cause damage to the sensor.
Figure 24. Power-Up and Power-Down Sequence
VDD
SUB
ESD VCCD
Low HCCD
Low
Time
V+
V−
Do Not Pulse the Electronic Shutter until ESD is Stable
Activate All Other Biases when ESD is Stable and Sub is above 3 V
1. Activate all other biases when ESD is stable and SUB is above 3 V.
2. Do not pulse the electronic shutter until ESD is stable.
3. VDD cannot be +15 V when SUB is 0 V.
4. The image sensor can be protected from an accidental improper ESD voltage by current limiting the SUB current to less than 10 mA. SUB
and VDD must always be greater than GND. ESD must always be less than GND. Placing diodes between SUB, VDD, ESD and groun
d
will protect the sensor from accidental overshoots of SUB, VDD and ESD during power on and power off. See the figure below.
Notes:
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The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage.
Figure 25. VCCD Clock Waveform
All VCCD Clock Absolute
Maximum Overshoot of 0.4 V
0.0 V
ESD
ESD − 0.4 V
Example of external diode protection for SUB, VDD and ESD. a denotes a, b, c or d.
Figure 26. Example of External Diode Protection
ESD
GND
VDD
a
SUB
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DC Bias Operating Conditions
Table 14. DC BIAS OPERATING CONDITIONS
Description Pins Symbol Min. Nom. Max. Unit Max. DC
Current Notes
Reset Drain RDaRD 12.4 12.6 12.8 V 10 mA1, 9
Output Gate OGaOG −2.2 −2.0 −1.8 V10 mA1
Output Amplifier Supply VDDaVDD 14.5 15.0 15.5 V 11.0 mA 1, 2
Ground GND GND 0.0 0.0 0.0 V −1.0 mA
Substrate SUB VSUB 5.0 VAB VDD V50 mA3, 8
ESD Protection Disable ESD ESD −9.2 −9.0 Vx_L V 50 mA6, 7, 10
Output Bias Current VOUTaIOUT −3.0 −5.0 −10.0 mA − 1, 4, 5
1. a denotes a, b, c or d.
2. The maximum DC current is for one output. IDD = IOUT + ISS. See Figure 27.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is the nominal PNe (see Specifications).
4. An output load sink must be applied to each VOUT pin to activate each output amplifier.
5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise.
6. Adherence to the power-up and power-down sequence is critical. See Sequence section.
7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V.
8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
9. 12.0 V may be used if the total output signal desired is 20,000 e− or less.
10.Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application.
Figure 27. Output Amplifier
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Floating
Diffusion
ISS
IDD
IOUT
VOUTa
VDDa
Ra
RDa
HCCD
OGa
R2a
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AC Operating Conditions
Table 15. CLOCK LEVELS
Description Pins
(Note 1) Symbol Level Min. Nom. Max. Unit
Vertical CCD Clock, Phase 1 V1B, V1T V1_L Low −8.2 −8.0 −7.8 V
V1_M Mid −0.2 0.0 0.2
V1_H High 11.5 12.0 12.5
Vertical CCD Clock, Phase 2 V2B, V2T V2_L Low −8.2 −8.0 −7.8 V
V2_H High −0.2 0.0 0.2
Vertical CCD Clock, Phase 3 V3B, V3T V3_L Low −8.2 −8.0 −7.8 V
V3_H High −0.2 0.0 0.2
Vertical CCD Clock, Phase 4 V4B, V4T V4_L Low −8.2 −8.0 −7.8 V
V4_H High −0.2 0.0 0.2
Horizontal CCD Clock, Phase 1 Storage H1SaH1S_L Low −5.2 −4.0 −3.8 V
H1S_A Amplitude (Note 3) 3.8 4.0 5.2
Horizontal CCD Clock, Phase 1 Barrier H1BaH1B_L Low −5.2 −4.0 −3.8 V
H1B_A Amplitude (Note 3) 3.8 4.0 5.2
Horizontal CCD Clock, Phase 2 Storage H2SaH2S_L Low −5.2 −4.0 −3.8 V
H2S_A Amplitude (Note 3) 3.8 4.0 5.2
Horizontal CCD Clock, Phase 2 Barrier H2BaH2B_L Low −5.2 −4.0 −3.8 V
H2B_A Amplitude (Note 3) 3.8 4.0 5.2
Horizontal CCD Clock, Last Phase
(Note 2) H2SLaH2SL_L Low −5.2 −5.0 −4.8 V
H2SL_A Amplitude (Note 3) 4.8 5.0 5.2
Reset Gate R1aR_L Low −3.2 −3.0 −2.8 V
R_A Amplitude 6.0 − 6.4
Reset Gate 2 R2aR2_L Low −2.0 −1.8 −1.6 V
R2_A Amplitude 6.0 − 6.4
Electronic Shutter (Note 4) SUB VES High 29.0 30.0 40.0 V
1. a denotes a, b, c or d.
2. Use separate clock driver for improved speed performance.
3. The horizontal clock amplitude should be set such that the high level reaches 0.0 V. Examples:
a. If the minimum horizontal low voltage of −5.2 V is used, then a 5.2 V amplitude clock is required for a clock swing of −5.2 V to 0.0 V.
b. If the maximum horizontal low voltage of −3.8 V is used, then a 3.8 V amplitude clock is required for a clock swing of −3.8 V to 0.0 V.
4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock
are referenced to ground.
Figure 28. DC Bias and AC Clock Applied to the SUB Pin
VSUB
VES
GND GND
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Capacitance
Table 16. CAPACITANCE
V1B V2B V3B V4B V1T V2T V3T V4T GND All Pins Unit
V1B X 4 3 3 2 2 2 1 10 25 nF
V2B X X 1 3 1 1 1 1 10 20 nF
V3B X X X 5 2 1 2 1 6 23 nF
V4B X X X X 2 1 1 1 13 23 nF
V1T X X X X X 2 3 2 20 29 nF
V2T X X X X X X 5 3 4 21 nF
V3T X X X X X X X 2 9 24 nF
V4T X X X X X X X X 3 20 nF
VSUB 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 2.8 2.8 nF
H2S H1B H2B GND All Pins Unit
H1S 32 29 29 120 210 pF
H2S X 16 21 170 240 pF
H1B X X 7 155 210 pF
H2B X X X 165 235 pF
1. Tables show typical cross capacitance between pins of the device.
2. Capacitance is total for all like pins.
3. Capacitance values are estimated.
Device Identification
The device identification pin (DevID) may be used to determine which Truesense Imaging 7.4 micron pixel interline CCD
sensor is being used.
Table 17. DEVICE IDENTIFICATION
Description Pins Symbol Min. Nom. Max. Unit Max. DC
Current Notes
Device Identification DevID DevID 64,000 74,000 84,000 W50 mA1, 2, 3
1. Nominal value subject to verification and/or change during release of preliminary specifications.
2. If the Device Identification is not used, it may be left disconnected.
3. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent
localized heating of the sensor due to current flow through the R_DeviceID resistor.
Recommended Circuit
Note that V1 must be a different value than V2.
Figure 29. Device Identification Recommended Circuit
ADC
R_external
V1 V2
DevID
GND
KAI−04070
R_DeviceID
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TIMING
Requirements and Characteristics
Table 18. REQUIREMENTS AND CHARACTERISTICS
Description Symbol Min. Nom. Max. Unit Notes
Photodiode Transfer tPD 1.0 − − ms
VCCD Leading Pedestal t3P 4.0 − − ms
VCCD Trailing Pedestal t3D 4.0 − − ms
VCCD Transfer tV2.0 − − ms
VCCD Clock Cross-Over VVCR 75 − 100 % 1
VCCD Rise, Fall Times tVR, tVF 5 − 10 % 1, 2
HCCD Delay tHS 2.0 − − ms
HCCD Transfer te25.0 − − ns
Shutter Transfer tSUB 2.0 − − ms
Shutter Delay tHD 2.0 − − ms
Reset Pulse tR2.5 − − ns
Reset − Video Delay tRV − 2.2 − ns
H2SL − Video Delay tHV − 3.1 − ns
Line Time tLINE 34.9 − − msDual HCCD Readout
61.5 − − msSingle HCCD Readout
Frame Time tFRAME 36.9 − − ms Quad HCCD Readout
73.8 − − ms Dual HCCD Readout
129.9 − − ms Single HCCD Readout
Line Time (XLDR Bin 2×2) tLINE 69.8 − − msDual HCCD Readout
123.0 − − msSingle HCCD Readout
Frame Time (XLDR Bin 2×2)
Constant HCCD Timing tFRAME 36.9 − − ms Quad HCCD Readout
73.7 − − ms Dual HCCD Readout
129.9 − − ms Single HCCD Readout
Frame Time (XLDR Bin 2×2)
Variable HCCD Timing tFRAME 29.8 − − ms Quad HCCD Readout
59.5 − − ms Dual HCCD Readout
101.7 − − ms Single HCCD Readout
1. Refer to Figure 47: VCCD Clock Rise Time, Fall Time, and Edge Alignment.
2. Relative to the VCCD Transfer pulse width, tV.
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Timing Flow Charts
In the timing flow charts the number of HCCD clock cycles per row, NH, and the number of VCCD clock cycles per frame,
NV, are shown in the following table.
Table 19. VALUES FOR NH AND NV WHEN OPERATING THE SENSOR IN THE VARIOUS MODES OF RESOLUTION
Full Resolution 1/4 Resolution XLDR
NV NH NV NH NV NH
Quad 1056 1076 528 538 528 538
Dual VOUTa, VOUTc 1056 2152 528 1076 528 1076
Dual VOUTa, VOUTb 2112 1076 1056 538 1056 538
Single VOUTa 2112 2152 1056 1076 1056 1076
1. The time to read out one line tLINE = Line Timing + NH / (Pixel Frequency).
2. The time to read out one frame tFRAME = NV ⋅ tLINE + Frame Timing.
3. Line Timing: See Table 21: Line Timing.
4. Frame Timing: See Table 20: Frame Timing.
5. XLDR: eXtended Linear Dynamic Range.
No Electronic Shutter
In this case the photodiode exposure time is equal to the time to read out an image. This flow chart applies to both full and
1/4 resolution modes.
Figure 30. Timing Flow when Electronic Shutter is Not Used
Frame Timing
(see Table 20)
Line Timing
(see Table 21)
Pixel Timing
(see Table 22)
Repeat NH
Times
Repeat NV
Times
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Using the Electronic Shutter
This flow chart applies to both the full and 1/4 resolution
modes. The exposure time begins on the falling edge of the
electronic shutter pulse on the SUB pin. The exposure time
ends on the falling edge of the photodiode transfer (tPD) of
the V1T and V1B pins. The electronic shutter timing is
shown in Figure 38.
Figure 31. Timing Flow Chart using the Electronic Shutter for Exposure Control
Frame Timing
(see Table 20)
Line Timing
(see Table 21)
Pixel Timing
(see Table 22)
Repeat NH
Times
Repeat NV−NEXP
Times
Electronic
Shutter Timing
Line Timing
(see Table 21)
Pixel Timing
(see Table 22)
Repeat NH
Times
Repeat NEXP
Times
NOTE: NEXP: Exposure time in increments of number of lines.
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Timing Tables
Frame Timing
This timing table is for transferring charge from the photodiodes to the VCCD. See Figures 32 and 33 for frame timing
diagrams.
Table 20. FRAME TIMING
Device
Pin
Full Resolution, High Gain or Low Gain 1/4 Resolution, High Gain or Low Gain 1/4 Resolution XLDR
Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb Single
VOUTa Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb Single
VOUTa Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb Single
VOUTa
V1T F1T F1B F1T F1B F1T F1B
V2T F2T F4B F2T F4B F2T F4B
V3T F3T F3B F3T F3B F3T F3B
V4T F4T F2B F4T F2B F4T F2B
V1B F1B F1B F1B
V2B F2B F2B F2B
V3B F3B F3B F3B
V4B F4B F4B F4B
H1Sa P1 P1Q P1XL
H1Ba P1 P1Q P1XL
H2Sa P2 P2Q P2XL
H2Ba P2 P2Q P2XL
Ra RHG/RLG RHGQ/RLGQ RXL
H1Sb P1 P1Q P1XL
H1Bb P1 P2 P1 P2 P1Q P2Q P1Q P2Q P1XL P2XL P1XL P2XL
H2Sb P2 P2Q P2XL
H2Bb P2 P1 P2 P1 P2Q P1Q P2Q P1Q P2XL P1XL P2XL P1XL
Rb RHG/
RLG (Note 1) RHG/
RLG (Note 1) RHGQ/
RLGQ (Note 1) RHGQ/
RLGQ (Note 1) RXL (Note 1) RXL (Note 1)
R2ab R2HG/R2LG R2HGQ/R2LGQ R2XL
H1Sc P1 (Note 1) P1Q (Note 1) P1XL (Note 1)
H1Bc P1 (Note 1) P1Q (Note 1) P1XL (Note 1)
H2Sc P2 (Note 1) P2Q (Note 1) P2XL (Note 1)
H2Bc P2 (Note 1) P2Q (Note 1) P2XL (Note 1)
Rc RHG/RLG (Note 1) RHGQ/RLGQ (Note 1) RXL (Note 1)
H1Sd P1 (Note 1) P1Q (Note 1) P1XL (Note 1)
H1Bd P1 P2 (Note 1) P1Q P2Q (Note 1) P1XL P2XL (Note 1)
H2Sd P2 (Note 1) P2Q (Note 1) P2XL (Note 1)
H2Bd P2 P1 (Note 1) P2Q P1Q (Note 1) P2XL P1XL (Note 1)
Rd RHG/
RLG (Note 1) (Note 1) RHGQ/
RLGQ (Note 1) (Note 1) RXL (Note 1) (Note 1)
R2cd R2HG/R2LG (Note 1) R2HGQ/R2LGQ (Note 1) R2XL (Note 1)
SHP
(Note 2) SHP1 SHPQ (Note 4)
SHD
(Note 2) SHD1 SHDQ (Note 5)
1. This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interline Transfer
CCD family of products.
2. SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
3. This note intentionally left empty.
4. Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
5. Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
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Line Timing
This timing is for transferring one line of charge from the VCCD to the HCCD. See Figure 34, Figure 35, Figure 36 and
Figure 37 for line timing diagrams.
Table 21. LINE TIMING
Device
Pin
Full Resolution, High Gain or Low Gain 1/4 Resolution, High Gain or Low Gain 1/4 Resolution XLDR
Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb Single
VOUTa Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb Single
VOUTa Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb Single
VOUTa
V1T L1T L1B 2 ×L1T 2 ×L1B 2 ×L1T 2 ×L1B
V2T L2T L4B 2 ×L2T 2 ×L4B 2 ×L2T 2 ×L4B
V3T L3T L3B 2 ×L3T 2 ×L3B 2 ×L3T 2 ×L3B
V4T L4T L2B 2 ×L4T 2 ×L2B 2 ×L4T 2 ×L2B
V1B L1B 2 ×L1B 2 ×L1B
V2B L2B 2 ×L2B 2 ×L2B
V3B L3B 2 ×L3B 2 ×L3B
V4B L4B 2 ×L4B 2 ×L4B
H1Sa P1L P1LQ P1XL
H1Ba P1L P1LQ P1XL
H2Sa P2L P2LQ P2XL
H2Ba P2L P2LQ P2XL
Ra RHG/RLG RHGQ/RLGQ RXL
H1Sb P1L P1LQ P1XL
H1Bb P1L P2L P1L P2L P1LQ P2LQ P1LQ P2LQ P1XL P2XL P1XL P2XL
H2Sb P2L P2LQ P2XL
H2Bb P2L P1L P2L P1L P2LQ P1LQ P2LQ P1LQ P2XL P1XL P2XL P1XL
Rb RHG/
RLG (Note 1) RHG/
RLG (Note 1) RHGQ/
RLGQ (Note 1) RHGQ/
RLGQ (Note 1) RXL (Note 1) RXL (Note 1)
R2ab R2HG/R2LG R2HGQ/R2LGQ R2XL
H1Sc P1L (Note 1) P1LQ (Note 1) P1XL (Note 1)
H1Bc P1L (Note 1) P1LQ (Note 1) P1XL (Note 1)
H2Sc P2L (Note 1) P2LQ (Note 1) P2XL (Note 1)
H2Bc P2L (Note 1) P2LQ (Note 1) P2XL (Note 1)
Rc RHG/RLG (Note 1) RHGQ/RLGQ (Note 1) RXL (Note 1)
H1Sd P1L (Note 1) P1LQ (Note 1) P1XL (Note 1)
H1Bd P1L P2L (Note 1) P1LQ P2LQ (Note 1) P1XL P2XL (Note 1)
H2Sd P2L (Note 1) P2LQ (Note 1) P2XL (Note 1)
H2Bd P2L P1L (Note 1) P2LQ P1LQ (Note 1) P2XL P1XL (Note 1)
Rd RHG/
RLG (Note 1) (Note 1) RHGQ/
RLGQ (Note 1) (Note 1) RXL (Note 1) (Note 1)
R2cd R2HG/R2LG (Note 1) R2HGQ/R2LGQ (Note 1) R2XL (Note 1)
SHP
(Note 2) SHP1 SHPQ (Note 4)
SHD
(Note 2) SHD1 SHDQ (Note 5)
1. This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interline Transfer
CCD family of products.
2. SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
3. The notation 2× L1B means repeat the L1B timing twice for every line. This sums two rows into the HCCD.
4. Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
5. Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
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Pixel Timing
This timing is for transferring one pixel from the HCCD to the output amplifier.
Table 22. PIXEL TIMING
Device
Pin
Full Resolution, High Gain or Low Gain 1/4 Resolution, High Gain or Low Gain 1/4 Resolution XLDR
Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb Single
VOUTa Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb Single
VOUTa Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb Single
VOUTa
V1T −8 V −8 V −8 V
V2T −8 V −8 V −8 V
V3T 0V 0V 0V
V4T 0V 0V 0V
V1B −8 V −8 V −8 V
V2B 0V 0V 0V
V3B 0V 0V 0V
V4B −8 V −8 V −8 V
H1Sa P1 P1Q P1XL
H1Ba P1 P1Q P1XL
H2Sa P2 P2Q P2XL
H2Ba P2 P2Q P2XL
Ra RHG/RLG RHGQ/RLGQ RXL
H1Sb P1 P1Q P1XL
H1Bb P1 P2 P1 P2 P1Q P2Q P1Q P2Q P1XL P2XL P1XL P2XL
H2Sb P2 P2Q P2XL
H2Bb P2 P1 P2 P1 P2Q P1Q P2Q P1Q P2XL P1XL P2XL P1XL
Rb RHG/
RLG (Note 1) RHG/
RLG (Note 1) RHGQ/
RLGQ (Note 1) RHGQ/
RLGQ (Note 1) RXL (Note 1) RXL (Note 1)
R2ab R2HG/R2LG R2HGQ/R2LGQ R2XL
H1Sc P1 (Note 1) P1Q (Note 1) P1XL (Note 1)
H1Bc P1 (Note 1) P1Q (Note 1) P1XL (Note 1)
H2Sc P2 (Note 1) P2Q (Note 1) P2XL (Note 1)
H2Bc P2 (Note 1) P2Q (Note 1) P2XL (Note 1)
Rc RHG/RLG (Note 1) RHGQ/RLGQ (Note 1) RXL (Note 1)
H1Sd P1 (Note 1) P1Q (Note 1) P1XL (Note 1)
H1Bd P1 P2 (Note 1) P1Q P2Q (Note 1) P1XL P2XL (Note 1)
H2Sd P2 (Note 1) P2Q (Note 1) P2XL (Note 1)
H2Bd P2 P1 (Note 1) P2Q P1Q (Note 1) P2XL P1XL (Note 1)
Rd RHG/
RLG (Note 1) (Note 1) RHGQ/
RLGQ (Note 1) (Note 1) RXL (Note 1) (Note 1)
R2cd R2HG/R2LG (Note 1) R2HGQ/R2LGQ (Note 1) R2XL (Note 1)
SHP
(Note 2) SHP1 SHPQ (Note 4)
SHD
(Note 2) SHD1 SHDQ (Note 5)
1. This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interline Transfer
CCD family of products.
2. SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
3. This note intentionally left empty.
4. Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
5. Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
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Timing Diagrams
The charge in the photodiodes its transfer to the VCCD on
the rising edge of the +12 V pulse and is completed by the
falling edge of the +12 V pulsed on F1T and F1B. During the
time period when F1T and F1B are at +12 V (tPD)
anti-blooming protection is disabled. The photodiode
integration time ends on the falling edge of the +12 V pulse.
Frame Timing − Quadrant and Dual V OUTa/VOUTc Readout Modes
Figure 32. Frame Timing Diagram Quadrant and Dual VOUTa/VOUTc Readout Modes
F1T
F2T
F3T
F4T
F1B
F2B
F3B
F4B
+12 V
0 V
−8 V
+12 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
Frame Timing
Device
Pin Pattern t3P
tV
2
tV
2
tV
2tV
2tV
2tV
2tV
2
t3D
tPD
Frame Timing Line TimingPixel Timing
t3P
tV
2
tV
2
tV
2tV
2tV
2tV
2tV
2
t3D
tPD
NOTE: See Table 20 for pin assignments.
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Frame Timing − Single and Dual VOUTa/VOUTb Readout Modes
Figure 33. Frame Timing Diagram Single and Dual VOUTa/VOUTb Readout Modes
F1B
F4B
F3B
F2B
F1B
F2B
F3B
F4B
+12 V
0 V
−8 V
+12 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
Frame Timing
Device
Pin Pattern t3P
tV
2
tV
2
tV
2tV
2tV
2tV
2tV
2
t3D
tPD
Frame Timing Line TimingPixel Timing
t3P
tV
2
tV
2
tV
2tV
2tV
2tV
2tV
2
t3D
tPD
NOTE: See Table 20 for pin assignments.
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Line Timing −Full Resolution − Quadrant and Dual VOUTa/VOUTc Readout Modes
Figure 34. Line Timing Diagram − Full Resolution − Quadrant and Dual VOUTa/VOUTc Readout Modes
Device
Pin Pattern
Frame or Pixel Timing Line Timing Pixel Timing
tV
2
NOTE: See Table 21 for pin assignments.
L1T
L2T
L3T
L4T
L1B
L2B
L3B
L4B
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
P1L
0 V
−4 V
0 V
−4 V
P2L
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
Hor izont al
Cl ocks
te
2
tV
2tV
2tV
2tV
2tV
2tV
2tV
2
Time Duration is 4 ⋅ tV
Line Timing
tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2
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Line Timing −Full Resolution − Single and Dual VOUTa/VOUTb Readout Modes
Figure 35. Line Timing Diagram − Full Resolution − Single and Dual VOUTa/VOUTb Readout Modes
Device
Pin Pattern
Frame or Pixel Timing Line Timing Pixel Timing
tV
2
NOTE: See Table 21 for pin assignments.
L1B
L4B
L3B
L2B
L1B
L2B
L3B
L4B
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
P1L
0 V
−4 V
0 V
−4 V
P2L
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
Hor izont al
Cl ocks
te
2
tV
2tV
2tV
2tV
2tV
2tV
2tV
2
Time Duration is 4 ⋅ tV
Line Timing
tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2
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Line Timing − Low Gain, High Gain and XLDR 1/4 Resolution − Quadrant and Dual VOUTa/VOUTc Readout Modes
Figure 36. Line Timing Diagram − 1/4 Resolution − Quadrant and Dual VOUTa/VOUTc Readout Modes
Device
Pin Pattern
Frame or Pixel Timing 1/4 Resolution Line Timing Pixel Timing
tV
2
NOTE: See Table 21 for pin assignments.
te
2
Time Duration is 8 ⋅ tV
L1T
L2T
L3T
L4T
L1B
L2B
L3B
L4B
P1L
P2L
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−4 V
0 V
−4 V
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
Hor izont al
Cl ocks
tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2
1/4 Resolution Line Timing
tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2
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Line Timing − Low Gain, High Gain and XLDR 1/4 Resolution − Single and Dual VOUTa/VOUTb Readout Modes
Figure 37. Line Timing Diagram − 1/4 Resolution − Single and Dual VOUTa/VOUTb Readout Modes
Device
Pin Pattern
Frame or Pixel Timing 1/4 Resolution Line Timing Pixel Timing
tV
2
NOTE: See Table 21 for pin assignments.
te
2
Time Duration is 8 ⋅ tV
L1B
L4B
L3B
L2B
L1B
L2B
L3B
L4B
P1L
P2L
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−8 V
0 V
−4 V
0 V
−4 V
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
Hor izont al
Cl ocks
tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2
1/4 Resolution Line Timing
tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2tV
2
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Electronic Shutter Timing Diagrams
The electronic shutter pulse can be inserted at the end of
any line of the HCCD timing. The HCCD should be empty
when the electronic shutter is pulsed. A recommended
position for the electronic shutter is just after the last pixel
is read out of a line. The VCCD clocks should not resume
until at least tV/2 after the electronic shutter pulse has
finished. The HCCD clocks can be run during the electronic
shutter pulse as long as the HCCD does not contain valid
image data.
For short exposures less than one line time, the electronic
shutter pulse can appear inside the frame timing. Any
electronic shutter pulse transition should be tV/2 away from
any VCCD clock transition.
Figure 38. Electronic Shutter Timing
tV
2
SUB
VAB
VES
0 V
−8 V
VCCD Clock
tSUB tV
2
Figure 39. Frame/Electrical Shutter Timing
tINT
V1T/V1B
SUB
t
FRAME
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Pixel Timing − Full Resolution − High Gain Pixel Timing
Use this timing to read out every pixel at high gain. If the
sensor is to be permanently operated at high gain, the R2ab
and R2cd pins can be left floating or set to any DC voltage
between +3 V and +5 V. Note the R2ab and R2cd pins are
internally biased to +4.3 V when left floating. The SHP1 and
SHD1 pulses indicate where the camera electronics should
sample the video waveform. The SHP1 and SHD1 pulses are
not applied to the image sensor.
Figure 40. Pixel Timing Diagram − Full Resolution − High Gain
0 V
−4 V
0 V
−4 V
+4.2 V
−1.8 V
+3 V
−3 V
Device
Pin Pattern
Hor izont al
Cl ocks
Video
VOUTa
RHG
Ra
R2HG
R2a
SHP1
SHD1
P1
P2
te
tR
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Pixel Timing − Full Resolution − Low Gain Pixel Timing
Use this pixel timing to read out every pixel at low gain.
If the sensor is to be permanently operated at low gain, the
Ra, Rb, Rc and Rd pins should be set to any DC voltage
between +3 V and +5 V. The SHP1 and SHD1 pulses
indicate where the camera electronics should sample the
video waveform. The SHP1 and SHD1 pulses are not
applied to the image sensor.
Figure 41. Pixel Timing Diagram − Full Resolution − Low Gain
0 V
−4 V
0 V
−4 V
+4.2 V
−1.8 V
+3 V
−3 V
Device
Pin Pattern
Hor izont al
Cl ocks
Video
VOUTa
RLG
Ra
R2LG
R2a
SHP1
SHD1
P1
P2
te
tR
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Pixel Timing − 1/4 Resolution − High Gain Pixel Timing
Use this timing to read out two pixels summed on the
output amplifier sense node at high gain. If the sensor is to
be permanently operated at high gain, the R2ab and R2cd
pins can be left floating or set to any DC voltage between
+3 V and +5 V. Note the R2ab and R2cd pins are internally
biased to +4.3 V when left floating. The SHPQ and SHDQ
pulses indicate where the camera electronics should sample
the video waveform. The SHPQ and SHDQ pulses are not
applied to the image sensor.
The Ra, Rb, Rc, and Rd pins are pulsed at half the
frequency of the horizontal CCD clocks. This causes two
pixels to be summed on the output amplifier sense node.
The SHPQ and SHDQ clocks are also half the frequency of
the horizontal CCD clocks.
Device
Pin Pattern
Hor izont al
Cl ocks
Video
VOUTa
RHGQ
Ra
R2HGQ
R2a
SHP1
SHD1
P1Q
P2Q
te
Figure 42. Pixel Timing Diagram − 1/4 Resolution − High Gain
0 V
−4 V
0 V
−4 V
+4.2 V
−1.8 V
+3 V
−3 V
2
⋅
t
e
tR
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Pixel Timing − 1/4 Resolution − Low Gain Pixel Timing
Use this timing to read out two pixels summed on the
output amplifier sense node at low gain. If the sensor is to be
permanently operated at low gain, the Ra, Rb, Rc and Rd
pins can be set to any DC voltage between +3 V and +5 V.
The SHPQ and SHDQ pulses indicate where the camera
electronics should sample the video waveform. The SHPQ
and SHDQ pulses are not applied to the image sensor.
The R2ab and R2cd pins are pulsed at half the frequency
of the horizontal CCD clocks. This causes two pixels to be
summed on the output amplifier sense node. The SHPQ an d
SHDQ clocks are also half the frequency of the horizontal
CCD clocks.
Device
Pin Pattern
Hor izont al
Cl ocks
Video
VOUTa
RLGQ
Ra
R2LGQ
R2a
SHP1
SHD1
P1Q
P2Q
te
Figure 43. Pixel Timing Diagram − 1/4 Resolution − Low Gain
0 V
−4 V
0 V
−4 V
+4.2 V
−1.8 V
+3 V
−3 V
2
⋅
t
e
tR
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XLDR Pixel Timing
To operate the sensor in extended linear dynamic range
(XLDR) mode, the following pixel timing should be used.
This mode requires two sets of analog front end (AFE) signal
processing electronic units for each output. As shown in
Figure 44 one AFE samples the pixel at low gain (SHPLG
and SHDLG) and the other AFE samples the pixel at high
gain (SHPHG and SHDHG).
Two HCCD pixels are summed on the output amplifier
node to obtain enough char ge to fully use the 82 dB range of
the XLDR timing. Combined with two-line VCCD
summing, a total of 160,000 electrons of signal (4 × 40,000)
can be sampled with 12 electrons or less noise. Note that
a linear dynamic range of 82 dB is very large. Ensure that t h e
camera optics is capable of focusing an 82 dB dynamic
range image on the sensor. Lens flare caused by inexpensive
optics or even dust on the lens will limit the dynamic range.
The timing shown in Figure 46 shows the HCCD not
being clocked at a constant frequency. If the HCCD cannot
be clocked at a variable frequency, then the HCCD may be
clocked at a constant frequency (Figure 45) at the expense
of about 33% slower frame rate.
Figure 44. XLDR Timing − AFE Connections Block Diagram
Low Gain AFE
High Gain AFE
SHPL
G
SHDL
G
SHPHG
SHDHG
Sensor Output
Low Gain
Digital Out
High Gain
Digital Out
Caution: In the XLDR mode the
output of the CCD can produce
large signals that may damage
some AFE devices. If there is the
potential for damage to the AFE,
the CCD output should be
electronically attenuated.
KAI−04070
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44
Pixel Timing − 1/4 Resolution − XLDR Pixel Timing − Constant HCCD Timing
Device
Pin Pattern
Hor izont al
Cl ocks
VideoVOUTa
RXLRa
P2XL
te
Figure 45. Pixel Timing Diagram − 1/4 Resolution − XLDR − Constant HCCD Timing
tR
0 V
−4 V
0 V
−4 V
+4.2 V
−1.8 V
+3 V
−3 V
tetete
P1XL
SHDHG
SHPHG
SHDLG
SHPLG
R2XLR2a
4
⋅
t
e
KAI−04070
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45
Pixel Timing − 1/4 Resolution − XLDR Pixel Timing − Variable HCCD Timing
Device
Pin Pattern
Hor izont al
Cl ocks
VideoVOUTa
RXLRa
P2XL
te
Figure 46. Pixel Timing Diagram − 1/4 Resolution − XLDR − Variable HCCD Timing
tR
P1XL
SHDHG
SHPHG
SHDLG
SHPLG
R2XLR2a
3
⋅
t
e
0 V
−4 V
0 V
−4 V
+4.2 V
−1.8 V
+3 V
−3 V
tete
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47
MECHANICAL INFORMATION
Completed Assembly
Figure 48. Completed Assembly (1 of 2)
1. See Ordering Information for marking code.
2. No materials to interfere with clearance through guide holes.
3. Units: mm.
Notes:
Figure 49. Completed Assembly (2 of 2)
1. Optical center of image is nominally at the package center.
2. Units: mm.
Notes:
KAI−04070
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48
Cover Glass
Figure 50. Cover Glass
1. Substrate = Schott D263T eco.
2. Dust, Scratch, Inclusion Specification: 10 mm maximum size in Zone A.
3. MAR coated both sides.
4. Spectral Transmission:
a. T > 98.0% 420−435 nm
b. T > 99.2% 435−630 nm
c. T > 98.0% 630−680 nm
5. Units: mm.
Notes:
KAI−04070
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50
REFERENCES
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference Manual (SOLDERRM/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf. S CILLC r eserves the right t o make changes without further n otice to any product s herein. S CILLC makes no warrant y, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all l iabilit y, including without limitation special, consequential or i ncident al d amages. “Typical” parameters which may be provided in SCILLC d at a s heet s
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application b y c ust omer’s technical e xperts. SCILLC does not c onvey a ny license under its p atent rights nor t he r ights of o thers. SCILLC p roducts ar e n ot d esigned, i ntended,
or authorized for use as c omponent s i n s yst ems i nt ended f or s urgic al i m plant i nt o the body, or other applications in tended to support or sust ain life, o r f or a ny o ther a pplicat ion in w hich
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC an d it s officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and r easonable a ttorney f ees a rising o ut of, directly or i ndirectly, any claim o f p ersonal i njury o r d eath a ssociated w ith s uch u nint ended o r u nauthorized u se, e ven if such claim
alleges that SCILLC was negligent regarding the d esign or manufacture of the p art. S CILLC i s a n E qual O pportunity/Af firmative Act ion Employer. T his literature is s ubject t o all applicable
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P
UBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
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Phone: 81−3−5817−1050
KAI−04070/D
LITERATURE FULFILLMENT:
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Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
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