FM25P16-GTR - Ramtron - Product.Network

Preliminary

This is a product that has fixed target specifications but are subject Ramtron International Corporation

to change pending characterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921

(800) 545-FRAM, (719) 481-7000

Rev. 1.0 www.ramtron.com

Dec. 2011 Page 1 of 14

FM25P16

16Kb Ultra Low Power Serial SPI F-RAM

Features

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2044 x 8 bits

• Unlimited Read/Write Cycles

• 10 Year Data Retention

• NoDelay™ Writes

• Member of a New Family of Low Energy

Memory Devices

Serial Peripheral Interface - SPI

• Up to 1 MHz Frequency

• Direct Hardware Replacement for EEPROM

• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)

Low Power Operation

• 1.8 - 3.6V Wide Operating Voltage

• 3.2 μA (typ.) Active Current @ 100 kHz

Applications

• Solar Powered

• Small Capacity Coin Cells

• Energy Harvesting

Industry Standard Configuration

• Industrial Temperature -40° C to +85° C

• “Green”/RoHS 8-pin SOIC Package

DESCRIPTION

The FM25P16 is a 16-kilobit nonvolatile memory

employing an advanced ferroelectric process. A

ferroelectric random access memory or F-RAM is

nonvolatile and performs reads and writes like a

RAM. It provides reliable data retention for 10 years

while eliminating the complexities, overhead, and

system level reliability problems caused by

EEPROM and other nonvolatile memories.

F-RAM technology uses less energy to perform

memory writes and completes those writes faster.

The FM25P16 is a member of a new family of low

energy memory products that take advantage of these

features to produce a nonvolatile memory that

requires very little energy to operate.

Unlike serial EEPROMs, the FM25P16 performs

write operations at bus speed. Data is written to the

memory array immediately after each byte has been

transferred to the device. The next bus cycle may

commence without the need for data polling. The

product offers virtually unlimited write endurance,

orders of magnitude more endurance than EEPROM.

These capabilities make the FM25P16 ideal for

nonvolatile memory applications requiring frequent

or rapid writes. Examples range from data logging

where the number of write cycles may be critical, to

applications where the long write time of EEPROM

would otherwise cause data loss.

The FM25P16 provides substantial benefits to users

of serial EEPROM as a hardware drop-in

replacement by using a standard SPI interface.

Device specifications are guaranteed over an

industrial temperature range of -40°C to +85°C.

PIN CONFIGURATION

Pin Name Function

/CS Chip Select

/WP Write Protect

/HOLD Hold

SCK Serial Clock

SI Serial Data Input

SO Serial Data Output

VDD Supply Voltage

VSS Ground

Ordering Information

FM25P16-G “Green”/RoHS 8-pin SOIC

VSS

VDD

HOLD

SCK

FM25P16 - 16Kb Ul tr a Low Power FRAM

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Dec. 2011 Page 2 of 14

Instruction Decode

Clock Generator

Control Logic

Write Protect

Instruction Register

Address Register

Counter

511 x 32

FRAM Array

Data I/O Register

Nonvolatile Status

HOLD

SCK

SOSI

Figure 1. Block Diagram

PIN DESCRIPTION

Pin Name I/O Description

/CS Input Chip Select: This active low input activates the device. When high, the device enters

low-power standby mode, ignores other inputs, and all outputs are tri-stated. When

low, the device internally activates the SCK signal. A falling edge on /CS must occur

prior to every op-code.

SCK Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on

the rising edge and outputs occur on the falling edge. Since the device is static, the

clock frequency may be any value between 0 and 1 MHz and may be interrupted at

any time.

/HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation

for another task. When /HOLD is low, the current operation is suspended. The device

ignores any transition on SCK or /CS. All transitions on /HOLD must occur while

SCK is low. If it is not used, the /HOLD pin should be tied to VDD.

/WP Input Write Protect: This active-low pin prevents write operations to the Status Register

only. A complete explanation of write protection is provided on pages 6 and 7. If it is

not used, the /WP pin should be tied to VDD.

SI Input Serial Input: All data is input to the device on this pin. The pin is sampled on the

rising edge of SCK and is ignored at other times. It should always be driven to a valid

logic level to meet IDD specifications.

* SI may be connected to SO for a single pin data interface.

SO Output Serial Output: This is the data output pin. It is driven during a read and remains tri-

stated at all other times including when /HOLD is low. Data transitions are driven on

the falling edge of the serial clock.

* SO may be connected to SI for a single pin data interface.

VDD Supply Power Supply (1.8V to 3.6V)

VSS Supply Ground

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Dec. 2011 Page 3 of 14

OVERVIEW

The FM25P16 is a serial F-RAM memory. The

memory array is logically organized as 2,044 x 8 and

is accessed using an industry standard Serial

Peripheral Interface or SPI bus. Functional operation

of the F-RAM is similar to serial EEPROMs. The

major difference between the FM25P16 and a serial

EEPROM with the same pinout is the F-RAM’s

superior write performance.

MEMORY ARCHITECTURE

When accessing the FM25P16, the user addresses

2,044 locations of 8 data bits each. These data bits

are shifted serially. The addresses are accessed using

the SPI protocol, which includes a chip select (to

permit multiple devices on the bus), an op-code, and

a two-byte address. The upper 5 bits of the address

range are ‘don’t care’ values. The complete address

of 11-bits specifies each byte address uniquely.

The top four address locations (0x7FC - 0x7FF)

are not user-accessible. A write to these locations

will be ignored by the device, and a read to these

locations will return 0x00.

Most functions of the FM25P16 either are controlled

by the SPI interface or are handled automatically by

on-board circuitry. The access time for memory

operation is essentially zero, beyond the time needed

for the serial protocol. That is, the memory is read or

written at the speed of the SPI bus. Unlike an

EEPROM, it is not necessary to poll the device for a

ready condition since writes occur at bus speed. So,

by the time a new bus transaction can be shifted into

the device, a write operation will be complete. This is

explained in more detail in the interface section.

Users expect several obvious system benefits from

the FM25P16 due to its fast write cycle and high

endurance as compared with EEPROM. In addition

there are less obvious benefits as well. For example

in a high noise environment, the fast-write operation

is less susceptible to corruption than an EEPROM

since it is completed quickly. By contrast, an

EEPROM requiring milliseconds to write is

vulnerable to noise during much of the cycle.

Serial Peripheral Interface – SPI Bus

The FM25P16 employs a Serial Peripheral Interface

(SPI) bus. It is specified to operate at speeds up to 1

MHz. This high-speed serial bus provides high

performance serial communication to a host

microcontroller. Many common microcontrollers

have hardware SPI ports allowing a direct interface.

It is quite simple to emulate the port using ordinary

port pins for microcontrollers that do not. The

FM25P16 operates in SPI Mode 0 and 3.

The SPI interface uses a total of four pins: clock,

data-in, data-out, and chip select. A typical system

configuration uses one or more FM25P16 devices

with a microcontroller that has a dedicated SPI port,

as Figure 2 illustrates. Note that the clock, data-in,

and data-out pins are common among all devices.

The Chip Select and Hold pins must be driven

separately for each FM25P16 device.

For a microcontroller that has no dedicated SPI bus, a

general purpose port may be used. To reduce

hardware resources on the controller, it is possible to

connect the two data pins (SI, SO) together and tie

off (high) the Hold pin. Figure 3 shows a

configuration that uses only three pins.

Protocol Overview

The SPI interface is a synchronous serial interface

using clock and data pins. It is intended to support

multiple devices on the bus. Each device is activated

using a chip select. Once chip select is activated by

the bus master, the FM25P16 will begin monitoring

the clock and data lines. The relationship between the

falling edge of /CS, the clock and data is dictated by

the SPI mode. The device will make a determination

of the SPI mode on the falling edge of each chip

select. While there are four such modes, the

FM25P16 supports Modes 0 and 3. Figure 4 shows

the required signal relationships for Modes 0 and 3.

For both modes, data is clocked into the FM25P16 on

the rising edge of SCK and data is expected on the

first rising edge after /CS goes active. If the clock

begins from a high state, it will fall prior to beginning

data transfer in order to create the first rising edge.

The SPI protocol is controlled by op-codes. These

op-codes specify the commands to the device. After

/CS is activated the first byte transferred from the bus

master is the op-code. Following the op-code, any

addresses and data are then transferred. Note that the

WREN and WRDI op-codes are commands with no

subsequent data transfer.

Important: The /CS must go inactive (high) after

an operation is complete and before a new op-code

can be issued. There is one valid op-code only per

active chip select.

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Dec. 2011 Page 4 of 14

SPI

Microcontroller FM25P16

SO SI SCK

CS HOLD

FM25P16

SO SI SCK

CS HOLD

SCK

MOSI

MISO

SS1

SS2

HOLD1

HOLD2

MOSI : Master Out Slave In

MISO : Master In Slave Out

SS : Slave Select

Figure 2. System Configuration with SPI port

Microcontroller

FM25P16

SO SI SCK

CS HOLD

P1.0

P1.1

P1.2

Figure 3. System Co nfiguration without SPI port

SPI Mode 0: CPOL=0, CPHA=0

01234567

SPI Mode 3: CPOL=1, CPHA=1

01234567

Figure 4. SPI Modes 0 & 3

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Dec. 2011 Page 5 of 14

Data Transfer

All data transfers to and from the FM25P16 occur in

8-bit groups. They are synchronized to the clock

signal (SCK), and they transfer most significant bit

(MSB) first. Serial inputs are registered on the rising

edge of SCK. Outputs are driven from the falling

edge of SCK.

Command Structure

There are six commands called op-codes that can be

issued by the bus master to the FM25P16. They are

listed in the table below. These op-codes control the

functions performed by the memory. They can be

divided into three categories. First, there are

commands that have no subsequent operations. They

perform a single function such as to enable a write

operation. Second are commands followed by one

byte, either in or out. They operate on the status

memory transactions followed by an address and one

or more bytes of data.

Table 1. Op-code Commands

Name Description Op-code

WREN Set Write Enable Latch 0000 0110b

WRDI Write Disable 0000 0100b

RDSR Read Status Register 0000 0101b

WRSR Write Status Register 0000 0001b

READ Read Memory Data 0000 0011b

WRITE Write Memory Data 0000 0010b

RDID Read Device ID 1001 1111b

WREN - Set Write Enable Latch

The FM25P16 will power up with writes disabled.

The WREN command must be issued prior to any

write operation. Sending the WREN op-code will

allow the user to issue subsequent op-codes for

write operations. These include writing the status

Sending the WREN op-code causes the internal

Write Enable Latch to be set. A flag bit in the status

WEL=1 indicates that writes are permitted.

Attempting to write the WEL bit in the status

operation will automatically clear the write-enable

latch and prevent further writes without another

WREN command. Figure 5 below illustrates the

WREN command bus configuration.

WRDI - Write Disable

The WRDI command disables all write activity by

clearing the Write Enable Latch. The user can verify

that writes are disabled by reading the WEL bit in

the status register and verifying that WEL=0. Figure

6 illustrates the WRDI command bus configuration.

Figure 5. WREN Bus Configuration

Figure 6. WRDI Bus Configuration

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Dec. 2011 Page 6 of 14

RDSR - Read Status Register

The RDSR command allows the bus master to verify

the contents of the Status Register. Reading Status

provides information about the current state of the

write protection features. Following the RDSR op-

code, the FM25P16 will return one byte with the

contents of the Status Register. The Status Register is

described in detail in a later section.

WRSR – Write Status Regis ter

The WRSR command allows the user to select

certain write protection features by writing a byte to

the Status Register. Prior to issuing a WRSR

command, the /WP pin must be high or inactive.

Note that on the FM25P16, /WP only prevents

writing to the Status Register, not the memory array.

Prior to sending the WRSR command, the user must

send a WREN command to enable writes. Note that

executing a WRSR command is a write operation

and therefore clears the Write Enable Latch. The bus

configuration of RDSR and WRSR are shown

below.

Figure 7. RDSR Bus Configuration

Figure 8. WRSR Bus Configuration

Status Register & Write Protection

The write protection features of the FM25P16 are

multi-tiered. First, a WREN op-code must be issued

prior to any write operation. Assuming that writes are

enabled using WREN, writes to memory are

controlled by the Status Register. As described

above, writes to the status register are performed

using the WRSR command and subject to the /WP

pin. The Status Register is organized as follows.

Table 2. Status Re gister

Bit 7 6 5 4 3 2 1 0

Name WPEN 0 0 0 BP1 BP0 WEL 0

Bits 0 and 4-6 are fixed at 0 and cannot be modified.

Note that bit 0 (Ready in EEPROMs) is unnecessary

as the F-RAM writes in real-time and is never busy.

The WPEN, BP1 and BP0 control write protection

features. They are nonvolatile (shaded yellow). The

WEL flag indicates the state of the Write Enable

Latch. Attempting to directly write the WEL bit in

the status register has no effect on its state. This bit

is internally set and cleared via the WREN and

WRDI commands, respectively.

BP1 and BP0 are memory block write protection

bits. They specify portions of memory that are write

protected as shown in the following table.

Table 3. Block Memory Write Protection

BP1 BP0 Protected Address Range

0 0 None

0 1 600h to 7FFh (upper ¼)

1 0 400h to 7FFh (upper ½)

1 1 000h to 7FFh (all)

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The BP1 and BP0 bits and the Write Enable Latch

are the only mechanisms that protect the memory

from writes. The remaining write protection features

protect inadvertent changes to the block protect bits.

The WPEN bit controls the effect of the hardware

/WP pin. When WPEN is low, the /WP pin is

ignored. When WPEN is high, the /WP pin controls

write access to the status register. Thus the Status

This scheme provides a write protection mechanism,

which can prevent software from writing the

memory under any circumstances. This occurs if the

BP1 and BP0 are set to 1, the WPEN bit is set to 1,

and /WP is set to 0. This occurs because the block

protect bits prevent writing memory and the /WP

signal in hardware prevents altering the block

protect bits (if WPEN is high). Therefore in this

condition, hardware must be involved in allowing a

write operation. The following table summarizes the

write protection conditions.

Table 4. Write Protection

WEL WPEN /WP Protected Blocks Unprotected Blocks Status Register

0 X X Protected Protected Protected

1 0 X Protected Unprotected Unprotected

1 1 0 Protected Unprotected Protected

1 1 1 Protected Unprotected Unprotected

MEMORY OPERATION

The SPI interface, which is capable of a relatively

high clock frequency, highlights the fast write

capability of the F-RAM technology. Unlike SPI-bus

EEPROMs, the FM25P16 can perform sequential

writes at bus speed. No page register is needed and

any number of sequential writes may be performed.

Write Operation

All writes to the memory array begin with a WREN

op-code. The next op-code is the WRITE instruction.

This op-code is followed by a two-byte address

value. The upper 5-bits of the address are ignored. In

total, the 11-bits specify the address of the first data

byte of the write operation. Subsequent bytes are data

and they are written sequentially. Addresses are

incremented internally as long as the bus master

continues to issue clocks. If the last address of 7FFh

is reached, the counter will roll over to 000h. Data is

written MSB first. A write operation is shown in

Figure 9.

Unlike EEPROMs, any number of bytes can be

written sequentially and each byte is written to

memory immediately after it is clocked in (after the

8th clock). The rising edge of /CS terminates a

WRITE op-code operation.

Read Operation

After the falling edge of /CS, the bus master can issue

a READ op-code. Following this instruction is a two-

byte address value. The upper 5-bits of the address

are ignored. In total, the 11-bits specify the address of

the first byte of the read operation. After the op-code

and address are complete, the SI line is ignored. The

bus master issues 8 clocks, with one bit read out for

each. Addresses are incremented internally as long as

the bus master continues to issue clocks. If the last

address of 7FFh is reached, the counter will roll over

to 000h. Data is read MSB first. The rising edge of

/CS terminates a READ op-code operation. A read

operation is shown in Figure 10.

Hold

The /HOLD pin can be used to interrupt a serial

operation without aborting it. If the bus master pulls

the /HOLD pin low while SCK is low, the current

operation will pause. Taking the /HOLD pin high

while SCK is low will resume an operation. The

transitions of /HOLD must occur while SCK is low,

but the SCK pin can toggle during a hold state.

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Dec. 2011 Page 8 of 14

Figure 9. Memory Write

(WREN must precede WRITE)

Figure 10. Memory Read

0 1 2 345670 1 2 345 45670 1 2 34567

op -c o de

0 0 0 0 0 0 1 0 M S B

11-bit

ess

X X X X X 10 3 2 1 0 7 6 5 4 3 2 1 0

LSB MSB LSB

C S

S C K

S I

S O

D ata

012345670 1 2 3456456701234567

op-code

0000001 MSB

11-bit

ess

XXXXX10 9 3 2 1 0

76543210

LSB MSB LSB

SCK

Data

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Dec. 2011 Page 9 of 14

Device ID

The FM25P16 device can be interrogated for its manufacturer, product identification, and die revision. The RDID

op-code 9Fh allows the user to read the manufacturer ID and product ID, both of which are read-only bytes. The

JEDEC-assigned manufacturer ID places the Ramtron identifier in bank 7, therefore there are six bytes of the

continuation code 7Fh followed by the single byte C2h. There are two bytes of product ID, which includes a Family

code, a Density code, a Sub code, and Product Revision code.

Table 5. Manufacturer and Product ID

Bit

7 6 5 4 3 2 1 0 Hex

Manufacturer ID 0 1 1 1 1 1 1 1 7F Continuation code

0 1 1 1 1 1 1 1 7F Continuation code

1 1 0 0 0 0 1 0 C2 JEDEC assigned Ramtron C2h in bank 7

Family Density Hex

Device ID (1st Byte) 0 1 0 0 0 0 1 0 42h Density: 02h=16K, 04h=64K

Sub Rev. Rsvd

Device ID (2n

Byte) 0 0 0 0 0 0 0 0 00h 00h=FM25P16

Figure 11. Read Device I D

Q 7Fh … 7Fh C2h 00h

Six bytes of continuation code 7Fh

9Fh

42h

1 6

. . . . . . .

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Dec. 2011 Page 10 of 14

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

Symbol Description Ratings

VDD Power Supply Voltage with respect to VSS -1.0V to +5.0V

VIN Voltage on any pin with respect to VSS -1.0V to +5.0V

and VIN < VDD+1.0V

TSTG Storage Temperature -55°C to + 125°C

TLEAD Lead Temperature (Soldering, 10 seconds) 260° C

VESD Electrostatic Discharge Voltage

- Human Body Model (AEC-Q100-002 Rev. E)

- Charged Device Model (AEC-Q100-011 Rev. B)

- Machine Model (AEC-Q100-003 Rev. E)

TBD

Package Moisture Sensitivity Level MSL-1

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating

only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this

specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

DC Operating Conditions (TA = -40° C to + 85° C, VDD = 1.8V to 3.6V unless otherwise specified)

Symbol Parameter Min Typ Max Units Notes

VDD Power Supply Voltage 1.8 3.0 3.6 V

IDD VDD Supply Current

@ SCK = 100 kHz

@ SCK = 1.0 MHz

3.2

μA

ISB Standby Current - 1.2 5

A 2

ILI Input Leakage Current -

A 3

ILO Output Leakage Current -

A 3

VIH Input High Voltage 0.7 VDD V

DD + 0.5 V

VIL Input Low Voltage -0.3 0.3 VDD V

VOH1 Output High Voltage

(IOH = -0.5 mA, VDD ≥ 2.7V)

2.4 - V

VOH2 Output High Voltage

(IOH = -100 μA)

VDD-0.2 - V

VOL1 Output Low Voltage

(IOL = 1 mA, VDD ≥ 2.7V)

- 0.4 V

VOL2 Output Low Voltage

(IOL = 150 μA)

- 0.2 V

VHYS Input Hysteresis (/CS and SCK only) 0.05 VDD - V 4

Notes

1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.

2. SCK = SI = /CS=VDD. All inputs VSS or VDD.

3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD.

4. Characterized but not 100% tested in production.

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AC Parameters (TA = -40° C to + 85° C, CL = 30pF)

Symbol Parameter Min Max Units Notes

SCK Clock Frequency 0 1000 kHz

tCH Clock High Time 300 ns 1

tCL Clock Low Time 300 ns 1

tCSU Chip Select Setup 200 ns

tCSH Chip Select Hold 100 ns

tOD Output Disable Time 100 ns 2

tODV Output Data Valid Time 200 ns

tOH Output Hold Time 0 ns

tD Deselect Time 200 ns

tR Data In Rise Time 50 ns 1,3

tF Data In Fall Time 50 ns 1,3

tSU Data Setup Time 70 ns

tH Data Hold Time 70 ns

tHS /Hold Setup Time 150 ns

tHH /Hold Hold Time 150 ns

tHZ /Hold Low to Hi-Z 100 ns 2

tLZ /Hold High to Data Active 100 ns 2

Notes

1. tCH + tCL = 1/fCK.

2. Characterized but not 100% tested in production.

3. Rise and fall times measured between 10% and 90% of waveform.

Power Cycle Timing (TA = -40° C to + 85° C, VDD = 1.8V to 3.6V)

Symbol Parameter Min Max Units Notes

tPU Power Up (VDD min) to First Access (/CS low) 1 - ms

tPD Last Access (/CS high) to Power Down (VDD min) 0 -

s 1

tVR V

DD Rise Time 1 -

s/V 2,3

tVF V

DD Fall Time 1 -

s/V 2,3

Notes

1. Assumes tCH and tCSH are both satisfied.

2. This parameter is periodically sampled and not 100% tested.

3. Slope measured at any point on VDD waveform.

Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)

Symbol Parameter Min Max Units Notes

CO Output Capacitance (SO) - 6 pF 1

CI Input Capacitance - 5 pF 1

Notes

1. This parameter is periodically sampled and not 100% tested.

AC Test Conditions

Input Pulse Levels 10% and 90% of VDD

Input rise and fall times 5 ns

Input and output timing levels 0.5 VDD

Output Load Capacitance 30 pF

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Serial Data Bus Timing

/Hold Timing

SCK

HOLD tHS

tHH

tHZ tLZ

tHS

tHH

Power Cycle Timing

VDD min

tPU

VDD

tVR

tPD

tVF

Data Retention (TA = -40° C to + 85° C)

Symbol Parameter Min Max Units Notes

TDR Data Retention 10 - Years

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MECHANICAL DRAWING

8-pin SOIC (JEDEC St andard MS-012, variation AA)

Pin 1

3.90 ±0.10 6.00 ±0.20

4.90 ±0.10

0.10

0.25

1.35

1.75

0.33

0.51

1.27 0.10 mm

0.25

0.50 45°

0.40

1.27

0.19

0.25

0°- 8°

Recommended PCB Footpri nt

7.70

0.65

1.27

2.00

3.70

Refer to JEDEC MS-012 for complete dimensions and notes.

All dimensions in millimeters.

SOIC Package Marking Scheme

Legend:

XXXX= part number, P= package type

LLLLLLL= lot code

RIC=Ramtron Int’l Corp, YY=year, WW=work week

Example: FM25P16, “Green” SOIC package, Year 2010, Work Week 28

FM25P16-G

A6340282A

RIC1028

XXXXXXX-P

LLLLLLL

RICYYWW

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REVISION HISTORY

Revision

Date

Summary

0.1 3/10/2010 Product Preview.

0.2 9/14/2010 Changed tOD and tODV timing parameters. Added note to tPD spec. Changed

supply current specs.

0.3 10/26/2010 Changed description of memory architecture from 2Kx8 to 2044x8.

0.4 6/20/2011 Removed DFN package.

1.0 12/20/2011 Changed to Preliminary status. Changed standby and active current specs.

Modified AC table.