CY7C024/024A/0241
CY7C025/0251
4K x 16/18 and 8K x 16/18 Dual-Port
Static RAM with SEM, INT, BUSY
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-06035 Rev. *D Revised December 09, 2008
Features
■
True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■
4K x 16 organization (CY7C024/024A
[1]
)
■
4K x 18 organization (CY7C0241)
■
8K x 16 organization (CY7C025)
■
8K x 18 organization (CY7C0251)
■
0.65 micron CMOS for optimum speed and power
■
High speed access: 15 ns
■
Low operating power: I
CC
= 150 mA (typ)
■
Fully asynchronous operation
■
Automati c power down
■
Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
■
On-chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Separate upper-byte and lower-byte control
■
Pin select for Master or Slave
■
Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin
(Pb-free) TQFP, and 100-pin TQFP
Functional Description
The CY7C024/024A/0241 and CY7C025/0251 are low power
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. V arious
arbitration schemes are included on the CY7C024/ 0241 and
CY7C025/0251 to handle situations when multiple processors
access the same piece of data. Two ports are provided,
permitting independent, asynchronous access for reads and
writes to any location in memory. The CY7C024/ 0241 and
CY7C025/0251 can be used as standalone 16 or 18-bit dual-port
static RAMs or multiple devices can be combined to function as
a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S
pin is provided for implementing 32-/36-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), an d Output Enable (OE). Two flags are
provided on ea ch port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semap hore) at any time. C ontrol of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip sel e c t (CE) pin.
The CY7C024/024A/0241 and CY7C025/0251 are available in
84-pin Pb-free PLCCs, 84-pin PLCCs (CY7C024 and CY7C025
only), 100-pin Pb-free T hin Quad Pl astic Fl atplack (TQFP), and
100-pin Thin Quad Pl astic Flatpack.
Note
1. CY7C024 and CY7C024A are functiona lly identical.
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 2 of 21
Logic Block Diagram
L
L
L
OE
L
A
0L
R/W
R
UB
R
CE
R
OE
R
CE
L
OE
L
UB
L
UB
R
I/O
8L
–I/O
15L
INTERRUPT
SEMAPHORE
ARBITRATION
CONTROL
I/O
MEMORY
ARRAY ADDRESS
DECODER
SEM
L
SEM
R
BUSY
L
INT
L
INT
R
M/S
CONTROL
I/O
LB
L
LB
R
I/O
0L
–I/O
7L
R/W
L
R/W
R
LB
R
CE
R
OE
R
A
0R
I/O
8R
I/O
15R
BUSY
R
I/O
0R
I/O
7R
(CY7C025/0251) A
12L
A
12R
(CY7C025/0251)
[2] [2]
–
–
ADDRESS
DECODER
A
11L
A
11R
[3]
[4]
[3]
[4]
Pin Configurations
Figure 1. 84-Pin PLCC (Top View)
Notes
2. BUSY is an output in master mode and an input in slave mode.
3. I/O
0
–I/O
8
on the CY7C0241/0251.
4. I/O
9
–I/O
17
on the CY7C0241/0251.
5. A
12L
on the CY7C025/0251.
6. A
12R
on the CY7C025/0251.
L
L
L
A
7L
OE
CE
NC
I/O
I/O
I/O
I/O
I/O
I/O
A
6L
A
5L
A
4L
A
3L
A
2L
INT
L
BUSY
L
M/S
BUSY
R
A
1R
A
2R
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
15L
V
CC
I/O
0R
I/O
2R
I/O
1R
I/O
3R
I/O
4R
I/O
5R
A
A
A
A
A
3R
A
4R
A
5R
A
6R
I/O
6R
I/O
7R
I/O
8R
GND
I/O
14L
A
1L
I/O
R/W
SEM
UB
A
0L
GND
INT
R
A
0R
GND
GND
7L
6L
5L
4L
3L
2L
0L
L
L
11L
10L
9L
8L
I/O
1L
V
CC
LB
L
OE
CE
I/O
I/O
I/O
I/O
I/O
A
A
A
A
GND
I/O
R/W
SEM
UB
9R
10R
11R
12R
13R
15R
R
R
R
R
10R
9R
8R
7R
I/O
14R
R
LB
R
A
11R
NC
GND
V
CC
63
62
61
60
59
58
57
56
55
54
535251504948
47
46454443
1234567891011
12
13
14
15
16
17
18
19
20
21 64
65
66
67
68
69
70
71
72
73
74
75767778798081828384
42414039383736353433
32
31
30
29
28
27
26
25
24
23
22 CY7C024/024A/025
[5]
[6]
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 3 of 21
Figure 2. 100-Pin TQFP (Top View)
Pin Configurations
(continued)
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
NC
NC
I/O
10L
I/O
11L
I/O
15L
V
CC
GND
I/O
1R
I/O
2R
V
CC
9091
A
3L
M/S
BUSY
R
I/O
14L
GND
I/O
12L
I/O
13L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
NC
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 4748 49 50
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
OE
L
SEM
L
V
CC
CE
L
UB
L
LB
L
NC
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
I/O
0R
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
Œ
R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
NC
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
CY7C024/5
R/W
L
[5]
[6]
Pin Definitions
Left Port Right Port Description
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
–A
11/12L
A
0R
–A
11/12R
Address
I/O
0L
–I/O
15/17L
I/O
0R
–I/O
15/17R
Data Bus Input/Output
SEM
L
SEM
R
Semaphore Enable
UB
L
UB
R
Upper Byte Select
LB
L
LB
R
Lower Byte Select
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S Master or Slave Select
V
CC
Power
GND Ground
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 4 of 21
Architecture
The CY7C024/024A/0241 and CY7C025/0251 consist of an
array of 4K words of 16/18 bits each and 8K words of 16/18 bits
each of dual-port RAM cells, I/O a nd address line s, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same loca tion, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be used for
port-to-port communication. T wo semaphore (SEM) control pins
are used for a llocating shared resources. W ith the M/S pin, the
CY7C024/024A/0241 and CY7C025/0251 can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The CY7C024/02 4A/0241 and CY7C025 /0251 have an
automatic power down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see Figure 7) or the CE pin (see Figure 8).
Required inputs for non contention ope rations are summarized
in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the outpu t; otherwise the
data read is not deterministic. Data is valid on the port t
DDD
after
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
ACE
after CE or t
DOE
after OE is
asserted. If the user of the CY7C024/024A/0241 or
CY7C025/0251 wishes to access a semaphore flag, then the
SEM pin must be asserted in stead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C024/024A/0241, 1FFF for the CY7C025/0251) is the
mailbox for the right port and the second-highest memory
location (FFE for the CY7C024/024A/0241, 1FFE for the
CY7C025/0251) is the mailbox for the left port. When one port
writes to the other port’s mailbox, an interrupt is generated to the
owner. The interrupt is reset when the owner reads the contents
of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the BU S Y signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active BUSY to a port prevents that port from reading its own
mailbox and thus resetting the interrupt to it.
If your application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2 on page 5.
Busy
The CY7C024/024A/0241 and CY7C025/0251 provide on-chip
arbitration to resolve simultaneous memory location access
(contention). If both ports’ CEs are asserted and an address
match occurs within t
PS
of each other , the busy logic determines
which port has access. If t
PS
is violated, one port definitely gains
permission to the location, but which one is not predictable.
BUSY is asserted t
BLA
after an address match or t
BLC
after CE
is taken L OW.
Master/Slave
A M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (t
BLC
or t
BLA
). Otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C024/024A/0241 and CY7C025/0251 provide eight
semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports. The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then verifies
its success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value is
available t
SWRD
+ t
DOE
after the rising edge of the semaphore
write. If the left port was successful (reads a zero), it assumes
control of the shared resource, otherwise (reads a one) it
assumes the right port has control and continues to poll the
semaphore. W hen the right side has relinquished contro l of the
semaphore (by wri ting a one), the left side succeeds in gai ning
control of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Selection Guide
Parameter 7C024/024A/0241–15
7C025/0251–15 7C024/0241–25
7C025/0251–25 7C024/0241–35
7C025/0251–35 7C024/0241–55
7C025/0251–55
Maximum Access Time (ns) 15 25 35 55
Typical Operati ng Current (mA) 190 170 160 150
Typical Standby Current for I
SB1
(mA) 50 40 30 20
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 5 of 21
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
0
is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now o nly be modifie d by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semapho re , the semaphore is se t to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port immediately owns the se maphore as soon as the left
port released it. Table 3 shows sample semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within t
SPS
of each other, the semaphore is
definitely obtained by one side or the other, but there is no
guarantee which side controls the semaphore
Table 1. Non-Contending Read/Write
Inputs Outputs Operation
CE R/W OE UB LB SEM I/O
0
–I/O
7[3]
I/O
8
–I/O
15[4]
H X X X X H High Z High Z Deselected: Power Down
X X X H H H High Z High Z Deselected: Power Down
L L X L H H High Z Data In Write to Upper Byte Only
L L X H L H Data In High Z Write to Lower Byte Only
L L X L L H Data In Data In Write to Both Bytes
L H L L H H High Z Data Out Read Upper Byte Only
L H L H L H Data Out High Z Read Lower Byte Only
L H L L L H Data Out Data Out Read Both Bytes
X X H X X X High Z High Z Outputs Disabled
H H L X X L Data Out Data Out Read Data in Semaphore Flag
X H L H H L Data Out Data Out Read Data in Semaphore Flag
H X X X L Data In Data In Write D
IN0
into Semaphore Flag
X X H H L Data In Data In Write D
IN0
into Semaphore Flag
L X X L X L Not Allowed
L X X X L L Not Allowed
Table 2. Interrupt Operation Example (Assumes BUSY
L
=BUSY
R
=HIGH)
[7]
Function Left Port Right Port
R/W
L
CE
L
OE
L
A
0L–11L
INT
L
R/W
R
CE
R
OE
R
A
0R–11R
INT
R
Set Right INT
R
Flag L L X (1)FFF X X X X X L
[9]
Reset Right INT
R
Flag X X X X X X L L (1)FFF H
[8]
Set Left INT
L
Flag X X X X L
[8]
LLX(1)FFEX
Reset Left INT
L
Flag X L L (1)FFE H
[9]
XXX X X
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 6 of 21
Table 3. Semaphore Operation Example
Function I/O
0
–I/O
15/17
Left I/O
0
–I/O
15/17
Right Status
No action 1 1 Semaphore-free
Left port writes 0 to semaphore 0 1 Left Port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore.
Left port writes 1 to semaphore 1 0 Right po rt obtains sema phore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore-free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Notes
7. A
0L–12L
and A
0R–12R
, 1FFF/1FFE for the CY7C025.
8. If BUSY
R
=L, then no change.
9. If BUSY
L
=L, then no change.
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 7 of 21
Maximum Ratings
[10]
Exceeding maximum ratings may shorten the useful life of the
device. User gui delines are not teste d .
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.3V to +7.0V
DC Voltage Applied to Outputs
in High-Z State............ ................. ...................–0.5V to +7.0V
DC Input Voltage
[11]
............................ ... .........–0.5V to +7.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge V oltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current................................................... > 200 mA
Operating Range
Range Ambient Temperature V
CC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 7C024/024A/0241–15
7C025/0251–15 7C024/024A/0241–25
7C025/0251–25 Unit
Min Typ Max Min Typ Max
V
OH
Output HIGH Voltage V
CC
= Min, I
OH
= –4.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage V
CC
= Min, I
OL
= 4.0 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 2.2 V
V
IL
Input LOW Voltage –0.7 0.8 –0.7 0.8 V
I
IX
Input Leakage Current GND ≤ V
I
≤ V
CC
–10 +10 –10 +10 μA
I
OZ
Output Leakage Current Output Disabled,
GND ≤ V
O
≤ V
CC
–10 +10 –10 +10 μA
I
CC
Operating Current V
CC
= Max, I
OUT
= 0 mA,
Outputs Disabled Com’l 190 300 170 250 mA
Ind 200 320 170 290
I
SB1
Standby Current
(Both Ports TTL Levels) CE
L
and CE
R
≥ V
IH
,
f = f
MAX[12]
Com’l 50 70 40 60 mA
Ind 50 70 75
I
SB2
Standby Current
(One Port TTL Level) CE
L
or CE
R
≥ V
IH
,
f = f
MAX[12]
Com’l 120 180 100 150 mA
Ind 120 180 100 170
I
SB3
Standby Current
(Both Ports CMOS
Levels)
Both Ports CE and CE
R
≥
V
CC
– 0.2V, V
IN
≥ V
CC
– 0.2V
or V
IN
≤ 0.2V, f = 0
[12]
Com’l 3 15 3 15 mA
Ind 3 15 3 15
I
SB4
Standby Current
(Both Ports CMOS
Levels)
One Port CE
L
or
CE
R
≥ V
CC
– 0.2V,
V
IN
≥ V
CC
– 0.2V or V
IN
≤ 0.2V ,
Active Port Outputs, f = f
MAX[12]
Com’l 110 160 90 130 mA
Ind 110 160 90 150
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions 7C024/024A/0241–35
7C025/0251–35 7C024/024A/0241–55
7C025/0251–55 Unit
Min Typ Max Min Typ Max
V
OH
Output HIGH Voltage V
CC
= Min, I
OH
= –4.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage V
CC
= Min, I
OL
= 4.0 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 2.2 V
V
IL
Input LOW Voltage –0.7 0.8 –0.7 0.8 V
I
IX
Input Leakage Current GND ≤ V
I
≤ V
CC
–10 +10 –10 +10 μA
I
OZ
Output Leakage Current Output Disabled, GND ≤ V
O
≤ V
CC
–10 +10 –10 +10 μA
Notes
10.The voltage on any input or I/O pin cannot exceed the power pin during power up
11. Pulse width < 20 ns .
12.f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
SB3
.
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 8 of 21
I
CC
Operating Current V
CC
= Max, I
OUT
= 0 mA,
Outputs Disabled Com’l 160 230 150 230 mA
Ind 160 260 150 260
I
SB1
Standby Current
(Both Ports TTL Levels) CE
L
and CE
R
≥ V
IH
,
f = f
MAX[12]
Com’l 30 50 20 50 mA
Ind 30 65 20 65
I
SB2
Standby Current
(One Port TTL Level) CE
L
or CE
R
≥ V
IH
,
f = f
MAX[12]
Com’l 85 135 75 135 mA
Ind 85 150 75 150
I
SB3
Standby Current
(Both Ports CMOS
Levels)
Both Ports CE and CE
R
≥
V
CC
– 0.2V, V
IN
≥ V
CC
– 0.2V
or V
IN
≤ 0.2V, f = 0
[12]
Com’l 3 15 3 15 mA
Ind 3 15 3 15
I
SB4
Standby Current
(Both Ports CMOS
Levels)
One Port C E
L
or
CE
R
≥ V
CC
– 0.2V,
V
IN
≥ V
CC
– 0.2V or V
IN
≤ 0.2V ,
Active Port Outputs, f = f
MAX[12]
Com’l 80 120 70 120 mA
Ind 80 135 70 135
Electrical Characteristics Over the Operating Range (continu ed)
Parameter Description Test Conditions 7C024/024A/0241–35
7C025/0251–35 7C024/024A/0241–55
7C025/0251–55 Unit
Min Typ Max Min Typ Max
Capacitance
[13]
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25
×
C, f = 1 MHz,
V
CC
= 5.0V 10 pF
C
OUT
Output Capacitance 10 pF
Figure 3. AC Test Loads and Waveforms
Note
13.Tested initially and after any design or process changes that may affect these parameters.
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUTPULSES
(a) Normal Load (Load 1)
R1 = 893Ω
5V
OUTPUT
R2 = 347Ω
C= 30pF
V
TH
=1.4V
OUTPUT
C= 30pF
(b) ThéveninEquivalent (Load 1) (c)Three-State Delay(Load 3)
C = 30 pF
OUTPUT
Load (Load 2)
R1 = 893Ω
R2 = 347Ω
5V
OUTPUT
C= 5pF
R
TH
= 250Ω
≤≤
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 9 of 21
Switching Characteristics
Over the Operating Range
[14]
Parameter Description
7C024/024A/0241–15
7C025/0251–15 7C024/024A/0241–25
7C025/0251–25 7C024/024A/0241–35
7C025/0251–35 7C024/024A/0241–55
7C025/0251–55
Unit
Min Max Min Max Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 15 25 35 55 ns
t
AA
Address to Data Valid 15 25 35 55 ns
t
OHA
Output Hold From Address
Change 3333ns
t
ACE[15]
CE LOW to Data Valid 15 25 35 55 ns
t
DOE
OE LOW to Data Valid 10 13 20 25 ns
t
LZOE[16, 17, 18]
OE Low to Low Z 3 3 3 3 ns
t
HZOE[16,17, 18]
OE HIGH to High Z 10 15 20 25 ns
t
LZCE[16, 17, 18]
CE LOW to Low Z 3 3 3 3 ns
t
HZCE[16, 17, 18]
CE HIGH to High Z 10 15 20 25 ns
t
PU[18]
CE LOW to Power Up 0 0 0 0 ns
t
PD[18]
CE HIGH to Power Down 15 25 25 55 ns
t
ABE[15]
Byte Enable Access Time 15 25 35 55 ns
Write Cycle
t
WC
Write Cycle Time 15 25 35 55 ns
t
SCE[15]
CE LOW to Write End 12 20 30 35 ns
t
AW
Address Setup to Write End 12 20 30 35 ns
t
HA
Address Hold From Write End 0 0 0 0 ns
t
SA[15]
Address Setup to Write Start 0 0 0 0 ns
t
PWE
Write Pulse Width 12 20 25 35 ns
t
SD
Data Setup to Write End 10 15 15 20 ns
t
HD
Data Hold From Write End 0 0 0 0 ns
t
HZWE[17, 18 ]
R/W LOW to High Z 10 15 20 25 ns
t
LZWE[17, 18]
R/W HIGH to Low Z 0 0 0 0 ns
t
WDD[19]
Write Pulse to Data Delay 30 50 60 70 ns
t
DDD[19]
Write Data Valid to Read
Data Valid 25 35 35 45 ns
Notes
14.Test conditions assume signal transit ion time of 3 ns or less, timing ref erence levels of 1.5V, input pulse levels of 0 to 3.0V, and output loadin g of the specified I
OI
/I
OH
and 30 pF load capacita nce.
15.To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
16.At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
17.Test conditions used are Load 3.
18.This parameter is guaranteed but not tested.
19.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11.
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 10 of 21
Data Retention Mode
The CY7C024/024A/0241 is designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH duri ng data retention,
within V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during
the power up and power down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (4.5V).
Busy Timing
[20]
t
BLA
BUSY LOW from Address
Match 15 20 20 45 ns
t
BHA
BUSY HIGH from Address
Mismatch 15 20 20 40 ns
t
BLC
BUSY LOW from CE LOW 15 20 20 40 ns
t
BHC
BUSY HIGH from CE HIGH 15 20 20 35 ns
t
PS
Port Setup for Priority 5 5 5 5 ns
t
WB
R/W HIGH after BUSY (Slave) 0 0 0 0 ns
t
WH
R/W HIGH after BUSY HIGH
(Slave) 13 20 30 40 ns
t
BDD[21]
BUSY HIGH to Data Valid Note 21 Note 21 Note 21 Note 21 ns
Interrupt Timing
[20]
t
INS
INT Set Time 15 20 25 30 ns
t
INR
INT Reset Time 15 20 25 30 ns
Semaphore Timing
t
SOP
SEM Flag Update Pulse (OE or
SEM)10 12 15 20 ns
t
SWRD
SEM Flag Write to Read Time 5 10 10 15 ns
t
SPS
SEM Flag Co nten tio n Win dow 5 10 10 15 ns
t
SAA
SEM Address Access Time 15 25 35 55 ns
Switching Characteristics
Over the Operating Range (continued)
[14]
Parameter Description
7C024/024A/0241–15
7C025/0251–15 7C024/024A/0241–25
7C025/0251–25 7C024/024A/0241–35
7C025/0251–35 7C024/024A/0241–55
7C025/0251–55
Unit
Min Max Min Max Min Max Min Max
Timing
Parameter Test Conditions
[22]
Max Unit
ICC
DR1
At VCC
DR
= 2V 1.5 mA
Notes
20.Test conditions used are Load 2.
21.t
BDD
is a calculated parameter and is the greater of t
WDD
–
t
PWE
(actual) or t
DDD
–
t
SD
(actual).
22.CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not test ed.
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 11 of 21
Switching Waveforms
Notes
23.R/W is HIGH for read cycles
24.Device is continuously selected CE = V
IL
and UB or LB = V
IL
. This waveform cannot be used for semaphore r eads.
25.OE = V
IL
.
26.Address valid prior to or coincident with CE transition LOW.
27.To access RAM, CE = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CE = V
IH
, SEM = V
IL
.
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
t
OHA
Figure 4. Read Cycle No. 1 (Either Port Address Access)
[23, 24, 25]
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
t
LZCE
t
PU
t
PD
I
SB
I
CC
DATA OUT
OE
CE and
LB or UB
CURRENT
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)
[23, 26, 27]
UB or LB
DATAOUT
t
RC
ADDRESS
t
AA
t
OHA
CE
t
LZCE
t
ABE
t
HZCE
t
HZCE
t
ACE
t
LZCE
Figure 6. Read Cycle No. 3 (Either Port)
[23,25,26, 26, 27]
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 12 of 21
Notes
28.R/W must be HIGH during all address transitions.
29.A write occurs during the overlap (t
SCE
or t
PWE
) of a LOW CE or SEM and a LOW UB or LB.
30.t
HA
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
31.If OE is LOW during a R/ W contro lled write cycle, the write pulse width must be t he larger of t
PWE
or (t
HZWE
+ t
SD
) to all ow the I/O drivers to tu rn of f and dat a to be
placed on the bus for the require d t
SD
. If OE is HIGH during an R/W controlled write cycle, this require ment does not apply and the write pulse can be as short as
the specified t
PWE
.
32.To access RAM, CE = V
IL
, SEM = V
IH
.
33.To access upper byte, CE = V
IL
, UB = V
IL
, SEM = V
IH
.
To access lower byte, CE = V
IL
, LB = V
IL
, SEM = V
IH
.
34.Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
35.During this period, the I/O pins are in the output state, and input signals must not be applied.
36.If the CE or SEM LOW transition occurs simultaneously with or after the R/W L OW transition, the outputs remain in the high impedance state.
Switching Waveforms
(continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Figure 7. Write Cycle No. 1: R/W Controlled Timing
[28,29,30,31]
[34]
[34]
[31]
[32,33]
NOTE 35 NOTE 35
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
Figure 8. Write Cycle N o. 2: CE Controlled Timing
[28,29,30,36]
[32,33]
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 13 of 21
Notes
37.CE = HIGH for the duration of the above timing (both write and read cycle).
38.I/O
0R
= I/O
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH.
39.Semaphores are reset (available to both ports) at cycle start.
40.If t
SPS
is violated, the semaphore is definitely obtained by one side or the other, but which side gets th e semaphore is unpredictable.
Switching Waveforms
(continued)
t
SOP
t
AA
VALID ADRESS VALID ADRESS
t
HD
DATA
IN
VALID DATA
OUT
VALID
t
OHA
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O
0
SEM
A
0
–A
2
Figure 9. Semaphore Read After Write Timing, Either Side
[37]
MATCH
t
SPS
A
0L
–A
2L
MATCH
R/W
L
SEM
L
A
0R
–A
2R
R/W
R
SEM
R
Figure 10. Timing Diagram of Semaphore Contention
[38,39,40]
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 14 of 21
Switching Waveforms
(continued)
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA IN
R
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
t
PS
t
BLA
t
BHA
t
BDD
BUSY
L
Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)
[41]
t
PWE
R/W
BUSY t
WB
t
WH
Figure 12. Write Timing with Busy Input (M/S=LOW)
Note
41.CE
L
= CE
R
= LOW
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 15 of 21
Note
42.If t
PS
is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Switching Waveforms
(continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
CE
R
ValidFirst:
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
Figure 13. Busy Timing Diagram No.1 (CE Arbitration)
[42]
CE
L
Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right AddressValid First:
Figure 14. Busy Timing Diagram No.2 (Address Arbitration)
[42]
Left Address Valid First:
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 16 of 21
Figure 15. Interrupt Timing Diagrams
Notes
43.t
HA
depends on which enable pin (CE
L
or R/W
L
) is deasserted first.
44.t
INS
or t
INR
depends on which enable pin (CE
L
or R/W
L
) is asserted last.
Switching Waveforms
(continued)
WRITE FFF (1FFF CY7C025)
t
WC
Right SideClears INT
R
:
t
HA
READ FFF
t
RC
t
INR
WRITE FFE (1FFE CY7C025)
t
WC
Right SideSets INT
L
:
Left Side Sets INT
R
:
Left SideClears INT
L
:
READ FFE
t
INR
t
RC
ADDRESS
R
CE
L
R/W
L
INT
L
OE
L
ADDRESS
R
R/W
R
CE
R
INT
L
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
t
HA
t
INS
(1FFF CY7C025)
(1FFE CY7C025)
[43]
[44]
[44]
[44]
[43]
[44]
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 17 of 21
Ordering Information
(
4K x16 Dual-Port SRAM)
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
15 CY7C024–15AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C024-15AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C024–15JC J83 84-Pin Plastic Leade d Chip Carrier
CY7C024-15JXC J83 84-Pin Pb Free Plastic Leaded Chip Carrier
25 CY7C024–25AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C024-25AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C024–25JC J83 84-Pin Plastic Leade d Chip Carrier
CY7C024A-25JXC J83 84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C024–25AI A100 100-Pin Th in Quad Flat Pack Industrial
CY7C024-25AXI A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C024–25JI J83 84-Pin Plastic Leaded Chip Carrier
CY7C024-25JXI J83 84-Pin Pb Free Plastic Leaded Chip Carrier
35 CY7C024–35AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C024-35AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C024–35JC J83 84-Pin Plastic Leade d Chip Carrier
CY7C024-35JXC J83 84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C024–35AI A100 100-Pin Th in Quad Flat Pack Industrial
CY7C024-35AXI A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C024–35JI J83 84-Pin Plastic Leaded Chip Carrier
CY7C024-35JXI J83 84-Pin Pb Free Plastic Leaded Chip Carrier
55 CY7C024–55AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C024-55AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C024–55JC J83 84-Pin Plastic Leade d Chip Carrier
CY7C024-55JXC J83 84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C024–55AI A100 100-Pin Th in Quad Flat Pack Industrial
CY7C024-55AXI A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C024–55JI J83 84-Pin Plastic Leaded Chip Carrier
CY7C024-55JXI J83 84-Pin Pb Free Plastic Leaded Chip Carrier
Ordering Information (8K x 16 Dual-Port SRAM)
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
15 CY7C025–15AC A100 10 0-Pin T hin Q uad Flat Pack Commercial
CY7C025-15AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C025–15JC J83 84-Pin Plastic Leaded Chip Carrier
CY7C025-15JXC J83 84-Pin Pb Free Plastic Le aded Chip Carrier
CY7C025–15AI A10 0 100-Pin Thin Quad Flat Pack Industrial
CY7C025-15AXI A100 100-Pin Pb Free Thin Quad Flat Pack
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 18 of 21
25 CY7C025–25AC A100 10 0-Pin T hin Q uad Flat Pack Commercial
CY7C025-25AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C025–25JC J83 84-Pin Plastic Leaded Chip Carrier
CY7C025-25JXC J83 84-Pin Pb Free Plastic Le aded Chip Carrier
CY7C025–25AI A10 0 100-Pin Thin Quad Flat Pack Industrial
CY7C025-25AXI A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C025–25JI J83 84-Pin Plastic Leaded Chip Carrier
CY7C025-25JXI J83 84-Pin Pb Free Plastic Leaded Chip Carrier
35 CY7C025–35AC A100 10 0-Pin T hin Q uad Flat Pack Commercial
CY7C025-35AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C025–35JC J83 84-Pin Plastic Leaded Chip Carrier
CY7C025-35JXC J83 84-Pin Pb Free Plastic Le aded Chip Carrier
CY7C025–35AI A10 0 100-Pin Thin Quad Flat Pack Industrial
CY7C025-35AXI A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C025–35JI J83 84-Pin Plastic Leaded Chip Carrier
CY7C025-35JXI J83 84-Pin Pb Free Plastic Leaded Chip Carrier
55 CY7C025–55AC A100 10 0-Pin T hin Q uad Flat Pack Commercial
CY7C025-55AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C025–55JC J83 84-Pin Plastic Leaded Chip Carrier
CY7C025-55JXC J83 84-Pin Pb Free Plastic Le aded Chip Carrier
CY7C025–55AI A10 0 100-Pin Thin Quad Flat Pack Industrial
CY7C025-55AXI A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C025–55JI J83 84-Pin Plastic Leaded Chip Carrier
CY7C025-55JXI J83 84-Pin Pb Free Plastic Leaded Chip Carrier
Ordering Information (4K x 18 Dual-Port SRAM)
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
15 CY7C0241–15AC A10 0 100-Pin Th in Quad Flat Pack Commercial
CY7C0241-15AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–15AI A100 100-Pin Thin Quad Fl at Pack Industrial
CY7C0241-15AXI A100 100-Pin Pb Free Thin Quad Flat Pack
25 CY7C0241–25AC A10 0 100-Pin Th in Quad Flat Pack Commercial
CY7C0241-25AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–25AI A100 100-Pin Thin Quad Fl at Pack Industrial
CY7C0241-25AXI A100 100-Pin Pb Free Thin Quad Flat Pack
35 CY7C0241–35AC A10 0 100-Pin Th in Quad Flat Pack Commercial
CY7C0241-35AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–35AI A100 100-Pin Thin Quad Fl at Pack Industrial
CY7C0241-35AXI A100 100-Pin Pb Free Thin Quad Flat Pack
Ordering Information (8K x 16 Dual-Port SRAM)
(continued)
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 19 of 21
55 CY7C0241–55AC A10 0 100-Pin Th in Quad Flat Pack Commercial
CY7C0241-55AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–55AI A100 100-Pin Thin Quad Fl at Pack Industrial
CY7C0241-55AXI A100 100-Pin Pb Free Thin Quad Flat Pack
Ordering Information (4K x 18 Dual-Port SRAM)
(continued)
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
8K x 18 Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
15 CY7C0251–15AC A100 1 00-Pin Thin Quad Flat Pack Commercial
CY7C0251–15AXC A100 100-Pin Pb Free Thin Quad Fla t Pack
25 CY7C0251–25AC A100 1 00-Pin Thin Quad Flat Pack Commercial
CY7C0251-25AXC A100 100-Pin Pb Free Thin Quad Flat Pack
CY7C0251–25AI A100 100-Pin Thin Quad F lat Pack Industrial
CY7C0251–25AXI A100 100-Pin Pb Free Thi n Qua d Flat Pack
35 CY7C0251–35AC A100 1 00-Pin Thin Quad Flat Pack Commercial
CY7C0251–35AXC A100 100-Pin Pb Free Thin Quad Fla t Pack
CY7C0251–35AI A100 100-Pin Thin Quad F lat Pack Industrial
CY7C0251–35AXI A100 100-Pin Pb Free Thi n Qua d Flat Pack
55 CY7C0251–55AC A100 1 00-Pin Thin Quad Flat Pack Commercial
CY7C0251–55AXC A100 100-Pin Pb Free Thin Quad Fla t Pack
CY7C0251–55AI A100 100-Pin Thin Quad F lat Pack Industrial
CY7C0251–55AXI A100 100-Pin Pb Free Thi n Qua d Flat Pack
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D Page 20 of 21
Package Diagrams
Figure 16. 100-Pin Pb-Free Thin Pla stic Qu ad Flat Pack (TQFP) A100
Figure 17. 84-Pin Pb Free Plastic Leaded Chip Carrier J83
51-85048-*C
51-85006-*A
[+] Feedback
Document #: 38-06035 Rev. *D Revised December 09, 2008 Page 21 of 21
All products and company names mentioned in this document may be the trademarks o f t heir respect i ve holders.
CY7C024/024A/0241
CY7C025/0251
© Cypress Semicondu ctor Corpor ation, 2001-200 8. The informati on cont ained herein is subject to change witho ut notice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress prod uc ts are n ot war ran t ed no r int end ed to be us ed for
medical, life supp or t, l if e savi n g, cr it ical control or safety ap pli c at ions, unless pursuant to a n exp re ss wr i tte n ag reement with Cypress. Fu rthermore, Cypress does not auth ori ze i ts products for use as
critical components in life-support systems where a malfunction or failur e may reasonably be expected to result in significant injury to the user. The inclusion of Cyp ress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com
PSoC Solutions
General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
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USB psoc.cypress.com/usb
Document Title: CY7C024/024A/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port St atic RAM with Sem, Int, Busy
Document Number: 38-06035
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** 110177 SZV 09/29/01 Change from Sp ec number: 38-00255 to 38-06035
*A 122286 RBI 12/27/02 Power up requirements added to Maximum Ratin gs Information
*B 236754 YDT See ECN Removed cross information from features section
*C 279132 RUY See ECN Added Lead (Pb)-Free packaging information
*D 2623540 VKN/PYRS 12/17/08 Added CY7C024A part
Updated Ordering information table
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