Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
http://www.cirrus.com
6-Channel Digital Amplifier Controller
Features
> 100 dB Dynamic Range - System Level
< 0.03% THD+N @ 1 W - System Level
32 kHz to 192 kHz Sample Rates
Internal Oscillator Circuit Supports 24.576 MHz
to 54 MHz Crystals
Integrated Sample Rate Converter (SRC)
– Eliminates Clock Jitter Effects
– Input Sample Rate Independent Operation
Power Supply Rejection Realtime Feedback
Spread Spectrum Modulation - Reduces EMI
PWM Popguard® for Single-Ended Mode
Eliminates AM Frequency Interference
Programmable Load Compensation Filters
Support for up to 40 kHz Audio Bandwidth
Digital Volume Control with Soft Ramp
– +24 to -127 dB in 0.25 dB Steps
Per Channel Programmable Peak Detect and
Limiter
SPI™ and I²C® Host Control Interfaces
Separate 2.5 V to 5.0 V Serial Port and Host
Control Port Supplies
DAI
Serial
Port
XTAL
PWMOUTA1+
Power
Supply
Rejection
PWMOUTB1+
SPI/I2C Host
Control Port
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
RST
INT
PSR_MCLK
PSR_SYNC
PSR_DATA
PWM
Backend
Control/
Status GPIO4
GPIO5
GPIO0
GPIO1
GPIO2
XTO
XTI
PWMOUTA1-
PWMOUTB1-
PWMOUTA2+
PWMOUTB2+
PWMOUTA2-
PWMOUTB2-
PWMOUTA3+
PWMOUTB3+
PWMOUTA3-
PWMOUTB3-
MUTE
DAI_MCLK
DAI_SCLK
DAI_LRCK
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
Volume
/ Limiter
Multibit
Σ∆
Modulator
PWM
Conversion
PWM
Conversion
PWM
Conversion
Volume
/ Limiter
Multibit
Σ∆
Modulator
Volume
/ Limiter
Multibit
Σ∆
Modulator
PWM
Clock
Control
Auto Fs
Detect
SYS_CLK
GPIO3
GPIO6
PSR_EN
PSR_RESET
PS_SYNC
SRC
MARCH '06
DS633F1
CS44600
2DS633F1
CS44600
General Description
The CS44600 is a multi-channel digital-to-PWM Class D audio system controller including interpolation, sample rate
conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedback in a 64-pin LQFP pack-
age.The architecture uses a direct-to-digital approach that maintains digital signal integrity to the final output filter,
minimizing analog interference effects which negativ ely af fect syst em performance.
The CS44600 integrates on-chip digital volume control, peak detect with limiter, de-emphasis, and 7 GPIO’s, allow-
ing easy interfacing to many commonly available power stages. The PWM amplifier can achieve greater than 90%
efficiency. This efficiency provides for smaller device package, less heat sink requirements, and smaller power
supplies.
The CS44600 is ideal for audio systems re quir ing wide dynamic ra ng e, negligible distor tion and low noise, such as
A/V receivers, DVD receivers, digital speaker and automotive audio systems.
DS633F1 3
CS44600
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
SPECIFIED OPERATING CONDITIONS .............................................................................................. 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8
DC ELECTRICAL CHARA CTERISTIC S ................ ... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... ................. . 9
DIGITAL INTERFACE CHARACTERISTICS ........................................................................................ 9
PWM OUTPUT PERFORMANCE CHARACTERISTICS .................................................................... 10
PWM FILTER CHARACTERISTICS ................................................................................................... 11
SWITCHING CHARACTERISTICS - XTI ............................................................................................ 11
SWITCHING CHARACTERISTICS - SYS_CLK .................................................................................. 12
SWITCHING CHARACTERISTICS - PWMOUTA1-B3 ....................................................................... 12
SWITCHING CHARACTERISTICS - PS_SYNC ................................................................................. 12
SWITCHING CHARACTERISTICS - DAI INTERFACE ...................................................................... 13
SWITCHING CHARACTE RISTIC S - CONTRO L PORT - I ²C FORMAT .... ... ... ... .... ... ... ... ... ................ 14
SWITCHING CHARACTE RISTIC S - CONTRO L PORT - SPI FORMAT ............................................ 15
2. PIN DESCRIPTIONS ......................................................................................................................... 16
2.1 I/O Pin Characteristics ................................................................................................................ 19
3. TYPICAL CONNECTION DIAGRAMS ......................................................................................20
4. APPLICATIONS ................................................................................................................................... 22
4.1 Overview ...... .... ... ... ... .... ... ................ ... ... .... ................ ... ... .... ................ ... ... ... .... ............................ 22
4.2 Feature Set Summary ................................................................................................................... 22
4.3 Clock Generation .............. ... ... ................ .... ... ... ... .... ................ ... ... ... .... ... ................ ... ................... 23
4.3.1 FsIn Domain Clocking .......................................................................................................... 24
4.3.2 FsOut Domain Clocking ..... ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ................ ...... 24
4.4 FsIn Clock Domain Modules ......................................................................................................... 26
4.4.1 Digital Audio Input Port ............ ... ... .... ... ................ ... .... ... ... ... ... .... ................ ... ... ... .... ............ 26
4.4.2 Auto Rate Detec t ............... ... ................ ... ... .... ................ ... ... ... .... ................ ... ... ... ................ 30
4.4.3 De-Emphasis .............. ... .... ................ ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ............ 30
4.5 FsOut Clock Domain Modules ....................................................................................................... 31
4.5.1 Sample Rate Converter ........... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ................ ... .... ... ... ...... 31
4.5.2 Load Compensation Filter .................................................................................................... 31
4.5.3 Digital Volume and Mute Control ....... ... ... ... .... ................ ... ... ... .... ... ... ................ ... .... ... ... ... ...31
4.5.4 Peak Detect / Limiter ............................................................................................................ 32
4.5.5 PWM Engines ................ .... ... ... ... ................ .... ... ... ... .... ... ... ................ ... .... ... ... ... ... ................ 32
4.5.6 Interpolation Filter .... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... ... ... ................ ................ 33
4.5.7 Quantizer .............. ... ... ... ................ .... ... ... ... .... ................ ... ... ... .... ... ................ ... ... ................ 33
4.5.8 Modulator ... ................ ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ............................ 33
4.5.9 PWM Outputs ... .... ................ ... ... ... .... ................ ... ... .... ... ... ................ ... .... ... ... ... ................... 33
4.5.10 Power Supply Rejection (PSR) Real-Time Feedback ........................................................ 34
4.6 Control Port Description and Timing ............................................................................................. 35
4.6.1 SPI Mode ................. ... ... ................ .... ... ... ... .... ................ ... ... ... .... ... ................ ... ... ................ 35
4.6.2 I²C Mode ............... ................ ... ... ... .... ... ................ ... .... ... ... ................ ... .... ... ... ... ................... 36
4.6.3 GPIOs ......... ... ................ .... ... ... ................ ... .... ... ................ ... ... .... ... ................ ... ................... 37
4.6.4 Host Interrupt ........ ... ... ................ ... .... ... ... ................ .... ... ... ................ ... .... ... ......................... 37
5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ....................................................................... 38
5.1 Reset and Power-Up ..................................................................................................................... 41
5.1.1 PWM PopGuard® Transient Control .................................................................................... 41
5.1.2 Recommended Power-Up Sequence ................................................................................... 41
5.1.3 Recommended PSR Calibration Sequence ........ ... .... ... ... ... ... .... ... ... ... ................ .... ... ... ... ... 42
5.1.4 Recommended Power-Down Sequence .............................................................................. 43
6. REGISTER QUICK REFERENCE ........................................................................................................ 44
7. REGISTER DESCRIPTION .................................................................................................................. 48
7.1 Memory Address Pointer (MAP) .................... ............................. ............................. ...................... 48
4DS633F1
CS44600
7.1.1 Increment (INCR) ................................................................................................................. 48
7.1.2 Memory Address Pointer (MAPx) ......................................................................................... 48
7.2 CS44600 I.D. and Revision Register (address 01h) (Read Only) ................................................. 48
7.2.1 Chip I.D. (Chip_IDx) ............................................................................................................. 48
7.2.2 Chip Revision (Rev_IDx) ...................................................................................................... 49
7.3 Clock Configuration and Power Control (address 02h) ................................................................. 50
7.3.1 Enable SYS_CLK Output (EN_SYS_CLK) ........................................................................... 50
7.3.2 SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0]) ....................................................... 50
7.3.3 PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0]) ............................................. 50
7.3.4 Power Down XTAL (PDN_XTAL) ......................................................................................... 50
7.3.5 Power Down Output Mode (PDN_OUTPUT_MODE) ........................................................... 51
7.3.6 Power Down (PDN) .............................................................................................................. 51
7.4 PWM Channel Power Down Control (address 03h) ...................................................................... 51
7.4.1 Power Down PWM Channels (PDN_PWMB3:PDN_PWMA1) ............................................. 51
7.5 Misc. Configuration (address 04h) ................................................................................................ 52
7.5.1 Digital Interface Format (DI FX) ... ... .... ... ................ ... .... ... ... ... ................ .... ... ... ... ... ................ 52
7.5.2 AM Frequency Hopping (AM_FREQ_HOP) ......................................................................... 52
7.5.3 Freeze Controls (FREEZE) .................................................................................................. 52
7.5.4 De-Emphasis Control (DEM[1:0]) ......................................................................................... 53
7.6 Ramp Configuration (address 05h) ............................................................................................... 53
7.6.1 Ramp-Up/Down Setting (RAMP[1:0]) .................................................................................. 53
7.6.2 Ramp Speed (RAMP_SPD[1:0]) ................ .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 53
7.7 Volume Control Configuration (address 06h) ............. ... ... .... ... ................ ... ... .... ... ... ... ... .... ... ... ...... 54
7.7.1 Single Volume Control (SNGVOL) ....................................................................................... 54
7.7.2 Soft Ramp and Zero Cross Control (SZC[1:0]) ............ ... ... ... ................ .... ... ... ... ... ................ 54
7.7.3 Enable 50% Duty Cycle for Mute Condition (MUTE_50/50) ................................................. 54
7.7.4 Soft Ramp-Down on Interface Error (SRD_ERR) ....... ...... ...... ....... ...... .... ...... ...... ....... ...... ... 55
7.7.5 Soft Ramp-Up on Recovered Interface Error (SRU_ERR) ................................................... 55
7.7.6 Auto-Mute (AMUTE) ............................................................................................................. 55
7.8 Master Volume Control - Integer (address 07h) ............................................................................ 56
7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0]) ............................................................ 56
7.9 Master Volume Control - Fraction (address 08h) .......................................................................... 56
7.9.1 Master Volume Control - Fraction (MSTR_FVOL[1:0]) ......................................................... 56
7.10 Channel XX Volume Control - Integer (addresses 09h - 0Eh) .................................................... 58
7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0]) ........................................................ 58
7.11 Channel XX Volume Cont rol1 - Frac tion (address 11h) ............................................................ 58
7.12 Channel XX Volume Cont rol2 - Frac tion (address 12h) .............................................................. 58
7.12.1 Channel Volume Control - Fraction (CHXX_FVOL[1:0]) .................................................... 58
7.13 Channel Mute (address 13h) ....................................................................................................... 59
7.13.1 Independent Channel Mute (CHXX_MUTE) ....................................................................... 59
7.14 Channel Invert (address 14h) ...................................................................................................... 59
7.14.1 Invert Signal Polarity (CHXX_INV) ........ ................ .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 59
7.15 Peak Limiter Control Register (address 15h) ............................................................................. 60
7.15.1 Peak Signal Limit All Channels (LIMIT_ALL) ...................................................................... 60
7.15.2 Peak Signal Limiter Enable (LIMIT_EN) ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ... .... ... ... ... ... 60
7.16 Limiter Attack Rate (address 16h) .............................................................................................. 60
7.16.1 Attack Rate (ARATE[7:0]) .................................................................................................. 60
7.17 Limiter Release Rate (address 17h) ......................................................................................... 61
7.17.1 Release Rate (RRATE[7:0]) ...............................................................................................61
7.18 Chnl XX Load Compensation Filter - Coarse Adjust (addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h) ..
61 7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0]) .................................. 61
7.19 Chnl XX Load Compensation Filter - Fine Adjust (addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h) .... 62
7.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0]) ......................................... 62
DS633F1 5
CS44600
7.20 Interrupt Mode Control (address 28h) ......................................................................................... 62
7.20.1 Interrupt Pin Control (INT1/INT0) .......................................................................................62
7.20.2 Overflow Level/Edge Select (OVFL_L/E) ........................................................................... 63
7.21 Interrupt Mask (address 29h) ...................................................................................................... 63
7.22 Interrupt Status (address 2Ah) (Read Only) ...............................................................................63
7.22.1 SRC Unlock Interrupt (SRC_UNLOCK) ........ ... ... ... .... ... ... ... ................ .... ... ... ... ... ................ 63
7.22.2 SRC Lock Interrupt (SRC_LOCK) ...................................................................................... 64
7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE) ................................................................. 64
7.22.4 Ramp-Down Complete Interrupt (RMPD N _DON E) ............... .... ... ................ ... ... .... ... ... ... ... 64
7.22.5 Mute Complete Interrupt (Mute_DONE) ............................................................................. 64
7.22.6 Channel Over Flow Interrupt (OVFL_INT) .... ... ... ... .... ... ................ ... ... .... ... ................ ... ... ... 64
7.22.7 GPIO Interrupt Condition (GPIO_INT) ... ... .... ... ... ... ................ .... ... ... ... ................ .... ... ... ... ... 64
7.23 Channel Over Flow Status (address 2Bh) (Read Only) .............................................................. 65
7.23.1 ChXX_OVFL ....................................................................................................................... 65
7.24 GPIO Pin In/Out (address 2Ch) ................................................................................................... 65
7.24.1 GPIO In/Out Selection (GPIOX_I/O) .................................................................................. 65
7.25 GPIO Pin Polarity/Type (address 2Dh) .... ... ... ... .... ................ ... ... ... .... ... ................ ... ... .... ... ......... 65
7.25.1 GPIO Polarity/Type Selection (GPIOX_P/T) ...................................................................... 65
7.26 GPIO Pin Level/Edge Trigger (address 2Eh) .............................................................................. 66
7.26.1 GPIO Level/Edge Input Sensitive (G PIO X _L/E ) .... .... ... ... ... ................ .... ... ... ... ... .... ... ... ... ... 66
7.27 GPIO Status Register (address 2Fh) .......................................................................................... 66
7.27.1 GPIO Pin Status (GPIOX_STATUS) .................................................................................. 66
7.28 GPIO Interrupt Mask Register (address 30h) .... .... ... ... ................ ... .... ... ... ... .... ... ................ ... ... ... 67
7.28.1 GPIO Pin Interrupt Mask (M_GPIOX) ................................................................................. 67
7.29 PWM Configuration Register (address 31h) ............................................................................... 67
7.29.1 Over Sample Rate Selection (OSRATE) ............................................................................ 67
7.29.2 Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG) ......... ... ... ... ... .... ... ... ... ... 67
7.29.3 Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG) ......... ... ... ... ... .... ... ... ... ... 67
7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG) ......................................................... 68
7.29.5 Channel B3 Output Configuration (B3_OUT_CNFG) ......................................................... 68
7.30 PWM Minimum Pulse Width Register (address 32h) ................................................................. 68
7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-) ................................................. 68
7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE [4: 0] ) . ... .... ................ ... ... ... .... ... ......... 68
7.31 PWMOUT Delay Register (address 33h) ................................................................................... 69
7.31.1 Differential Signal Delay (DIFF_DLY[2:0]) .......................................................................... 69
7.31.2 Channel Delay Settings (CHNL_DLY[4:0]) ........................................................................ 69
7.32 PSR and Power Supply Configuration (address 34h) ................................................................. 70
7.32.1 Power Supply Rejection Enable (PSR _EN) .......... .... ... ... ... ... .... ................ ... ... ... .... ... ... ... ... 70
7.32.2 Power Supply Rejection Reset (PSR_RESET) .................................................................. 70
7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN) ........ ....... ...... ...... ....... ... ...... 71
7.32.4 Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0]) ..................................... 71
7.33 Decimator Shift/Scale (addresses 35h, 36h, 37h) ....................................................................... 71
7.33.1 Decimator Shift (DEC_SHIFT[2:0]) ..................................................................................... 71
7.33.2 Decimator Scale (DEC_SCALE[18:0]) ............................................................................... 71
7.34 Decimator Outd (addresses 3Bh, 3Ch, 3Dh) ............................................................................... 72
7.34.1 Decimator Outd (DEC_OUTD[23:0]) .................................................................................. 72
8. PARAMETER DEFINITIONS ................................................................................................................ 73
9. REFERENCES ...................................................................................................................................... 75
10. PACKAGE DIMENSIONS ......................................................................................................... 76
11. THERMAL CHARACTERISTICS ....................... ... ... .... ................ ... ... ... .... ... ... ... .... ... ... ................ ...... 77
12. ORDERING INFORMATIO N .............. ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ... ................ ......... 77
13. REVISION HISTORY ................... .... ... ... ... ... .... ................ ... ... .... ... ... ... ................ .... ... ... ... ................... 77
6DS633F1
CS44600
LIST OF FIGURES
Figure 1.Performance Characteristics Evaluation Active Filter Circuit ...................................................... 10
Figure 2.XTI Timings ....... ... ... .... ................ ... ... ... .... ... ... ................ .... ... ... ... ... .... ... ...................................... 11
Figure 3.SYS_CLK Timings ...................................................................................................................... 12
Figure 4.PWMOUTxx Timings .. ................ ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... ................ 12
Figure 5.PS_SYNC Timings .. .... ... ... ... ................ .... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ................... 12
Figure 6.Serial Audio Interface Timing ......... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ................ ... ... ... ................ 13
Figure 7.Serial Audio Interface Timing - TDM Mode ................................................................................. 13
Figure 8.Control Port Timing - I²C Format . ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... ... ... ... .... ............ 14
Figure 9.Control Port Timing - SPI Format ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ............ 15
Figure 10.CS44600 Pinout Diagram .. .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ............ 16
Figure 11.Typical Full-Bridge Connection Diagram .. ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... ................ 20
Figure 12.Typical Half-Bridge Connection Diagram .................................................................................. 21
Figure 13.CS44600 Data Flow Diagram (Single Channel Shown) ........................................................... 23
Figure 14.Fundamental Mode Crystal Configuration ....................... ... ... ... ................ .... ... ... ... ... .... ... ... ... ... 24
Figure 15.3rd Overtone Crystal Configuration .......................................................................................... 25
Figure 16.CS44600 Internal Clock Generation ......................................................................................... 25
Figure 17.I²S Serial Audio Formats ........................................................................................................... 27
Figure 18.Left-Justified Serial Audio Formats ........................................................................................... 27
Figure 19.Right-Justified Serial Audio Formats ......................................................................................... 28
Figure 20.One Line Mode #1 Serial Audio Format .................................................................................... 28
Figure 21.One Line Mode #2 Serial Audio Format .................................................................................... 29
Figure 22.TDM Mode Serial Audio Format .. ... ... ................. ... ... ... .... ... ................ ... ... .... ... ................ ......... 29
Figure 23.De-Emphasis Curve ........ ... .... ................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... ................ 30
Figure 24.Control Port Timing in SPI Mode .............................................................................................. 35
Figure 25.Control Port Timing, I²C Slave Mode Write ............................................................................... 36
Figure 26.Control Port Timing, I²C Slave Mode Read ............................................................................... 36
Figure 27.Recommended CS44600 Power Supply Decoupling Layout .................................................... 38
Figure 28.Recommended CS44600 Crystal Circuit Layout ...................................................................... 39
Figure 29.Recommended PSR Circuit Layout ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 40
Figure 30.PSR Calibration Sequence ....................................................................................................... 43
Figure 31.PWM Output Delay ............ .... ... ... ... ... ....................................................................................... 70
Figure 32.64-Pin LQFP Package Drawing ................................................................................................ 76
DS633F1 7
CS44600
LIST OF TABLES
Table 1. Common DAI_MCLK Frequencies .............................................................................................. 24
Table 2. DAI Serial Audio Port Channel Allocations ................................................................................. 26
Table 3. Load Compensation Example Settings ....................................................................................... 31
Table 4. Typical PWM Switch Rate Settings ............................................................................................. 33
Table 5. Digital Audio Interface Formats ................................................................................................... 52
Table 6. Master Integer Volume Settings .................................................................................................. 56
Table 7. Master Fractional Volume Settings ............................................................................................. 57
Table 8. Channel Integer Volume Settings ............................................................................................... 58
Table 9. Channel Fractional Volume Settings ........................................................................................... 59
Table 10. Limiter Attack Rate Settings ...................................................................................................... 61
Table 11. Limiter Release Rate Settings ................................................................................................... 61
Table 12. Channel Load Compensation Filter Coarse Adjust ............. ... ................................................... 62
Table 13. Channel Load Compensation Filter Fine Adjust ........................................................................ 62
Table 14. PWM Minimum Pulse Width Settings . .... ... ................ ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 69
Table 15. Differential Signal Delay Settings .............................................................................................. 69
Table 16. Channel Delay Settings .......... ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ... ... ... .... ... ... ... ................... 69
Table 17. Power Supply Sync Clock Divider Settings ............................................................................... 71
Table 18. Decimator Shift/Sca le Coefficient Calculation Examples .......................................................... 72
8DS633F1
CS44600
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteri stic s an d spec if icat ion s ar e de riv e d from measurements taken at nominal supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to ground)
Notes:
1. When using external crystal, VDX = 3.14 V(min). When using clock signal input, VDX = 2.37 V(min).
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.)
WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
Parameter Symbol Min Typ Max Units
DC Power Supply
Digital 2.5 V VD 2.37 2.5 2.63 V
XTAL (Note 1) 2.5 V
3.3 V
5.0 V
VDX 2.37
3.14
4.75
2.5
3.3
5.0
2.63
3.47
5.25
V
V
V
PWM Interface 3.3 V
5.0 V VDP 3.14
4.75 3.3
5.0 3.47
5.25 V
V
Serial Audio Interface 2.5 V
3.3 V
5.0 V
VLS 2.37
3.14
4.75
2.5
3.3
5.0
2.63
3.47
5.25
V
V
V
Control Interface 2.5 V
3.3 V
5.0 V
VLC 2.37
3.14
4.75
2.5
3.3
5.0
2.63
3.47
5.25
V
V
V
Ambient Operating Temperature
Commercial -CQZ
Automotive -DQZ TA-10
-40 -
-+70
+85 °C
°C
Parameters Symbol Min Max Units
DC Power Supply Digital
XTAL
PWM Interface
Serial Audio Interface
Control Interface
VD
VDX
VDP
VLS
VLC
-0.3
-0.3
-0.3
-0.3
-0.3
3.5
6.0
6.0
6.0
6.0
V
V
V
V
V
Input Current (Note 2) Iin -±10mA
Digital Input Voltage PWM Interface
(Note 3) Serial Audio Interface
Control Interface
VIND-PWM
VIND-S
VIND-C
-0.3
-0.3
-0.3
VDP+0.4
VLS+0.4
VLC+0.4
V
V
V
Ambient Operating Temperature -CQ
(power applied) -DQ TA-20
-50 +85
+95 °C
°C
Storage Temperature Tstg -65 +150 °C
DS633F1 9
CS44600
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground; DAI_MCLK = 12.288 MHz, XTAL = 24.576 MHz, PWM Switch
Rate = 384 kHz unless otherwise specified.)
4. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input.
5. Current consumption increases with increasing XTAL clock rates and PWM switch rates. Variance be-
tween DAI clock rates is negligible.
6. ILC measured with no external load ing on the SDA pin.
7. Valid with PSRR function enabled and the recommended external ADC (CS4461) and filtering.
8. Power down mode is defined as RST pin = LOW with all clock and data lines held static.
9. When RST pin = LOW, the internal oscillator is active to provide a valid clock for the SYS_CLK output.
DIGITAL INTERFACE CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground)
10. Serial Port signals include: SYS_CLK, DAI_MCLK, DAI_SCLK, DAI_LRCK, DAI_SDIN1-3
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, INT, RST, MUTE
PWM signals include: PWMOUTA1-B3, PSR_MCLK, PSR_SYNC, PSR_DATA, PS_SYNC, GPIO[6:0]
Parameter Symbol Min Typ Max Units
Normal Operation (Note 4)
Power Supply Current (Note 5) VD = 2.5 V
VDX = 3.3 V
VDP = 3.3 V
VLS = 3.3 V
VLC = 3.3 V (Note 6)
ID
IDX
IDP
ILS
ILC
-
-
-
-
-
150
2
1.2
150
250
-
-
-
-
-
mA
mA
mA
µA
µA
Power Dissipation VD=2.5 V, VDX = VDP = VLS = VLC = 3.3 V - 387 500 mW
Power Supply Rejection Ratio (Note 7) (1 kHz)
(60 Hz) PSRR -
-15
40 -
-dB
dB
Power-Down Mod e (Note 8)
Power Supply Current All Supplies except VDX (Note 9) Ipd -80-µA
Parameters (Note 10) Symbol Min Typ Max Units
High-Level Input Voltage XTAL
PWM Interface
Serial Audio Interface
Control Interface
VIH
0.7xVDX
0.7xVDP
0.7xVLS
0.7xVLC
-
-
-
-
-
-
-
-
V
V
V
V
Low-Level Input Voltage XTAL
PWM Interface
Serial Audio Interface
Control Interface
VIL
-
-
-
-
-
-
-
-
0.2xVDX
0.2xVDP
0.2xVLS
0.2xVLC
V
V
V
V
High-Level Output Voltage at Io = -2 mA PWM Interface
Serial Audio Interface
Control Interface VOH
VDP-1.0
VLS-1.0
VLC-1.0
-
-
-
-
-
-
V
V
V
Low-Level Output Voltage at Io = 2 mA PWM Interface
Serial Audio Interface
Control Interface VOL
-
-
-
-
-
-
0.45
0.45
0.45
V
V
V
Input Leakage Current Iin --±10µA
Input Capacitance - - 8 pF
10 DS633F1
CS44600
PWM OUTPUT PERFORMANCE CHARACTERISTICS
(Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL= 24.576 MHz; PWM
Switch Rate = 384 kHz; Fs = 32 kHz to 192 kHz; Measurement bandwidth is 10 Hz to 20 kHz unless otherwise
specified; Performance measurements taken with a full-scale 997 Hz.)
11. Performance characteristics measured using filter shown in Figure 1.
Parameter Symbol Min Typ Max Unit
Dynamic Performance (Note 11)
24-Bits A-Weighted
unweighted
16-Bits unweighted
102
99
-
108
105
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 11 )
24-Bits 0 dB
-20 dB
-60 dB
THD+N -
-
-
-90
-77
-45
-85
-
-
dB
dB
dB
Idle Channel Noise / Signal-to-Noise Ratio - 110 - dB
Interchannel Isolation (1 kHz) - 100 - dB
-
+
-
+
PWMOUTxx+
PWMOUTxx-
-
+-
+
Analog
Output
Figure 1. Performance Characteristics Evalu atio n Active Filter Circuit
DS633F1 11
CS44600
PWM FILTER CHARACTERISTICS
(Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL = 24.576 MHz; PWM
Switch Rate = 384 kHz; Fs = 32 kHz to 192 kHz; Measurement bandwidth is 10 Hz to 20 kHz unless otherwise
specified.)
12. Filter response is not production tested but is characterized and guaranteed by design.
13. XTAL = 49.152 MHz; PWM Switch Rate = 768 kHz; Fs = 96 kHz to 192 kHz.
14. The equation for the gr oup delay throug h the sa mple rate conver ter with OSRATE = 0b is (8.5 / Fsi) + (10
/ Fso) ± (4.5 / Fsi). The equation for the gr oup delay through the sample rate co nverter with OSRATE = 1b
is (8.5 / Fsi) + (20 / Fso) ± (4.5 / Fsi).
SWITCHING CHARACTERISTICS - XTI
(VD = 2.5 V, VDP = VLC = VLS = 3.3 V, VDX = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VDX)
Parameter UnitMin Typ Max
Digital Filter Response (Note 12)
Passband
OSRATE = 0b to -0.01 dB corner
to -3 dB corner
OSRATE = 1b (No te 13 ) to -0.01 dB corner
to -3 dB corner
0
0
0
0
-
-
-
-
1.6
24.0
3.3
44.5
kHz
kHz
kHz
kHz
Frequency Response
OSRATE = 0b 10 Hz to 20 kHz
OSRATE = 1b (No te 13 ) 10 Hz to 40 kHz -0.8
-1.2 -
-+0.02
+0.02 dB
dB
Group Delay (Note 14) ms
De-emphasis Error Fs = 32 kHz
(Relative to 1 kHz ) Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
±0.23
±0.14
±0.09
dB
dB
dB
Parameter Symbol Min Typ Max Unit
XTI period tclki 18.518 --- 40.69 ns
XTI high time tclkih 8.34 --- 22.38 ns
XTI low time tclkil 8.34 --- 22.38 ns
XTI Duty Cycle 45 50 55 %
External Crystal operating frequency 24.576 --- 54 MHz
XTI tclkih tclkil
tclki
Figure 2. XTI Timings
12 DS633F1
CS44600
SWITCHING CHARACTERISTICS - SYS_CLK
(VD = 2.5 V, VDP = VLC = VDX = 3.3 V, VLS = 2.5 V to 5.0 V, Cload = 50 pF)
SWITCHING CHARACTERISTICS - PWMOUTA1-B3
(VD = 2.5 V, VLS = VLC = VDX = 3.3 V, VDP = 3.3 V to 5.0 V unless otherwise specified, Cload = 10 pF)
SWITCHING CHARACTERISTICS - PS_SYNC
(VD = 2.5 V, VLS = VLC = VDX = 3.3 V, VDP = 3.3 V to 5.0 V, Cload = 20 pF)
Parameter Symbol Min Typ Max Unit
SYS_CLK Period tsclki 18.518 --- --- ns
SYS_CLK Duty Cycle 45 50 55 %
Parameter Symbol Min Typ Max Unit
PWMOUTxx Period tpwm 2.60 - 1.18 µs
Rise Time of PWMOUTxx VDP = 5.0 V
VDP = 3.3 V tr-
-1.6
2.1 -
-ns
ns
Fall Time of PWMOUTxx VDP = 5.0 V
VDP = 3.3 V tf-
-1.1
1.4 -
-ns
ns
Parameter Symbol Min Typ Max Unit
PS_SYNC Period tpsclki 592.576 --- --- ns
PS_SYNC Duty Cycle 45 50 55 %
SYS_CLK
tsclki
Figure 3. SYS_CLK Timings
PWMOUTxx
tpwm
trtf
Figure 4. PWMOUTx x Ti mi ngs
PS_SYNC
tpsclki
Figure 5. PS_SYNC Timings
DS633F1 13
CS44600
SWITCHING CHARACTERISTICS - DAI INTERFACE
(VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLS.)
15. After powerin g up, the CS44600, RST should be held low until after the power supplies and clocks are set-
tled.
16. See Table 1 on page 26 for suggested MCLK frequencies.
17. Max DAI sample rate is 96 kHz for One Line and TDM modes of operation.
Parameters Symbol Min Max Units
RST pin Low Pulse Width (Note 15) 1-ms
DAI_MCLK Duty Cycle (Note 16) 40 60 %
DAI_SCLK Duty Cycle 45 55 %
DAI_LRCK Duty Cycle 45 55 %
DAI Sample Rate (Note 17) Fs32 192 kHz
DAI_SDIN Setup Time Before DAI_SCLK Rising Edge tds 10 - ns
DAI_SDIN Hold Time After DAI_SCLK Rising Edge tdh 10 - ns
DAI_SCLK High Time tsckh 20 - ns
DAI_SCLK Low Time tsckl 20 - ns
DAI_LRCK Setup Time Before DAI_SCLK Rising Edge tlrcks 25 - ns
DAI_SCLK Rising Edge Before DAI_LRCK Edge tlrckd 25 - ns
sckh sckl
t
t
DAI_SDINx
lrcks
t
lrckd
t
DAI_SCLK
DAI_LRCK
ds
tdh
t
Figure 6. Serial Aud io Interface Timing Figure 7. Serial Audio Interface Timing - TDM Mode
sckh sckl
t
t
DAI_SDIN1
dh
t
ds
t
lrcks
t
lrckd
t
DAI_SCLK
(input)
DAI_LRCK
(input) lrcks
t
MSB MSB-1
14 DS633F1
CS44600
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(VD = 2.5 V, VDX = VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)
18. Data must be held for sufficient time to bridge the transition time, tf, of SCL.
Parameter Symbol Min Max Unit
SCL Clock Frequency fscl - 100 kHz
Bus Free Time between Transm issions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 18) thdd 10 - ns
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL and SDA tr-1000ns
Fall Time SCL and SDA tf-300ns
Setup Time for Stop Condition tsusp 4.7 - µs
tbuf thdst thdst
tlow tr
tf
thdd
thigh
tsud tsust
tsusp
Stop Start Start Stop
Repeated
SDA
SCL
Figure 8. Control Port Timing - I²C Format
DS633F1 15
CS44600
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For fsck <1 MHz.
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency fsck 0-6.0MHz
CS High Time between Transmissions tcsh 1.0 - - µs
CS Falling to CCLK Edge tcss 20 - - ns
CCLK Low Time tscl 66 - - ns
CCLK High Time tsch 66 - - ns
CDIN to CCLK Rising Setup Time tdsu 40 - - ns
CCLK Rising to DATA Hold Time (Note 19) tdh 15 - - ns
CCLK Falling to CDOUT Stable tpd - - 50 ns
Rise Time of CDOUT tr1 - - 25 ns
Fall Time of CDOUT tf1 - - 25 ns
Rise Time of CCLK and CDIN (Note 20) tr2 - - 100 ns
Fall Time of CCLK and CDIN (Note 20) tf2 - - 100 ns
tr2 tf2
tdsu tdh
tsch
tscl
CS
CCLK
CDIN
tcss
tpd
CDOUT
tcsh
Figure 9. Control Port Timing - SPI Format
16 DS633F1
CS44600
2. PIN DESCRIPTIONS
GND
XTI
XTO
VLS
DAI_MCLK
DAI_SCLK
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
INT
RST
VD
GND
GPIO0
GND
VDP
PWMOUTB2+
VDP
GND
PWMOUTA1+
PWMOUTA1-
PWMOUTB1+
PWMOUTB1-
PWMOUTA2+
PWMOUTA2-
PSR_MCLK
PSR_SYNC
PSR_DATAL
PWMOUTB2-
PWMOUTA3+
PWMOUTA3-
PWMOUTB3+
PWMOUTB3-
NC
NC
NC
NC
VLC
DAI_LRCK
NC
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
GND
VDX
GPIO3
GPIO4
GPIO6
GPIO2
VD
VDP
GND
GND
VDP
SYS_CLK
GND
PSR_RESET
GPIO1
GPIO5
MUTE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PSR_EN
PS_SYNC
GND
CS44600
Figure 10. CS44600 Pinout Diag ram
DS633F1 17
CS44600
Pin Name Pin # Pin Description
PS_SYNC 3 Power Supply Synchronization Clock (Output) - The PWM synchronized clock to the
switch mode power supply.
XTI 5 Crystal Oscillat or Input (Input) - Crystal Oscillator input or accepts an external clock
input signal that is used to drive the internal PWM core logic.
XTO 6 Crystal Oscillator Output (Output) - Crystal Oscillator output.
SYS_CLK 8 External System Clock (Output) - Clock output. This pin provides a divided down clock
derived from the XTI input.
DAI_MCLK 9 Digital Audio Input Master Clock (Input) - Master audio clock.
DAI_SCLK 10 Digital Audio Input Serial Clock (Input) - Serial clock for the Digital Audio Input Inter-
face. The clock frequency is a multiple of the Left/Right Clock running at Fs.
DAI_LRCK 11 Digital Audio Input Left/Right Clock (Input) - Determines which channel, Left or Right,
is currently active on the serial audio data line. The rate is determined by the sampling fre-
quency Fs.
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
12
13
14 Digital Audio Input Serial Data (Input) - Input for two’s complement serial audio data.
MUTE 20 Mute (Input) - The device will perform a hard mute on all channels. All internal registers
are not reset to their default settings.
SCL/CCLK 21 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an
external pull-up resistor to the logic inte rface voltage in I²C mode as shown in the Typical
Connection Diagram.
SDA/CDOUT 22 Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an
external pull-up resistor to the logic interface voltage, as shown in the Typical Connection
Diagram.; CDOUT is the output data line for the control port interface in SPI mode.
AD1/CDIN 23 Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C
mode.;CDIN is the input data line for the control port inter face in SPI mode.
AD0/CS 24 Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in
I²C mode; CS is the chip select signal in SPI mode.
INT 25 Interrupt Request (Output) - CMOS or open-drain interrupt request ou tput. This pin is
driven to the configu red active state to indicate that the PWM Controller has status data
that should be read by the host.
RST 26 Reset (Input) - The device enters a low power mode and all internal registers ar e re set to
their default settings when low.
GPIO6 29 General Purpose Input , Output (Input/Output) - This pin is configured as an input follow-
ing a RST condition. It can be configur ed as a general purpose input or outp ut which can
be individually controlled by the Host Controller.
GPIO5 30 General Purpose Input , Output (Input/Output) - This pin is configured as an input follow-
ing a RST condition. It can be configur ed as a general purpose input or outp ut which can
be individually controlled by the Host Controller.
GPIO4 31 General Purpose Input , Output (Input/Output) - This pin is configured as an input follow-
ing a RST condition. It can be configur ed as a general purpose input or outp ut which can
be individually controlled by the Host Controller.
18 DS633F1
CS44600
GPIO3 32 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow-
ing a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
GPIO2 33 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow-
ing a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
GPIO1 34 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow-
ing a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
GPIO0 35 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow-
ing a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
PSR_MCLK 49 Power Supply Rejection Master Clock (Output) - Master audio clock for external PSR
ADC (CS4461).
PSR_DATAL 50 Power Supply Rejection Input Serial Data (Input) - Input for serial audio data from
external PSR ADC (CS4461).
PSR_SYNC 51 Power Supply Rejection Sync Clock (Input) - Synchronization signal for external PSR
ADC (CS4461).
PSR_RESET 52 Power Supply Rejection Reset (Output) - The reset pin for the external Power Sup ply
Rejection circuitry.
PSR_EN 2 Power Supply Rejection Enable (Output) - T he enable pin for the external Po wer Supply
Rejection circuitry.
PWMOUTA1+
PWMOUTA1-
PWMOUTB1+
PWMOUTB1-
PWMOUTA2+
PWMOUTA2-
PWMOUTB2+
PWMOUTB2-
PWMOUTA3+
PWMOUTA3-
PWMOUTB3+
PWMOUTB3-
64
63
61
60
58
57
55
54
47
46
44
43
PWM Output (Output) - PWM control signals for the Class D amplifier backend.
VDX 7 Crystal Power (Input) - Positive power supply for the Crystal section.
VD 19, 27 Digital Power (Input) - Positive power supply for the digital section.
VLC 17 Host Interface Power (Input) - Determines the required signal level for the digital
input/output signals for the host interface.
VLS 16 Digit al Audio Interface Power (Input) - Dete rmines the required signal level for the dig ital
input signals for the dig i tal audio interf ac e.
VDP 39, 45,
56, 62 PWM Interface Power (Input) - Determines the required signal level for the digital
input/output signals for the PWM and GPIO interface.
GND
1, 4,
18, 28,
36, 42,
48, 53,
59
Digital Ground (Input) - Ground reference for digital circuits.
DS633F1 19
CS44600
2.1 I/O Pin Characteristics
Signal Name Power
Rail I/O Driver Receiver
RST VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible.
SCL/CCLK VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis.
SDA/CDOUT VLC Input /
Output 2.5-5.0 V,
CMOS/Open Drain 2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis.
AD0/CS VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-up.
AD1/CDIN VLC Input - 2.5 V and 3.3/5 .0 V TTL Compatible, Internal pull-up.
INT VLC Output 2.5-5.0 V,
CMOS/Open Drain -
MUTE VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible.
DAI_SDINx VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible.
DAI_SCLK VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible.
DAI_LRCK VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible.
DAI_MCLK VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible.
SYS_CLK VLS Output 2.5-5.0 V, CMOS -
XTI VDX Input - 2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-down.
XTO VDX Output - -
GPIOx VDP Input /
Output 3.3/5.0 V,
CMOS/Open Drain 3.3/5.0 V TTL Compatible.
PWMOUTAx+/- VDP Output 3. 3/ 5.0 V, CMOS -
PWMOUTBx+/- VDP Output 3.3/ 5.0 V, CMOS -
PSR_MCLK VDP Output 3. 3/ 5.0 V, CMOS -
PSR_SYNC VDP Input - 3.3/5.0 V TTL Compatible, Internal pull-up.
PSR_DATA VDP Input - 3.3/5.0 V TTL Compatible, Internal pull-up.
PSR_EN VDP Output 3.3/5.0 V, CMOS -
PSR_RESET VDP Output 3.3/5.0 V, CMOS -
PS_SYNC VDP Output 3.3/5.0 V, CMOS -
20 DS633F1
CS44600
3. TYPICAL CONNECTION DIAGRAMS
VD PWMOUTA1+
PWMOUTA1-
PWMOUTB1+
PWMOUTB1-
VLC
0.1 µF
+2.5 V
to +5.0 V
SCL/CCLK
SDA/CDOUT
AD1/CDIN
RST
2 kΩ
2 k Ω
Note: Resistors are required for
I²C control port operation
See
Note
DAI_SDIN1
DAI_SDIN3
DAI_SDIN2
DAI_LRCK
DAI_SCLK
AD0/CS
INT
Digital
Audio
Processor
Micro-
Controller
GND
DAI_MCLK
PWM IN1 OUT1
CONTROL
VD
PWMOUTA2+
PWMOUTA2-
PWMOUTB2+
PWMOUTB2-
PWMOUTA3+
PWMOUTA3-
PWMOUTB3+
PWMOUTB3-
PSR_DATA
PSR_SYNC
PSR_MCLK
CS4461
ADC
Power Supply Rail
Front Left
Surr. Le ft
Surr. Right
Center
Subwoofer
SYS_CLK
GPIO1
GPIO3
GPIO5
PSR_RESET
PSR_EN
PS_SYNC Power Supply Sync Clo ck
MUTE
STATUS
VDX
PWM IN2 OUT2
CONTROL Front Right
STATUS
PWM IN3 OUT3
CONTROL STATUS
PWM IN4 OUT4
CONTROL STATUS
PWM IN5 OUT5
CONTROL STATUS
PWM IN6 OUT6
CONTROL STATUS
GPIO0
GPIO6
Optional
GPIO2
GPIO4
XTAL
24.576 MHz
to 54 MHz XTI
XTO
VLS
+2.5 V +
10 µF 0.1 µF
0.1 µF
0.01 µF
0.01 µF
+3.3 V to
+5.0 V 0.1 µF 0.01 µF
+2.5 V to
+5.0 V 0.1 µF 0.01 µF
+3.3 V to +5.0 V
VDP
0.01 µF
10 µF
0.1 µF
0.01 µF
0.1 µF
0.01 µF
0.1 µF
0.01 µF
0.1 µF
Figure 11. Typi cal Full-Bridge Connection Diagram
CS44600
DS633F1 21
CS44600
GND
PSR_DATA
PSR_SYNC
PSR_MCLK
CS4461
ADC
Power Supply Rail
PSR_RESET
PSR_EN
PS_SYNC Power Supply Sync Clock
Optional
PWMOUTA1+
PWMOUTA1-
PWMOUTB1+
PWMOUTB1-
PWMOUTA2+
PWMOUTA2-
PWMOUTB2+
PWMOUTB2-
GPIO3
GPIO4
Front Left
PWM IN1
PWM IN2
OUT1
OUT2
CONTROL
STATUS
PWM IN1
PWM IN2
OUT1
OUT2
CONTROL
STATUS
PWMOUTA3+
PWMOUTA3-
PWMOUTB3+
PWMOUTB3-
GPIO5
PWM IN1
PWM IN2
OUT1
OUT2
CONTROL
STATUS
Front Right
Surr. Left
Surr. Right
Center
Subwoofer
GPIO0
GPIO1
GPIO2
VD
VLC
0.1 µF
+2.5 V
to +5.0 V
SCL/CCLK
SDA/CDOUT
AD1/CDIN
RST
2 kΩ
2 k Ω
Note: Resistors are required for
I²C control port operation
See
Note
DAI_SDIN1
DAI_SDIN3
DAI_SDIN2
DAI_LRCK
DAI_SCLK
AD0/CS
INT
Digital
Audio
Processor
Micro-
Controller
DAI_MCLK
VD
SYS_CLK
MUTE
VDX
XTAL
24.576 MHz
to 54 MHz XTI
XTO
VLS
+2.5 V +
10 µF 0.1 µF
0.1 µF
0.01 µF
0.01 µF
+3.3 V to
+5.0 V 0.1 µF 0.01 µF
+2.5 V to
+5.0 V 0.1 µF 0.01 µF
+3.3 V to +5.0 V
VDP
0.01 µF
10 µF
0.1 µF
0.01 µF
0.1 µF
0.01 µF
0.1 µF
0.01 µF
0.1 µF
Figure 12. Typical Half-Bridge Connection Diagram
CS44600
22 DS633F1
CS44600
4. APPLICATIONS
4.1 Overview
The CS44600 is a multi-channel digital-to-PWM Class D audio system controller including interpolation,
sample rate conversion, half- and full-bridg e PWM driver outputs, and power supply rej ection feedback in a
64-pin LQFP package. Th e ar chitecture u ses a d irect- to-di gital approach that maintains digi tal signal integ-
rity to the final output filter, minimizing analog interference effects which negatively affect system perfor-
mance.
The CS44600 integrates on-chip sample rate conversion, digital volume control, peak detect with volum e
limiter, de-emp hasis, pr ogramm able inte rrupt con ditions, a nd the ab ility to ch ange th e PWM switch rate to
eliminate AM frequency interference. The CS44600 also has a programmable load compensation filter,
which allows the speaker load to vary while the output filter remains fixed, maintaining a flat frequency re-
sponse. For single-ended half-bridge applications PWM Popguard® reduces the t ransient po ps and clicks
and realtime power supply fee dback reduces noise coupling from the power supply. Th e PWM amplifier can
achieve greater than 90% efficiency. This efficiency provides for a smalle r device pack age, less hea t sink
requirements, and smaller power supplies.
The CS44600 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise
such as A/V receivers, DVD receivers, digital speaker, and automotive audio systems.
4.2 Feature Set Summary
Core Features
• 2.5 V digital core voltage, VD.
• VLC voltage pin for host interface logic levels between 2.5 V and 5.0 V.
• VLS voltage pin for digital audio interface logic levels between 2.5 V and 5.0 V.
• VDP voltage pin for PWM backend interface logic levels between 3.3 V and 5.0 V.
• VDX voltage pin for clock input signals between 2.5 V and 5.0 V.
Clocking
• Minimum of 128Fs DAI_MCLK for DAI serial interface.
• DAI interface uses automatic detection of LRCK/MCLK ratio to configure internal DAI/SRC clocks.
• All PWM Processing clocks generated internally via:
– An external crystal - 24.576 MHz to 54 MHz, or
– XTI input pin capable of supporting a clock signal at the VDX voltage level.
• Programmable divide of XTI by 1, 2, 4, 8 for SYS_CLK output.
• Programmable divide of XTI by 32, 64, 128, 256 for PS_SYNC (power supply synchronization signal).
Digital Audio Playback
• Supports 32 k Hz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz sample frequencies.
• High performance sample rate converter.
• 16, 20 and 24 bit audio sample lengths.
• De-emphasis for 32 kHz, 44.1 kHz, 48 kHz.
DS633F1 23
CS44600
• Digital volume control with soft ramp.
• Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB steps.
• Master volume attenuation; +24 to -127 dB in 0.25 dB steps.
• Peak Detect and Volume Limiter with pro grammable attack and release rates.
• Signal-clipping interrupt indicator.
Additional Features
• Contains a two-stage digital output filter for speaker impedance compensation.
• Provides 7 pr ogram mab le GPIO pin s with inte rrupt ge nera tion for ea sily inter facin g to a variety of com-
monly available power state parts. Interrupts can be masked.
• Selectable over-sample rate for increased audio bandwidth.
• Power supply clock output, PS_SYNC, with programmable divider
4.3 Clock Generation
The sources for internal clock generation for the PWM processing are as follows:
• FsIn Domain:
– DAI_MCLK, minimum 128Fs
• FsOut Domain:
– XTI/XTO (Fundamental or 3rd overtone crystal), or
– Clock signal on XTI (VDX is used to set logic voltage level)
DAI_SCLK
DAI_SDINx
Digital Audio
Input Port
DAI_MCLK
DAI_LRCK
Ratio Detect
SYS_CLK
XTI
XTO
PWM Engine
VOL
mute
PEAK
DETECT
SRC 2-pole Load
Compensation
Filter
128Fs
LIMITER
Multibit
Σ∆
Modulator
Σ
Master
Volume
Channel
Volume
x2
Over Sample
(OSRATE)
Delay
Delay
XTAL /
CLKIN
1,2,4,8
Clock Control
PWM_MCLK
MOD_MCLK
SRC_MCLK (128Fs)
PSR
Feedback
PWM_OUT+
PWM_OUT-
FsIn FsOut
1, 1.5, 2,
3, 4, 6, 8
AM Freq. Hop
(AM_FREQ_HOP)
2.25 1,1.5,
2,4
Over Sample
(OSRATE)
De-
Emphasis
Figure 13. CS44600 Data Flow Diagram (Single Channel Shown)
24 DS633F1
CS44600
4.3.1 FsIn Domain Clocking
Common DAI_MCLK frequencies and sample rates are shown in Table 1.
4.3.2 FsOut Domain Clocking
To ensure the highest quality conversion of PWM signals, the CS44600 is capable of operating from a
fundamental mode or 3rd overtone crystal, or a clock signal attached to XTI, at a frequency of 24.576 MHz
to 54 MHz. If XTI is being directly driven by a clock signal, XTO can be left floating or tied to ground
through a pull-down resistor and the internal oscillator should be powered down using the PDN_XTAL bit
in register 02h.
Mode
(sample-rate range) Sample
Rate
(kHz)
DAI_MCLK (MHz)
DAI_MCLK/LRCK Ratio −> 256x 384x 512x 768x 1024x
Single Speed
(4 to 50 kHz) 32 8.1920 12.2880 16.3840 24.5760 32.7680
44.1 11.2896 16.9344 22.5792 33.8688 45.1584
48 12.2880 18.4320 24.5760 36.8640 49.1520
DAI_MCLK/LRCK Ratio −> 128x 192x 256x 384x 512x
Double Speed
(50 to 100 kHz) 64 8.1920 12.2880 16.3840 24.5760 32.7680
88.2 11.2896 16.9344 22.5792 33.8688 45.1584
96 12.2880 18.4320 24.5760 36.8640 49.1520
DAI_MCLK/LRCK Ratio −> 64x 96x 128x 192x 256x
Quad Speed
(100 to 200 kHz) 176.4 n/a n/a 22.5792 33.8688 45.1584
192 n/a n/a 24.5760 36.8640 49.1520
Table 1. Common DAI_MCLK Frequencies
Y1 C1
C2
XTI
XTO
Figure 14. Fundamental Mode Crystal Configuration
DS633F1 25
CS44600
Appropriate clock dividers for each functional block and a programmable divider to support an output for
switched-mode power supply synchronization are provided. The clock generation for the CS44600 is
shown in the Figure 16.
Y1
L1
C3
C1
C2
XTI
XTO
Figure 15. 3rd Overtone Crystal Config uration
PWM_MCLK
SRC_MCLK
XTO
XTI
MOD_MCLKSYS_CLK
PS_SYNC
PWM Master
Clock Di vi der
Syst em Cloc k
Divider
Power Supply
Sync. Divider
PWM Modulator
Clock Di vi der
Sample Rate Converter
Clock Di vi der
Figure 16. CS44600 Internal C lo ck Generation
26 DS633F1
CS44600
4.4 FsIn Clock Domain Modules
4.4.1 Digital Audio Input Port
The CS44600 interfaces to an external Digital Audio Processo r vi a the Digi ta l Audio Input serial po rt, the
DAI serial port. The DAI port has 3 stereo data inputs with support for I²S, left-justified and right-justified
formats. The DAI port operates in slave operation only, where DAI_LRCK, DAI_SCLK and DAI_MCLK are
always inputs. The signal DAI_LR CK must be equal to the sample rate, Fs and must be synchronously
derived from the supplied master clock , DAI_MCLK. The serial bit clock, DAI_SCLK, is used to sample
the data bits and m ust be synch ro no u s ly deriv ed from the master clock.
DAI_SDIN1, DAI_SDIN2, and DAI_SDIN3 are the serial data input pins supplying the associated internal
PWM channel modulators. Th e seri al data interfa ce format selection (left-justified, right-justified, I²S, one
line mode, or TDM) for the DAI serial port data input pins is configured using the appropriate bits in the
register “M isc. Configuration (address 04h)” on pag e 52. The serial a udio data is presented in 2's comple-
ment binary form with the MSB first in all formats.
When operated in One Line Data Mode, 6 channels of PWM data are input on DAI_SDIN1. In TDM mode,
all 6 channels are multiplexed onto the DAI_SDIN1 data line. Table 2 outlines the serial port channel al-
locations.
The DAI digital audi o serial ports support 6 fo rmats with varying bit depths from 16 to 24 as shown in Fig-
ure 17, Figure 18, Figure 19, Figure 20, Figure 21 and Figure 22. These formats are selected using the
configuration bits in the “Misc. Configuration (address 04h)” on page 52.
Serial Dat a Input s Dat a mode Channel Assignment s
DAI_SDIN1 Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM
PWMOUTA1(left channel)/PWMOUTB1(right channel)
PWMOUTA1/A2/A3/B1/B2/B3
PWMOUTA1/A2/A3/B1/B2/B3
DAI_SDIN2 Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM
PWMOUTA2(left channel)/PWMOUTB2(right channel)
not used
not used
DAI_SDIN3 Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM
PWMOUTA3(left channel)/PWMOUTB3(right channel)
not used
not used
Table 2. DAI Serial Audio Port Channel Allocations
DS633F1 27
CS44600
4.4.1.1 I²S Data Format
For I²S, data is received most si gnificant bit first, one DAI_SCLK delay after the transition of DAI_LRCK,
and is valid on the rising edge of DAI_SCLK. For the I²S format, the left ch annel data is presented wh en
DAI_LRCK is low; the right channel data is presented when DAI_LRCK is high.
4.4.1.2 Left-Justified Data Format
For left-justified format, data is received most significant bit first on the first DAI_SCLK after a DAI_LRCK
transition and is valid on the rising edge of DAI_SCLK. For the left-justified format, the left channel data
is presented when DAI_LRCK is high and the right channel data is presented when DAI_LRCK is low.
Left Channel Right Channel
DAI_SDINx +3 +2 +1+5 +4
-1 -2 -3 -4 -5 +3 +2 +1+5 +4
-1 -2 -3 -4
MSB MSB
LSB LSB
DAI_LRCK
DAI_SCLK
Figure 17. I²S Serial Audio Formats
I²S Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample SCLK Rates
16 32, 48, 64, 128, 256 Fs
18 to 24 48, 64, 128, 256 Fs
DAI_LRCK
DAI_SCLK
Left Channel Right Channel
DAI_SDINx +3 +2 +1+5 +4
-1 -2 -3 -4 -5 +3 +2 +1+5 +4
-1 -2 -3 -4
MSB LSB MSB LSB
Figure 18. Left-Justified Serial Audio Formats
Left-Justified Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample SCLK Rate(s)
16 32, 48, 64, 128, 256 Fs
18 to 24 48, 64, 128, 256 Fs
28 DS633F1
CS44600
4.4.1.3 Right-Justified Data Format
In the right-justified format, data is received most significant bit first and with the least significant bit pre-
sented on the last DAI_SCLK before the DAI_LRCK transition and is valid on the rising edge of
DAI_SCLK. For the right-justified format, the left channel data is presented when DAI_LRCK is high and
the right channel data is pr esented when DAI_LRCK is low. Eith er 16 bits per sample or 24 bits per sam-
ple are supp orted.
4.4.1.4 One Line Mode #1
In One Line mode #1 format, data is received most significant bit first on the first DAI_SCLK after a
DAI_LRCK trans ition and is valid on the rising e dge of DAI_SC LK. DAI_SCLK must operate at a 128Fs
rate. DAI_LRCK identifies the start of a n ew frame a nd is eq ua l to th e sa mple peri od. DAI_L RCK is sa m-
pled as valid on the same clock edge a s the most sign ificant bit of the first data sample and must b e held
high for 64 DAI_SCLK periods. Each time slot is 20 bits wide, with the valid data sample left-justified within
the time slot. Valid data lengths are 16, 18, or 20 bits. Valid samples rates for this mode are 32 kHz to
96 kHz.
Left Channel Right Channel
6543210987
15 14 13 12 11 10 6543210987
15 14 13 12 11 10
DAI_SDINx
DAI_LRCK
DAI_SCLK
Figure 19. Right-Justified Serial Audio Formats
Right-Justified Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample SCLK Rate(s)
16 32, 48, 64, 128, 256 Fs
24 48, 64, 128, 256 Fs
PWMOUTB3
DAI_LRCK
DAI_SCLK
LSBMSB
20 clks
64 clks 64 clks
LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB
20 clks 20 clks 20 clks 20 clks 20 clks
DAI_SDIN1
PWMOUTA1 PWMOUTB1PWMOUTA2 PWMOUTB2PWMOUTA3
Left Channels Right Channels
Figure 20. One Line Mode #1 Serial Audio Format
DS633F1 29
CS44600
4.4.1.5 One Line Mode #2
In One Line mode #2 format, data is received most significant bit first on the first DAI_SCLK after a
DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 256 Fs
rate. DAI_LRCK identifie s the start of a new frame and is equal to the sample per iod. DAI_LRCK is sam-
pled as valid on the same clock ed ge as the most significant bit of the first data sample and must be held
high for 128 DAI_SCLK periods. Each time slot is 24 bits wide, with the valid data sample left-justified with-
in the time slot. Valid da ta lengths are 16, 18, 20 , or 24 bits. Valid samples rates for this mode are 32 kHz
to 96 kHz.
4.4.1.6 TDM Mode
In TDM mode format, data is received most significant bit first on the first DAI_SCLK after a DAI_LRCK
transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 256 Fs rate.
DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sampled
as valid on the proceeding clock e dge as the most significant bit of the first dat a sample and mu st be held
valid for at least 1 DAI_SCLK period. Each time slot is 32 bits wide, with the valid data sample left-justified
within the time slot. Vali d data lengths are 16, 18 , 20, 24 or 32 bits. Valid samples rates for this mode are
32 kHz to 96 kHz.
PWMOUTB3
DAI_LRCK
DAI_SCLK
LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB
DAI_SDIN1
PWMOUTA1 PWMOUTB1PWMOUTA2 PWMOUTB2PWMOUTA3
128 clks 128 clks
24 clks 24 clks 24 clks 24 clks 24 clks 24 clks
Left Channels Right Channels
Figure 21. One Line Mode #2 Serial Audio Format
PWMOUTB2
DAI_LRCK
DAI_SCLK
LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB
DAI_SDIN1
PWMOUTA1 PWMOUTA2 PWMOUTB1PWMOUTA3
256 clks
32 clks 32 clks 32 clks 32 clks 32 clks 32 clks
LSBMSB
PWMOUTB3
32 clks 32 clks
Figure 22. TDM Mode Serial Audio Format
30 DS633F1
CS44600
4.4.2 Auto Rate Detect
The CS44600 will automatically determine the incoming sample rate, DAI_LRCK, to master clock,
DAI_MCLK, ratio and configure the app ropriate inter nal cl oc k di vid er su ch t hat t he sa mple rate conv ert or
receives the required clock ra te. A minimum DAI_MCLK rat e of 128Fs is required for proper operation.
The supported DAI_MCLK to DAI_LRCK ratios are shown in Table 1 on page 26.
4.4.3 De-Emphasis
The CS44600 includes on-chip dig ital de-emphasis filters. The de-empha sis feature is included to accom-
modate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.
Figure 23 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale pro-
portionally with changes in sample rate, Fs. The required de-emphasis filter for 32 kHz, 44.1 kHz, or
48 kHz is selected via the de-emphasis control bits in “Misc. Configuration (address 04h)” on page 52.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.1 83 kHz 10.61 kHz
Figure 23. De-Emphasis Curve
DS633F1 31
CS44600
4.5 FsOut Clock Domain Modules
4.5.1 Sample Rate Converter
One of the characteristics of a PWM amplifier is that the frequency content of out-of-band noise generated
by the modulator is depende nt on the PWM switching frequency. The power stag e external LC and snub-
ber filter component values are based on this switching frequency. To accommodate input sample rates
ranging from 32 kHz to 192 kHz the CS44600 utilizes a Sample Rate Converter (SRC) and several clock-
ing modes that keep the PWM switching frequency fixed.
The SRC supports a range of sample rate conversion to upsample rates from 32 kHz to 192 kHz to a fixed
FsOut sample rate. This is typically 384 kHz for most audio applications. The SRC also allows the PWM
modulator output to be independent of the input clock jitter since the output of the SRC is clocked from a
very stable crystal or oscillator. This results in very low jitter PWM output and higher dynamic range.
4.5.2 Load Compensation Filter
To accommodate varying speaker impedances, the CS44600 incorporates a 2-pole load compensation
filter to adjust the effective frequency response of the on-card L/C de-modulatio n filter. The frequ ency re-
sponse of the 2-pole inductor/capacitor filter used on the board to filter out the high-frequency PWM
switching clock is highly dependant on the resistive load (speaker) attached.
If the L/C filter implemented was designed for a low impedance load (4 Ω speaker), but an 8 Ω speaker
was attached, the frequency response would have a large peaking near the resonant frequency of the
L/C. The peaking usually starts at ar ound 15 kHz, with about a +4 dB of gain at around 20 kHz. This phe-
nomenon will cause the system to not meet the frequency response requirements as specified by Dolby
Labs.
By using the programmable 2-po le load compensation filter, the overall frequency response of the system
can be modified to cut the amoun t of peaking. The 2 poles of the filter are ind ependently configurable and
are concatenated to form the overall filter response. The first filter is defined as a coarse setting. This filter
should be programme d to provide most of the attenuation of the peaking. The second filter, defined as th e
fine adjust, is used to achieve incremental improvements to the overall frequency response. Table 3
shows example register settings based on an output filter that has been designed for a 4 Ω load imped-
ance. See “Chann el Compensation Filter - Coarse Ad just (CHXX_CORS[5:0])” on page 62 and “Channel
Compensation Filter - Fine Adjust (CHXX_FINE[5:0])” on page 63.
4.5.3 Digital Volume and Mute Control
The CS44600 provides two levels of vo lume control. A Master Volume Control Register is used to set the
volume level across all PWM channels. The register value, which selects a volume range of +24 dB to -
127 dB in 0.25 dB steps, is used to control the overall volume setting of all the amplifier channels. Volume
control changes ar e program mable to ramp in increme nts of 0.125 dB at a variable rate controlled by the
SZC[1:0] bits in “Volume Control Configuration (address 06h)” on page 55.
Each PWM channel’s output level is controlled via a Chann el Volum e Contro l reg iste r ope ratin g over th e
range of +24 dB to -127 dB attenuation with 0.25 dB resolution. See “Channel XX Volume Control - Inte-
Load Impedance Coarse Filter Setting Fine Filter Setting
6Ω-1.2 dB 0 dB
8Ω-1.8 dB 0 dB
16 Ω-3.4 dB 0 dB
Table 3. Load Compensation Example Settings
32 DS633F1
CS44600
ger (addresses 09h - 10h)” on page 58. Volume control changes are programmable to ramp in increments
of 0.125 dB at a variable rate controlled by the SZC[1:0] bits.
Each PWM channel output can be independently muted via mute control bits in the register “Channel Mute
(address 13h)” on page 60.
When enabled, each CHXX_MUTE bit attenuates the corr esponding PWM channel to its m aximum value
(-127 dB). When the CHXX_MUTE bit is disabled, the corresponding PWM channel returns to the atten-
uation level set in the Volume Control register. The attenuation is ramped up and down at the rate spec-
ified by the SZC[1:0] bits.
4.5.4 Peak Detect / Limiter
The CS44600 has the ability to limit the maximum signal amplitude to prevent clipping. The “Peak Limiter
Control Register (address 15h)” on page 60 is used to configure the peak detect and limiter engines’ op-
eration. Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the “Lim-
iter Attack Rate (address 16h)” on page 61. The release rate is determined by the “Limiter Release Rate
(address 17h)” on page 61.
4.5.5 PWM Engines
There are three ste reo PWM Engines: PWM_ENG_1, PWM_ENG_2, and PWM_ENG_3. Each PWM can
handle one stereo pair and connects to a driver or a pair of drivers, depending on the output configuration.
Each PWM Engine receives the master clock, PWM_MCLK, from the Clock Control block, and the asso-
ciated channel data and audio sample timings from the Sample Rate Converter.
The “ PWM Conf iguration Register ( addre ss 31h) ” on page 68 is used to configure the PWM engines’ op-
eration. This register controls the parameters of the PWM engines and can only be changed while the
PWM engines are in the power down state.
Features:
• Up to 6 channel supp ort
• 64 Quantizat i on leve ls
• PSRR compensation feedback
• Programmable Over Sampling - interpolate times 2 (2x) or filter by-pass. By-pass is intended for
384 kHz (single-speed) PWM switch rate sup port. The interpolate 2x filter is used to upsam ple the data
to support a PWM switch rate of 768 kHz (double speed mode). This enables the output frequency re-
sponse to extend past 20 kHz when the DAI sample rate is 96 kHz or 192 kHz.
• Program ma b le re gis ter s to mo ve PWM ed ge s for dela y adjustment. This lowers the overall noise con-
tribution by allowing each PWM edge to switch at different times.
• Programmable Modulation Setup
– Min/Max PWM pulse width allowed
– Programmable Modulation index.
The table below shows the available settings for the PWM Engine for a 384 kHz/768 kHz or
421.875 kHz/843.75 kHz PWM Fswitch rate verses the supp or te d F sin sam p le ra te s us ing th e SRC with
a maximum PWM_ MC LK of 49.1 5 2 MHz/54 MHz.
DS633F1 33
CS44600
4.5.6 Interpolation Filter
The times 2 (2x) interpolation filter is part of the Quantizer and is used to up sample the data to support
a higher PWM switch rate. The interpolator is controlled by the OSRATE bit in the “PWM Configuration
Register (address 31h)” on page 68 and employs digital filtering to provide high quality interpolation.
4.5.7 Quantizer
The quantizer takes the input audio data at a typical 384 kHz or 768 kHz rate (dependi ng on whether the
2x Interpolator is on or not) from the Interp olator as input. When PSRR is ena bled, the quantizer take s the
input from PSRR Decimator and uses it to correct for power_supply noise. It also provides protection
through min/max pu lse limiting har d war e to gener ate ou tp uts tha t wou ldn’t violate min imum pulse widths
required at the PWM drive r s. Its ste reo outp u ts ar e runn in g at th e PWM switch rat e.
4.5.8 Modulator
Each output from the Quantizer goes to the Modulator. The Modulator takes the parallel input data at a
384 kHz or 768 kHz, depen ding on the setting of the OSRATE bit, a nd changes the pa rallel data to seri al,
one-bit outputs. The result is modulated pulses at the selected switch rate with 64 level resolution. The
modulator maintains low frequency audio signals, allowing the output to reproduce all low frequency audio
content down to 0 Hz.
4.5.9 PWM Outputs
The Modulators outputs are followed by the PWM Configuration block. These signals are routed through
delay control blocks where they generate two outputs each. These final outputs are modulated pulses run-
ning at the PWM switch rate as determined by the settings shown in Table 4.
Circuitry in the PWM Configuration block gu ar antees, that no pulses shorter th an the min imum pulse ar e
generated. The minimum pulse width is configured using the MIN_PULSE[4:0] bits in the “PWM Minimum
Pulse Width Register (address 32h)” on page 69.
The PWM Configuration block also provides the PWM outp ut signal delay mechanism. Adjusting the out-
puts’ delays allows for managing the switching noise between channels, as well as differential signal
noise. The “PWMOUT Delay Register (address 33h)” on page 70 specify the delay amount for each PWM
Output. The delay is measured in periods of PWM_MCLK.
Table 4. Typ ic al PWM Switch Rate Settings
Fsin (kHz) Fsout
(
kHz
)
usi ng S RC Quant Level OS RATE PW M
Switch Rate
(kHz)
Re qui red X TAL
or SYS_CLK
(MHz)
64 1 384 24.576
64 2 768 49.152
64 1 421.875 27.000
64 2 843.75 54.000
32, 44.1, 48, 88. 2, 96,
176.4, 192 384
32, 44.1, 48, 88. 2, 96,
176.4, 192 421.875
34 DS633F1
CS44600
4.5.10 Power Supply Rejection (PSR) Real-Time Feedback
Inherent to most Class D power amplifier so lutions is the requireme nt for a clean and well-regu lated high
voltage power supply. Any noise or tones present on the power rail will couple through each channel’s
power MOSFET output device. These spurious di stortion components on the outp ut signal consist of dis-
crete tones, which can be a udible from the speaker, an d tones that modulate around the a udio signal be-
ing played.
To remove the re quirement for a well-re gulated power sup ply, and therefore reduce ove rall system costs,
the rejection of harmonic distortion from the power supply and tones coupled onto the power rail is ac-
complished by the patented power supp ly rejection realtime feedback. By using the CS4461 and associ-
ated attenuation circuitry, the scaled AC and DC components of the power supply rail are fed back into
the PWM modulator. All de lays through the feedback path have been minimize d such that th e noise can-
cellation is accomplished in real-time allowing for substantial noise rejection within the output audio signal.
See “Typical Connection Diagrams” on page 22 for examples on how to connect the external ADC
(CS4461) to the CS44600 for PSR feedback, “Recommended PSR Calibration Sequence” on page 44,
and the CS4461 datasheet.
DS633F1 35
CS44600
4.6 Control Port Description and Timing
The control port is used to access the registers, allowing the CS44600 to be configured for the desired op-
erational modes and formats. The operation of the control port may be completely asynchronous with re-
spect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is re quired.
The control port has 2 modes: SPI and I²C, with the CS44600 acting as a slave device. SPI mode is selected
if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C mode is
selected by connecting the AD0/CS pin through a resistor to V LC or GND, the reby permanently selecting
the desired AD0 bit address state.
4.6.1 SPI Mode
In SPI mode, CS is the CS44600 chip select signal, CCLK is the control port bit clock (input into the
CS44600 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the
output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling
edge.
Figure 24 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulle d high or low with a 47 kΩ resistor, if desired
There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement
after each byte is written, allowing block writes of successive registers. Autoincrem ent reads are not sup-
ported.
To read a reg ister , the M AP ha s to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or no t,
as desired. To begin a r ead, bring CS low, send out the chip address an d set the read/write bit (R/ W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high
impedance state).
MAP
MSB LSB
DATA
byte 1 byte n
R/W R/W
ADDRESS
CHIP
ADDRESS
CHIP
CDIN
CCLK
CS
CDOUT MSB LSB MSB LSB
1001111
1001111
MAP = Memory Address Pointer, 8 bits, MSB first
High Impedance
Figure 24. Control Port Timing in SPI Mode
36 DS633F1
CS44600
4.6.2 I²C Mode
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two leas t signific ant bits of the chip ad dres s and sh ould
be connected through a resistor to VLC or GND as desired. The state of the pins is sensed while the
CS44600 is being reset.
The signal timings for a read and write cycle are shown in Figure 25 and F igure 26. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop c ondition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS44600 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low
for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS44600,
the chip address field, which is the first byte sent to the CS44600, should match 10011 followed by the
settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Addr ess Pointer (MAP) which selects the register to be read or written. If the op-
eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto incre-
ment bit in MAP allows successive writes of consecutive registers. Each byte is separated by an
acknowledge bit. Th e ACK bit is output from the CS44600 after each input byte is read, and is input to the
CS44600 from the microcontroller afte r each transmitted byte. Autoin crement reads are not supported.
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As
shown in Figure 26, the write operation is aborted after the acknowledge for the MAP byte by sending a
stop condition. The following pseudocode illustrates an aborted write operation followed by a read oper-
ation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
4 5 6 7 24 25
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK STOP
ACKACKACK
1 0 0 1 1 AD1 AD0 0
SDA INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28
26
DATA +n
Figure 25. Control Port Timing, I²C Slave Mode Write
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START ACK
STOP
ACK
ACK
ACK
1 0 0 1 1 AD1 AD0 0
SDA 1 0 0 1 1 AD1 AD0 1
CHIP ADDRESS (READ)
START
INCR 6 5 4 3 2 1 0 7 0 7 0 7 0
NO
168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24 26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 26. Control Port Timing, I²C Slave Mode Read
DS633F1 37
CS44600
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Each byte is separated by an acknowledge bit.
4.6.3 GPIOs
The CS44600 GPIO pins will have the following features:
• Data directio n con tr ol.
• Programmable open-drain or push-pull driver when configured as an output pin.
• Maskable interrupt for GPIO[3:0] pins when set as a general purpose input.
• Level-sensitive or edge-trigger event selector for all GPIO pins.
4.6.4 Host Interrupt
The CS44600 has a comprehensive interrupt capability. The INT output pin is intended to drive the inter-
rupt input pin on the host microcontroller. The INT pin may be set to be active low, active high or active
low with an open-drain driver . This last mode is used for active low, wired-OR hook-ups, with multiple pe-
ripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status re gister de scription s. See “Inte r-
rupt Status (address 2Ah) (read only)” on page 64. Each source may be masked off through mask register
bits. In addition, each sou rce may be set to rising edge, falling edg e, or level sensitive. Combined with the
option of level sensitive or edge sensitive mode s within the microcontroller , many different configurations
are possible, depending on the needs of the equipment designer.
38 DS633F1
CS44600
5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT
The CS44600 require s a 2.5 V digital power supply for the core logic. In order to support a number of PWM backend
solutions, separate VDP po wer pins are provided to condition the interface sign als to support up to 5.0 V levels. The
VDP power pins control the voltage levels for all PWM interface signals, PSR interface signals and GPIO for control
and status.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capac-
itors are recommended. It is necessary to decouple the power supply by placing capacitors directly between the
power and groun d of the CS44600. The recommended pro cedure is to place the lowest value capacito r as close as
physically possible to each power pin. Deco upl ing capa citors sho uld be as nea r to th e pins o f the CS446 00 as p os-
sible, with the low value ceramic capacitor being the nearest and mounted on the same side of the board as the
CS44600 to minimize indu ctance effects.
Figure 27 shows the recommende d power supply decoupling layout. U1 is the CS44600. C2, C3, C6, C8, C10, C12,
C14, and C16 are 0.01 µF X7R capacitors. These should be placed as close as possible to their respective power
supply pins. C1, C4, C5, C7, C9, C11, C13, C15, and C17 are 0.1 µF X7R capa citors. C18 is a 10 µF ele ctrolytic
capacitor. Top and bottom ground fill should be used as much as possible around all components shown.
Figure 27. Recommended CS44600 Power Supply Decoupling Layout
DS633F1 39
CS44600
Figure 28 shows the recomme nded crystal circuit layout. U1 is the CS446 00. C1 and C2 are the VDX power supply
decoupling capacitors. Y1 is the crystal and C3, C4, L1 and C5 are the associated components for the crystal circuit.
L1 and C5 are only use d fo r 3rd overto ne crystals. C3 and C4 should have a C0G ( NPO) dielectric. Care should be
taken to minimize the distance between the CS44600 XTI/XTO pins and C3. Top and bottom ground fill should be
used as much as possible around and in between all crystal circuit components to minimize noise.
Figure 28. Recommended CS44600 Crystal Circuit Layou t
40 DS633F1
CS44600
Figure 29 shows the recomme nded PSR circuit layout. See the CS4461 datasheet for further details on the input
buffer and other associated external components. U1 is the CS4461 and U2 is the input buffer op-amp. All supply
decoupling should be placed as close as possible to their respective power supply pins. C4 should have a C0G
(NPO) dielectric and be placed as close as possible to the CS4461 AIN+/- pins. The CS4461 and input buffer should
be placed on the boar d b etween the CS446 00 an d th e high voltage power supply. The sens e poi nt of the high volt-
age power supply (the point at which the input buffer taps off of the high voltage powe r supply) sho uld be close to
the middle of the am plifier output channe ls. If the sense poin t is taken at either end of the amplifie r output channels,
inaccurate reading could occur due to localized channel disturbances causing noise on the high voltage power sup-
ply. Optimally, the high voltage power connector should also be placed in the middle of the amplifier output channels
Figure 29. Recommended PSR Circuit Layout
DS633F1 41
CS44600
5.1 Reset and Power-Up
Reliable power- up can be accomplished by keeping the device in reset until the power supplies, clocks, and
configuration pins are stable. It is also recommended that the RST pin be activated if the voltage supplies
drop below the recommended operating condition to prevent power-glitch- related issues.
When RST is low, the CS44600 enters a low-power mode and all internal states are reset, including the
control port and register s. When RST is high, the control p ort becomes operatio nal and the desired settings
should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control Register will then
cause the part to leave the low-power state an d be g i n op er at ion .
5.1.1 PWM PopGuard® Transient Control
The CS44600 uses PopGuard® technology to min imize the effects of output transients durin g power-up
and power-down. This technique reduces the audio transients commonly produced by half-brid ge, single-
supply amplifiers when implemented with external DC-blocking capacitors connected in series with the
audio outputs. Each PWM channel can individually be controlled for ramp-up and ramp-down cycles.
When the device is initially powered-up and configured for ramp-up, the PWMOUTxx outputs are clamped
to GND. Following a write of a 0 to the PDN_PWMxx bit in the PWM Channel Power Down Control (ad-
dress 03h) register, each output begins to increase the PWM duty cycle toward the bias voltage point. By
a speed set by the RAMP_SPDx bits, the PWMOUTxx outputs will ramp from 0 V (GND) and reach the
bias point (50% PWM duty cycle). This gradual voltage ramping allows time for the external DC-blocking
capacitor to charge to the bias voltage, minimizing the power-up transient.
To prevent an audib le transient at the next power- on, the DC-blocking capacitors must fu lly discharge be-
fore turning off the power. If full discharge does not occur, a transient will occur when the audio outputs
are initially clamped to GND.
To prevent transients at power-down, the user must first mute the outputs. When this occurs, audio output
ceases and the PWM duty cycle is approximately 50% duty cycle, which represents the mute condition.
Once the channels are powered down, the PWMOUTxx outputs slowly decrease the DC offset until it
reaches GND. The time required to reach GND is determined by the RAMP_SPDx bits. This allows the
DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may
be turned off, and the system is ready for the next power-on.
5.1.2 Recommended Power-Up Sequence
1. Hold RST low until the power supply and clocks are stable. In this state, all control port registers are
reset to th e default settings. The PWMOUTxx pins are driven low.
2. The SYS_CLK pin will output a divided-down clock of the signal attached to the XTI pin. If the MUTE
pin is held low, SYS_CLK is equal to the XTI frequency. If the MUTE pin is held high, then SYS_CLK
is equal to the XTI frequency divided by 2.
3. Bring RST high. The device will remain in a low power state and all registers will contain the specified
default value. The logic state of the MUTE pin will be latched and used to specify the clock divider for
SYS_CLK. The control port will be accessible at this time.
4. With the CS44600 in the power-down state, PDN bit is ‘1’b, set up the required PWM configuration
registers and volume control register s. Configure the GPIO pins for normal operation. Do not enable
the power stages at this time.
5. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b.
42 DS633F1
CS44600
6. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘11’b and
the required ramp speed, to initiate a ra mp cycle when the channel is powered on. Set
MIN_PULSE[4:0] to ‘00000’b.
7. Set the PDN bit to ‘0’b to take the CS44600 out of the power-down state.
8. Start all clocks on the DAI interface (DAI_MCLK, DAI_SCLK, DAI_LRCK). This will initiate the SRC to
begin the lock sequence. The SRC lock function can be configured to cause an interrupt condition
when lock has been completed. This will be indicated by an active INT signal.
9. Wait for the SRC to lock.
10.If using the PSR feedback, jump to “Recommended PSR Calibration Sequence” on page 44. When
finished, continue to step 12. If not using PSR feedback, continue to step 12.
11.Set the appropriate GPIO pin, or other control signal, to enable the power output stage.
12.Enable each channel’s PWM modulator by setting the PDN_PWMxx bit to ‘0’b. If full-bridged, go to
step 14. If single-ended (half-bridged), this will initiate a sequence which will slowly increase the DC
voltage, from 0V to Vpower÷2, across the AC coupling capacitor. This will eliminate the instantaneous
charge across the capacitor which would have caused an audible pop from the speaker.
13.Wait for the ramp-up sequence to complete. The ramp-up function can be configured to cause an
interrupt condition when the ramp period has completed. This will be indicated by an active INT signal.
Once the ramp-up sequence has completed, set the RAMP[1:0] bits to ‘01’b
14.For full-bridged power output stage configurations, the ramp-up sequence is not required. Enabling
the power output stage will not cause an audible pop from the speaker.
15.If using the PSR feedback, set the FEEDBACK_EN bit to ‘1’b.
16.Un-mute all active channels.
17. At this point, the CS44600 is ready to accept audio samples and begin playback.
5.1.3 Recommended PSR Calibration Sequence
1. Set the DEC_SHIFT[2:0]/DEC_SCALE[18: 0] co ef ficie nt (C PSR) to decimal 1.0 (register 35h = 22h,
36h = 00h, 37h = 00h).
2. Set the PSR_RESET bit to ‘1’b.
3. Set the PSR_EN bit to ‘1’b.
4. Set the PSR_EN bit to ‘0’b.
5. Read DEC_OUTD[23:0].
6. See Figure 30 to adjust the DEC_SHIFT[2:0]/DEC_SCALE[18:0] registers.
7. Continue Recommended Power-Up Sequence.
DS633F1 43
CS44600
5.1.4 Recommended Power-Down Sequence
1. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b.
2. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘01’b and
the required ramp speed, to initiate a ramp cycle when the channel is powered down.
3. Power down each channel’s PWM modula tor by setting the PDN_PWMxx bit to ‘1’b. If single-ended,
this will initiate a sequence which will slowly decrease the DC voltage, from Vpower÷2 to 0 V, across
the AC-coupling capacitor.
4. The ramp-down function can be configured to cause an interrup t condition when the ramp period has
completed. This will be indicated by an active INT signal.
5. Once the ramp-down se quence has completed , set the appr opriate GPIO pin, o r other control signal,
to power down the po we r ou tp ut stag e .
6. For full-bridged power output stage configurations, the ramp-down sequence is not required. Powering
down the power output stage will not cause an audible pop from the speaker.
7. Concurrently with the ramp-down sequence, if desired, stop all clocks on the DAI interface
(DAI_MCLK, DAI_SCLK, DAI_LRCK).
8. Set the PDN bit to ‘1’b to put the CS44600 in the power down state.
Set PSR_EN = 1b
Set PSR_EN = 0b
Read DEC_OUTD[23:0]
3FEF90h <
DEC_OUTD[23:0] <
400FFFh?
Done
DEC_OUTD[23:0] >
400FFFh?
YN
CPSR =CPSR - 9Bh
Set PSR_RESET = 1b
CPSR =CPSR + 9Bh
YN
Figure 30. PSR Calibration Sequence
44 DS633F1
CS44600
6. REGISTER QUICK REFERENCE
Addr Function 7 6 5 4 3 2 1 0
01h ID / Rev. CHIP_ID3 CHIP_ID2 CHIP_ID1 CHIP_ID0 REV_ID3 REV_ID2 REV_ID1 REV_ID0
page 48 default 1 1 0 0 0 0 0 1
02h Clock Config / Power
Control EN_SYS_CLK SYS_CLK_DIV1 SYS_CLK_DIV0 PWM_MCLK_DIV1 PWM_MCLK_DIV0 PDN_XTAL PDN_OUTPUT_MO
DE PDN
page 49. default 1 0 0 0 0 0 0 1
03h Chnl Power Down RESERVED RESERVED PDN_PWMB3 PDN_PWMA3 PDN_PWMB2 PDN_PWMA2 PDN_PWMB1 PDN_PWMA1
page 50. default 1 1 1 1 1 1 1 1
04h Misc. Config. DIF2 DIF1 DIF0 RESERVED AM_FREQ_HOP FREEZE DEM1 DEM0
page 51 default 0 0 1 0 0 0 0 0
05h Ramp Config RESERVED RESERVED RESERVED RAMP1 RAMP0 RESERVED RAMP_SPD1 RAMP_SPD0
page 52 default 0 0 0 0 0 0 0 1
06h Vol Control Config SNGVOL SZC1 SZC0 RESERVED MUTE_50/50 SRD_ERR SRU_ERR AMUTE
page 53 default 0 1 0 0 0 0 0 1
07h Master V ol. Control
- Integer MSTR_IVOL7 MSTR_IVOL6 MSTR_IVOL5 MSTR_IVOL4 MSTR_IVOL3 MSTR_IVOL2 MSTR_IVOL1 MSTR_IVOL0
page 55 default 0 0 0 0 0 0 0 0
08h Master V o l.
Control - Fraction RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED MSTR_FVOL1 MSTR_FVOL0
page 55 default 0 0 0 0 0 0 0 0
09h Channel A1 Vol.
Control - Integer CHA1_IVOL7 CHA1_IVOL6 CHA1_IVOL5 CHA1_IVOL4 CHA1_IVOL3 CHA1_IVOL2 CHA1_IVOL1 CHA1_IVOL0
page 57 default 0 0 0 0 0 0 0 0
0Ah Channel B1 Vol.
Control - Integer CHB1_IVOL7 CHB1_IVOL6 CHB1_IVOL5 CHB1_IVOL4 CHB1_IVOL3 CHB1_IVOL2 CHB1_IVOL1 CHB1_IVOL0
page 57 default 0 0 0 0 0 0 0 0
0Bh Channel A2 Vol.
Control - Integer CHA2_IVOL7 CHA2_IVOL6 CHA2_IVOL5 CHA2_IVOL4 CHA2_IVOL3 CHA2_IVOL2 CHA2_IVOL1 CHA2_IVOL0
page 57 default 0 0 0 0 0 0 0 0
0Ch Channel B2 Vol.
Control - Integer CHB2_IVOL7 CHB2_IVOL6 CHB2_IVOL5 CHB2_IVOL4 CHB2_IVOL3 CHB2_IVOL2 CHB2_IVOL1 CHB2_IVOL0
page 57 default 0 0 0 0 0 0 0 0
0Dh Channel A3 Vol.
Control - Integer CHA3_IVOL7 CHA3_IVOL6 CHA3_IVOL5 CHA3_IVOL4 CHA3_IVOL3 CHA3_IVOL2 CHA3_IVOL1 CHA3_IVOL0
page 57 default 0 0 0 0 0 0 0 0
0Eh Channel B3 Vol.
Control - Integer CHB3_IVOL7 CHB3_IVOL6 CHB3_IVOL5 CHB3_IVOL4 CHB3_IVOL3 CHB3_IVOL2 CHB3_IVOL1 CHB3_IVOL0
page 57 default 0 0 0 0 0 0 0 0
0Fh Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
default 00 000000
10h Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
default 00 000000
DS633F1 45
CS44600
11h Channel Vol. Con-
trol 1-Fraction CHB2_FVOL1 CHB2_FVOL0 CHA2_FVOL1 CHA2_FVOL0 CHB1_FVOL1 CHB1_FVOL0 CHA1_FVOL1 CHA1_FVOL0
page 57. default 0 0 0 0 0 0 0 0
12h Channel Vol. Con-
trol 2-Fraction RESERVED RESERVED RESERVED RESERVED CHB3_FVOL1 CHB3_FVOL0 CHA3_FVOL1 CHA3_FVOL0
page 57 default 0 0 0 0 0 0 0 0
13h Channel Mute RESERVED RESERVED CHB3_MUTE CHA3_MUTE CHB2_MUTE CHA2_MUTE CHB1_MUTE CHA1_MUTE
page 58 default 0 0 0 0 0 0 0 0
14h Channel Invert RESERVED RESERVED CHB3_INV CHA3_INV CHB2_INV CHA2_INV CHB1_INV CHA1_INV
page 58 default 0 0 0 0 0 0 0 0
15h Peak Limiter
Control RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED LIMIT_ALL LIMIT_EN
page 59 default 0 0 0 0 0 0 0 0
16h Limiter Attack Rate ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0
page 59 default 0 0 0 1 0 0 0 0
17h Limiter Release Rate RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0
page 60 default 0 0 1 0 0 0 0 0
18h Chnl A1 Comp.
Filter - Coarse Adj RESERVED RESERVED CHA1_CORS5 CHA1_CORS4 CHA1_CORS3 CHA1_CORS2 CHA1_CORS1 CHA1_CORS0
page 60 default 0 0 0 0 0 0 0 0
19h Chnl A1 Comp.
Filter - Fine Adj RESERVED RESERVED CHA1_FINE5 CHA1_FINE4 CHA1_FINE3 CHA1_FINE2 CHA1_FINE1 CHA1_FINE0
page 61 default 0 0 0 0 0 0 0 0
1Ah Chnl B1 Comp.
Filter - Coarse Adj RESERVED RESERVED CHB1_CORS5 CHB1_CORS4 CHB1_CORS3 CHB1_CORS2 CHB1_CORS1 CHB1_CORS0
page 60 default 0 0 0 0 0 0 0 0
1Bh Chnl B1 Comp.
Filter - Fine Adj RESERVED RESERVED CHB1_FINE5 CHB1_FINE4 CHB1_FINE3 CHB1_FINE2 CHB1_FINE1 CHB1_FINE0
page 61 default 0 0 0 0 0 0 0 0
1Ch Chnl A2 Comp.
Filter - Coarse Adj RESERVED RESERVED CHA2_CORS5 CHA2_CORS4 CHA2_CORS3 CHA2_CORS2 CHA2_CORS1 CHA2_CORS0
page 60 default 0 0 0 0 0 0 0 0
1Dh Chnl A2 Comp.
Filter - Fine Adj RESERVED RESERVED CHA2_FINE5 CHA2_FINE4 CHA2_FINE3 CHA2_FINE2 CHA2_FINE1 CHA2_FINE0
page 61 default 0 0 0 0 0 0 0 0
1Eh Chnl B2 Comp.
Filter - Coarse Adj RESERVED RESERVED CHB2_CORS5 CHB2_CORS4 CHB2_CORS3 CHB2_CORS2 CHB2_CORS1 CHB2_CORS0
page 60 default 0 0 0 0 0 0 0 0
1Fh Chnl B2 Comp.
Filter - Fine Adj RESERVED RESERVED CHB2_FINE5 CHB2_FINE4 CHB2_FINE3 CHB2_FINE2 CHB2_FINE1 CHB2_FINE0
page 61 default 0 0 0 0 0 0 0 0
20h Chnl A3 Comp.
Filter - Coarse Adj RESERVED RESERVED CHA3_CORS5 CHA3_CORS4 CHA3_CORS3 CHA3_CORS2 CHA3_CORS1 CHA3_CORS0
page 60 default 0 0 0 0 0 0 0 0
Addr Function 7 6 5 4 3 2 1 0
46 DS633F1
CS44600
21h Chnl A3 Comp.
Filter - Fine Adj RESERVED RESERVED CHA3_FINE5 CHA3_FINE4 CHA3_FINE3 CHA3_FINE2 CHA3_FINE1 CHA3_FINE0
page 61 default 0 0 0 0 0 0 0 0
22h Chnl B3 Comp.
Filter - Coarse Adj RESERVED RESERVED CHB3_CORS5 CHB3_CORS4 CHB3_CORS3 CHB3_CORS2 CHB3_CORS1 CHB3_CORS0
page 60 default 0 0 0 0 0 0 0 0
23h Chnl B3 Comp.
Filter - Fine Adj RESERVED RESERVED CHB3_FINE5 CHB3_FINE4 CHB3_FINE3 CHB3_FINE2 CHB3_FINE1 CHB3_FINE0
page 61 default 0 0 0 0 0 0 0 0
24h Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
default 0 0 0 0 0 0 0 0
25h Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
default 0 0 0 0 0 0 0 0
26h Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
default 0 0 0 0 0 0 0 0
27h Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
default 0 0 0 0 0 0 0 0
28h Interrupt Mode
Control INT1 INT0 RESERVED RESERVED RESERVED RESERVED RESERVED OVFL_L/E
page 61 default 0 0 0 0 0 0 0 0
29h Interrupt Mask M_SRC_UNLOCK M_SRC_LOCK M_RMPUP_DONE M_RMPDN_DONE M_MUTE_DONE M_OVFL_INT RESERVED RESERVED
page 62 default 0 0 0 0 0 0 0 0
2Ah Interrupt Status SRC_UNLOCK SRC_LOCK RMPUP_DONE RMPDN_DONE MUTE_DONE OVFL_INT GPIO_INT RESERVED
page 62 default 0 0 0 0 0 0 0 0
2Bh Chnl Over Flow Sta-
tus RESERVED RESERVED CHB3_OVFL CHA3_OVFL CHB2_OVFL CHA2_OVFL CHB1_OVFL CHA1_OVFL
page 64 default 0 0 0 0 0 0 0 0
2Ch GPIO Pin I/O RESERVED GPIO6_I/O GPIO5_I/O GPIO4_I/O GPIO3_I/O GPIO2_I/O GPIO1_I/O GPIO0_I/O
page 64 default 0 0 0 0 0 0 0 0
2Dh GPIO Pin Polar-
ity/Type RESERVED GPIO6_P/T GPIO5_P/T GPIO4_P/T GPIO3_P/T GPIO2_P/T GPIO1_P/T GPIO0_P/T
ppage 64 default 0 1 1 1 1 1 1 1
2Eh GPIO Pin Level/Ed ge
trigger RESERVED GPIO6_L/E GPIO5_L/E GPIO4_L/E GPIO3_L/E GPIO2_L/E GPIO1_L/E GPIO0_L/E
page 65 default 0 0 0 0 0 0 0 0
2Fh GPIO Pin Status RESERVED GPIO6_STATUS GPIO5_STATUS GPIO4_STATUS GPIO3_STATUS GPIO2_STATUS GPIO1_STATUS GPIO0_STATUS
page 65 default X X X X X X X X
30h GPIO Interrupt Mask RESERVED RESERVED RESERVED RESERVED M_GPIO3 M_GPIO2 M_GPIO1 M_GPIO0
page 66 default 0 0 0 0 0 0 0 0
31h PWM Config OSRATE RESERVED RESERVED A1/B1_OUT_CNFG A2/B2_OUT_CNFG A3_OUT_CNFG B3_OUT_CNFG RESERVED
page 66 default 0 0 0 0 0 0 0 0
Addr Function 7 6 5 4 3 2 1 0
DS633F1 47
CS44600
32h PWM Minimum Pulse
Width DISABLE_
PWMOUTxx- RESERVED RESERVED MIN_PULSE4 MIN_PULSE3 MIN_PULSE2 MIN_PULSE1 MIN_PULSE0
page 67 default 0 0 0 0 0 0 0 0
33h PWMOUT Delay DIFF_DLY2 DIFF_DLY1 DIFF_DLY0 CHNL_DLY4 CHNL_DLY3 CHNL_DLY2 CHNL_DLY 1 CHNL_DLY0
page 68 default 0 0 0 0 0 0 0 0
34h PSR / Power Supply
Config PSR_EN PSR_RESET FEEDBACK_ EN RESERVED RESERVED PS_SYNC_DIV2 PS_SYNC_DIV1 PS_SYNC_DIV0
page 69 default 0 0 0 0 0 0 0 0
35h PSR_Decimator
Scaled RESERVED DEC_SHIFT2 DEC_SHIFT1 DEC_SHIFT0 RESERVED DEC_SCALED18 DEC_SCALED17 DEC_SCALED16
page 70 default 0 0 1 0 0 0 1 0
36h PSR_Decimator
Scaled DEC_SCALED15 DEC_SCALED14 DEC_SCALED13 DEC_SCALED12 DEC_SCALED11 DEC_SCALED10 DEC_SCALED09 DEC_SCALED08
page 70 default 0 1 0 1 1 0 0 0
37h PSR_Decimator
Scaled DEC_SCALED07 DEC_SCALED06 DEC_SCALED05 DEC_SCALED04 DEC_SCALED03 DEC_SCALED02 DEC_SCALED01 DEC_SCALED00
page 70 default 0 1 1 0 1 0 0 0
38h Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
default 0 0 0 0 0 0 0 0
39h Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
default 0 0 0 0 0 0 0 0
3Ah Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
default 0 0 0 0 0 0 0 0
3Bh PSR_Decimator Outd DEC_OUTD23 DEC_OUTD22 DEC_OUTD21 DEC_OUTD20 DEC_OUTD19 DEC_OUTD18 DEC_OUTD17 DEC_OUTD16
page 71 default 0 0 0 0 0 0 0 0
3Ch P SR_Decimator Outd DEC_OUTD15 DEC_OUTD14 DEC_OUTD13 DEC_OUTD12 DEC_OUTD11 DEC_OUTD10 DEC_OUTD09 DEC_OUTD08
page 71 default 0 0 0 0 0 0 0 0
3Dh P SR_Decimator Outd DEC_OUTD07 DEC_OUTD06 DEC_OUTD05 DEC_OUTD04 DEC_OUTD03 DEC_OUTD02 DEC_OUTD01 DEC_OUTD00
page 71 default 0 0 0 0 0 0 0 0
Addr Function 7 6 5 4 3 2 1 0
48 DS633F1
CS44600
7. REGISTER DESCRIPTION
All registers are read/write except for I.D. and Revision Register, Interrupt Status and Decimator OutD registers
which are read only. See the following bit definition tables for bit ass ign m en t info rm a tio n. The default state of each
bit after a power-up sequence or reset is listed in each bit description.
7.1 Memory Address Pointer (MAP)
Not a register
7.1.1 Increment (INCR)
Default = 1
Function:
memory address pointer auto increment control
– 0 - MAP is not incremented automatically.
– 1 - Internal MAP is automatically incremented after each read or write.
7.1.2 Memory Address Pointer (MAPx)
Default = 0000001
Function:
Memory address pointer (MAP). Sets the register address that will be read or written by the control port.
7.2 C S44600 I.D. and Revision Register (address 01h) (Read Only)
7.2.1 Chip I.D. (Chip_IDx)
Default = 1101
Function:
I.D. code for the CS44600. Permanently set to 1101.
7.2.2 Chip Revision (Rev_IDx)
Default = 0001
Function:
CS44600 revision level. Revision A is coded as 0001.
76543210
INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0
76543210
CHIP_ID3 CHIP_ID2 CHIP_ID1 CHIP_ID0 REV_ID3 REV_ID2 REV_ID1 REV_ID0
DS633F1 49
CS44600
7.3 Clock Configuration and Power Control (address 02h)
7.3.1 Enable SYS_CLK Output (EN_SYS_CLK)
Default = 1
Function:
This bit enables the driver for the SYS_CLK signal. If the SYS_CLK output is unused, this bit should be
set to ‘0’b to disable the driver.
7.3.2 SYS_CLK Clock Divider Settings (SYS_CLK_DI V[1:0])
Default = 00
Function:
These two bits determine the divider for the XTAL clock signal for generating the SYS_CLK signal. During
a reset condition, with the RST input pin held low, the logic level on the MUTE input pin will determine the
divider used for the SYS_CLK output. If MUTE is pulled low, the SYS_CLK divider will be set to divide
the clock frequency on XTI by a factor of 1. If the MUTE pin is pulled high, the SYS_CLK output will be
set to perform a divid e-by-2 on the XTI clock. The sta te of the MUTE pin will be latched on the rising edge
of the RST. The MUTE pin can then be used as defined.
7.3.3 PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0])
Default = 00
Function:
These two bits determine the divider for the XTAL clock signal for generating the PWM_MCLK signal.
7.3.4 Power Down XTAL (PDN_XTAL)
Default = 0
0 - Crystal Oscillator Circuit is running.
1 - Crystal Oscillator Circuit is powered down.
Function:
This bit is used to power down the crystal oscillator circuitry when not being used. When using a clock
signal attached to the XTI input, this bit should be set to ‘1’b.
76 5 4 3 2 10
EN_SYS_CLK SYS_CLK_DIV1 SYS_CLK_DIV0 PWM_MCLK_DIV1 PWM_MCLK_DIV0 PDN_XTAL PDN_OUTPUT_MODE PDN
SYS_CLK_DIV[1:0] SYS_CLK Clock Divider
00 Use state of MUTE input pin following RST
condition
01 Divide by 2
10 Divide by 4
11 Divide by 8
PWM_MCLK_DIV[1:0 ] PWM Master Clock
Divider
00 Divide by 1
01 Divide by 2
10 Divide by 4
11 Divide by 8
50 DS633F1
CS44600
7.3.5 Power Down Output Mode (PDN_OUTPUT_MODE)
Default = 0
0 - PWM Outputs are driven low during power down
1 - PWM Outputs ar e dr ive n to th e inactive state during power down
Function:
This bit is used to select the power-down state of the PWM output signals. When set to 0, each channel
which has been powered down, following the ramp-down cycle if enabled, will drive the output signals,
PWMOUTxx+ and PWMOUTxx-, low.
When set to 1, each channel which has been powered down, following the ramp-down cycle if enabled,
will drive the output signals to the inactive state. PWMOUTxx+ is driven low and PWMOUTxx- is driven
high.
7.3.6 Power Down (PDN)
Default = 1
0 - Normal Operation
1 - Power down
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation can occur.
7.4 P WM Channel Power Down Control (address 03h)
7.4.1 Power Down PWM Channels (PDN_PWMB3:PDN_PWMA1)
Default = 11111111
0 - Normal Operation
1 - Power down PWM channel
Function:
The specific PWM channel is in the power-down state. All processing is halted for the specific channel,
but does not alter the setup or delay register values. The PWM output signals are driven to the appropriate
logic level as defined by the Power-Down Output Mode bit, PDN_OUTPUT_MODE. When set to normal
operation, the specific channel will power up according to the state of the RAMP[1:0] bits and the channel
output configuration selected. When transitioning from normal operation to power down, the specific chan-
nel will power down according to the state of the RAMP[1:0] bits and the channel output configuration se-
lected. Ramp control is found in “Ramp Configuration (address 05h)” on page 54.
76543210
RESERVED RESERVED PDN_PWMB3 PDN_PWMA3 PDN_PWMB2 PDN_PWMA2 PDN_PWMB1 PDN_PWMA1
DS633F1 51
CS44600
7.5 Misc. Configuration (address 04h)
7.5.1 Digital Interface Format (DIFX)
Default = 001
Function:
These bits select the digital interfac e format used for the DAI Serial Port. The required relationship be-
tween the Left/Right clock, serial clock, and serial data is defined by the Digital Interface Format and the
options are detailed in Figures 17 - 22.
7.5.2 AM Frequency Hopping (AM_FREQ_HOP)
Default = 0
Function:
Enables the modulator to alter the PWM switch timings to rem ove interference when the desired frequ en-
cy from an AM tuner is positioned near the PWM switching rate. The PWM modulator circuitry must first
be powered down usin g the PDN bit in the Clock Conf iguration and Power Control (address 02h) Register
before this feature can be enabled. There will be a delay following the power-up sequence due to the re-
locking of the SRC. Once this feature is enabled, the output switch rate is divided by 2.25, resulting in a
lowered PWM switch rate. Care should be taken to ensure that:
PWM_MCLK / 16 > the upper freq uency limit of the AM tuner used
7.5.3 Freeze Controls (FREEZE)
Default = 0
Function:
This function will freeze the previous output of, and allow modifications to be made to the Master Volume
Control (address 07 h-08h), Channel XX Volume Contr ol (address 09h- 12h), and Ch annel Mute (addre ss
13h) registers without the changes taking effect until the FREEZE bit is disabled. To make multiple chang-
es in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.
7654 3210
DIF2 DIF1 DIF0 RESERVED AM_FREQ_HOP FREEZE DEM1 DEM0
DIF2 DIF1 DIF0 Description Figure
0 0 0 Left-Justified, up to 24-bit data 18
0 0 1 I²S, up to 24-bit data 17
0 1 0 Right-Justified, 16-bit data 19
0 1 1 Right-Justified, 24-bit data 19
1 0 0 One-Line mode #1, 20-bit data 20
1 0 1 One-Line mode #2, 24-bit data 21
1 1 0 TDM Mode, up to 32-bit data 22
Table 5. Digit a l Audio Interface Formats
52 DS633F1
CS44600
7.5.4 De-Emphasis Control (DEM[1:0])
Default = 00
00 - no de-emphasis
01 - 32 kHz de-emphasis filter
10 - 44.1 kHz de-emphasis filter
11 - 48 kHz de-emphasis filter
Function:
Enables the appropriate digital filter t o maintain the standard 15 ms/50 ms digital de-emphasis filter re-
sponse.
7.6 Ramp Configuration (address 05h)
7.6.1 Ramp-Up/Down Setting (RAMP[1:0])
Default = 00
00 - Ramp-up and ramp-down are disabled
01 - Ramp-up is disabled. Ramp-down is enabled.
10 - Reserved
11 - Ramp-up and ra mp-down are enabled. Note that after a ramp-up se quence has completed, audio will
not play until RAMP[1:0] is set to 01.
Function:
When ramping is e n abl ed , t he d ut y cycle of the ou tput PWM signal is in cre a sed ( ra m p- up ) or decr ea se d
(ramp-down) at a rate determined by th e Ramp Speed variabl e (RAMP_SPDx). This funct ion is used in
single-ended applications to reduce pops in the output caused by the DC-blocking capacitor. When the
ramp-up/down function i s disabled in single-ended application s, there will be an abrupt change in the out-
put signal. Refer to Section 5.1.1 .
If ramp-up or down is not needed, as in a full-bridge application, these bits should be set to 00. If ramp-
up or down is needed, as in a single-ende d half-bridge application, these bits must be used in the proper
sequence as outlined in “Recommended Power-Up Sequence” on page 43 and “Recommended Power-
Down Sequence” on page 45.
7.6.2 Ramp Speed (RAMP_SPD[1:0])
Default = 01
00 - Ramp speed = appro xim at ely 0. 1 seconds
01 - Ramp speed = approximately 0.2 seconds
10 - Ramp speed = approximately 0.3 seconds
11 - Ramp speed = approximately 0.65 seconds
Function:
This feature is used in single-en ded applications to reduce pops in the output caused by the DC-blocking
capacit or. The Ramp Spee d sets the time for the PWM signal to linear ly ramp-up a nd down fr om the bias
point (50% PWM duty cycle). Refer to Section 5.1.1
76543210
RESERVED RESERVED RESERVED RAMP1 RAMP0 RESERVED RAMP_SPD1 RAMP_SPD0
DS633F1 53
CS44600
7.7 Volume Control Configuration (address 06h)
7.7.1 Single Volume Control (SNGVOL)
Default = 0
Function:
The individual channel volume levels are independently controlled by their respective Volume Control reg-
isters when t his fu nc tio n is disa b led . W he n en ab le d, the volume on all channels is determined by the A1
Channel Volume Control register. The other Volume Control registers are ignored.
7.7.2 Soft Ramp and Zero Cross Control (SZC[1:0])
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a tim-
eout period (approximately 18.7 ms for a PWM switch rate of 384/768 kHz and 17.0 ms for a PWM switch
rate of 421.875/843.75 kHz) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
Soft Ramp
Soft Ramp allows level changes, bo th muting and attenuation, to be implemented by increme ntally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock period s.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or
muting, will occur in 1/8-dB steps and be implemented on a signal zero crossing. The 1/8-dB level change
will occur after a timeout period (approximately 18.7 ms for a PWM switch rate of 384/768 kHz and
17.0 ms for a PWM switch rate of 421.875/843.75 kHz) if the signal does not encounter a zero crossing.
The zero cross function is independently monitor ed and implemented for each channel.
7.7.3 Enable 50% Duty Cycle for Mute Condition (MUTE_50/50)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit enables the modulator to output an exact 50%-duty-cycle PWM signal (not modulated), which cor-
responds to digital silence, for all mute conditions. T he muting function is a ffected, similar to volume con-
76543210
SNGVOL SZC1 SZC0 RESERVED MUTE_50/50 SRD_ERR SRU_ERR AMUTE
54 DS633F1
CS44600
trol changes, by the Soft and Zero Cross bits (SZC[1:0]). This bit does not cause a mute condition to occur.
The MUTE_50/50 bit only defines operation during a normal mute condition.
When MUTE_50/50 is set and a mute condition occurs, PSR will not affect the output of the modulator,
regardless if PSR is enabled. Output noise may be increased in this case if the noise on the high volta ge
power supply is gr eater than the system noise. Ther efore, it is recommend ed that if a noisy p ower supply
is used in a single- ended half-bridge c onfiguration with PSR enabled, MUTE_50/50 should be disabled
and a normal, modulated mute should be used. This will allow the modulator to use the PSR feedback to
reject power supply no ise and improve system performance.
7.7.4 Soft Ramp-Down on Interface Error (SRD_ERR)
Default = 0
0 - Disabled
1 - Enabled
Function:
A mute will be performed upon detection of a timing error on the Digital Audio Interface or if an
SRC_LOCK error has occurred. An SRC_LOCK interrupt is an indication that the sample rate converter
timings have become unstable, or have changed abruptly. Audio data from the SRC is no longer consid-
ered valid and could cause unwanted pops or clicks.
When this featur e is enabled, th is mute is affected, similar to attenuation changes, by the Soft and Zero
Cross bits (SZC[1:0]). When disabled, an immediate mute is performed on detection of an error.
Note: For best results, it is recommended that this bit be used in conjunction with the SRU_ERR bit.
7.7.5 Soft Ramp-Up on Recovered Interface Error (SRU_ERR)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after a MCLK/LRCK ratio change, recovered DA I timing error, or after the
SRC has gained lock. Whe n this feature is enabled, this un-mute is a ffected, similar to atte nuation chang-
es, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an immediate un-mute is performed in
these inst an ce s.
Note: For best results, it is recommended that this bit be used in conjunction with the SRD_ERR bit.
7.7.6 Auto-Mute (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The PWM converters of the CS44600 will mute the output following the reception of 8192 consecutive
audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently fo r each channel. The muting function is a ffected, sim ilar to vo lume cont rol
changes, by the Soft and Zero Cross bits (SZC[1:0]).
DS633F1 55
CS44600
7.8 Master Volume Control - Integer (address 07h)
7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0])
Default = 00000000
Function:
The Mast er Volume Contro l - Intege r regis ter allows global control of the signal levels on all channels in
1 dB increments from +24 to -127 dB. Volume settings are decoded as shown in Table 6. The volume
changes are implemented as specified by the Soft and Zero Cross bits (SZC[1:0]). All volume settings
greater than 00011000b are equivalent to +24 dB. Binary values for integer volume settings less than
0 dB are in two’s complement form.
7.9 Master Volume Control - Fraction (address 08h)
7.9.1 Master Volume Control - Fraction (MSTR_FVOL[1:0])
Default = 00
00 - +0.00 dB
01 - +0.25 dB
10 - +0.50 dB
11 - +0.75 dB
Function:
The Master Volume Control - Fraction register is an additional offset to the value in the Master Volume
Control - Integer register and allows global control of the signal levels on all channels in 0.25 dB incre-
ments. Volume settings are decoded as shown in Table 7. These volume changes are implemented as
specified by the Soft and Zero Cross bits (SZC[1:0]). All volume settings greater than 00011000b are
equivalent to +24 dB. Binary values for integer and fractional vo lume settings less than 0 dB are in two’s
complement form.
To calculate from a positive decimal integer:fraction value to a binary positive integer:fraction value, do
the following:
1. Convert the decimal integer to binary. This is MSTR_ IVOL[7:0].
2. Select the bit representation of the desired 0.25 fractional increment. This is MSTR_FVOL[1:0].
To calculate from a nega tive decimal integer:fraction value to a binary, 2’s complement inte ger:fraction
value, do the following:
76543210
MSTR_IVOL7 MSTR_IVOL6 MSTR_IVOL5 MSTR_IVOL4 MSTR_IVOL3 MSTR_IVOL2 MSTR_IVOL1 MSTR_IVOL0
MSTR_IVOL[7:0] Hex Value Volume Setting
0001 1000 18 +24 dB
0001 0111 17 +23 dB
0000 0001 01 +1 dB
0000 0000 00 0 dB
1111 1111 FF -1 dB
1111 1110 FE -2 dB
1000 0001 81 -127 dB
Table 6. Master Intege r Volume Settings
76543210
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED MSTR_FVOL1 MSTR_FVOL0
56 DS633F1
CS44600
1. Convert the decimal integer to binary. This is MSTR_IVOL[7:0].
2. Select the bit representation of the desired 0.25 fractional increment. This is MSTR_FVOL[1:0].
3. Concatenate MSTR_IVOL[7:0]: MSTR_FVOL[1:0] to form a 10-bit binary value.
4. Perform a 2’s complement conversion on all 10 bits.
The upper 8 bits are now the new MSTR_FVOL[7:0] and the two lower bits are MSTR_FVOL[1:0].
To convert from a 2’s complement integer:fraction value to a negative decimal, do the following:
1. Concatena te M S TR _IVOL[7:0]: M STR_FVOL[1: 0] to for m a 10 -b it bin ar y valu e.
2. Perform a 2’s complement conversion on all 10 bits.
3. Convert the 10-bit binary number to a decimal va lue.
4. Divide the decimal value by 4.
MSTR_IVOL[7:0] MSTR_FVOL(1:0) Volume Setting
0001 1000 00 +24.00 dB
0001 0111 10 +23.50 dB
0000 0001 11 +1.75 dB
0000 0001 00 +1.00 dB
0000 0000 01 +0.25 dB
0000 0000 00 0 dB
1111 1111 10 -0.50 dB
1111 1111 00 -1.00 dB
1111 1110 11 -1.25 dB
1111 1101 10 -2.50 dB
1000 0010 00 -126.00 dB
1000 0001 11 -126.25 dB
1000 0001 00 -127.00 dB
Table 7. Master Fractional Volume Settings
DS633F1 57
CS44600
7.10 Channel XX Volume Control - Integer (addresses 09h - 0Eh)
7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0])
Default = 00000000
Function:
The Channel X Volume Control - Integer register allows global contro l of the signal levels on all channels
in 1 dB increments from +24 to -127 dB. Volume settings are decoded as shown in Table 6. The volume
changes are implemented as specified by the Soft and Zero Cross bits (SZC[1:0]. All volume settings
greater than 00011000b are equivalent to +24 dB. Binary values for integer volume settings less than
0 dB are in two’s complement form.
7.11 Channel XX Volume Control1 - Fraction (address 11h)
7.12 Channel XX Volume Control2 - Fraction (address 12h)
7.12.1 Channel Volume Control - Fraction (CHXX_FVOL[1:0])
Default = 00
00 - +0.00 dB
01 - +0.25 dB
10 - +0.50 dB
11 - +0.75 dB
Function:
The Channel X Volume Control - Fraction register is an additional offset to the value in the Channel Vol-
ume Control - Integer register and allows global control of the signal levels on all channels in 0.25 dB in-
crements. Volume settings are decoded as shown in Table 7. These volume changes are implemented
as specified by the Soft and Zero Cross bits (SZC[1:0]). All volume settings greater than 00011000b are
equivalent to +24 dB. Binary values for integer and fractional vo lume settings less than 0 dB are in two’s
complement form.
See “Master Volume Control - Fraction (address 08h)” on page 57 for hi nts on conve rting dec imal num-
bers to 2’s complement binary values.
76543210
CHXX_IVOL7 CHXX_IVOL6 CHXX_IVOL5 CHXX_IVOL4 CHXX_IVOL3 CHXX_IVOL2 CHXX_IVOL1 CHXX_IVOL0
CHXX_IVOL[7:0] Hex Value Volume Setting
0001 1000 18 +24 dB
0001 0111 17 +23 dB
0000 0001 01 +1 dB
0000 0000 00 0 dB
1111 1111 FF -1 dB
1111 1110 FE -2 dB
1000 0001 81 -127 dB
Table 8. Channel Integer Volume Settings
76543210
CHB2_FVOL1 CHB2_FVOL0 CHA2_FVOL1 CHA2_FVOL0 CHB1_FVOL1 CHB1_FVOL0 CHA1_FVOL1 CHA1_FVOL0
76543210
RESERVED RESERVED RESERVED RESERVED CHB3_FVOL1 CHB3_FVOL0 CHA3_FVOL1 CHA3_FVOL0
58 DS633F1
CS44600
7.13 Channel Mute (address 13h)
7.13.1 Independent Channel Mute (CHXX_MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The PWM outputs of the CS44600 will mute when enabled. The muting function is affected, similar to at-
tenuation changes, by the Soft and Zero Cross bits (SZC[1:0]).
7.14 Channel Invert (address 14h)
7.14.1 Invert Signal Polarity (CHXX_INV)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
CHXX_IVOL[7:0] CHXX_FVOL(1:0) Volume Setting
0001 1000 00 +24.00 dB
0001 0111 10 +23.50 dB
0000 0001 11 +1.75 dB
0000 0001 00 +1.00 dB
0000 0000 01 +0.25 dB
0000 0000 00 0 dB
1111 1111 10 -0.50 dB
1111 1111 00 -1.00 dB
1111 1110 11 -1.25 dB
1111 1101 10 -2.50 dB
1000 0010 00 -126.00 dB
1000 0001 11 -126.25 dB
1000 0001 00 -127.00 dB
Table 9. Channel Fractional Volume Settings
76543210
RESERVED RESERVED CHB3_MUTE CHA3_MUTE CHB2_MUTE CHA2_MUTE CHB1_MUTE CHA1_MUTE
76543210
RESERVED RESERVED CHB3_INV CHA3_INV CHB2_INV CHA2_INV CHB1_INV CHA1_INV
DS633F1 59
CS44600
7.15 Peak Limiter Control Register (address 15h)
7.15.1 Peak Signal Limit All Channels (LIMIT_ALL)
Default = 0
0 - individual channel
1 - all channels
Function:
When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the
specific channel indicating clipping. The other channels will not be affected.
When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on ALL
channels in response to ANY single channel indicating clipping.
7.15.2 Peak Signal Limiter Enable (LIMIT_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS44600 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the Limiter At-
tack Rate register.
7.16 Limiter Attack Rate (address 16h)
7.16.1 Attack Rate (ARATE[7:0])
Default = 00010000
Function:
The limiter attack rate is user selectable. The effective rate is a function of the SRC output sampling fre-
quency and the value in the Limiter Attack Rate register. Rates are calculated using the function
RATE = (32/{value})/SRC Fs, where {value} is the decimal value in the Limiter Attack Rate register and
SRC Fs is the output sample rate of the SRC which is determined by the PWM master clock frequency.
SRC Fs equals 384 kHz for 24.576 MHz based clocks and 421.875 kHz for 27.000 MHz based clocks.
Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see Peak Limiter Control Register (address 15h)).
76543210
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED LIMIT_ALL LIMIT_EN
76543210
ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0
60 DS633F1
CS44600
7.17 Limiter Release Rate (address 17h)
7.17.1 Release Rate (RRATE[7:0])
Default = 00100000
Function:
The limiter release rate is user selectable. The effective rate is a function of the SRC ou tput sampling fre-
quency and the value in the Release Rate register. Rates are calculated using the function
RATE = (512/{value})/SRC Fs, where {value} is the decimal value in the Release Rate register and SRC
Fs is the output samp le rate of the SRC which is determined by the PWM master clock frequency. SRC
Fs equals 384 kHz for 24.576 MHz based clocks and 421.875 kHz for 27.000 MHz based clocks.
Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see Peak Limiter Control Register (address 15h)).
7.18 Chnl XX Load Compensation Filter - Coarse Adjust
(addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h)
7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0])
Default = 000000
Function:
The Channel Load Compensation Filter Coarse Adjustment settings control the amount of attenuation of
this single-pole filter and are used in conjunction with the Fine Adjustment bits to compensa te for speaker
impedance load variations. Each PWM channel is controlled by an associated register. The coarse ad-
justment bits will attenuate the audio response curve according to the table below in 0.1 dB increments.
Filter setting values less than -4.0 dB will cause the PWM output to mute.
Binary Code Decimal Value Attack Rate - 384 k Hz
(µs per 1/8dB)Attack Rate - 421.875 kHz
(µs per 1/8dB)
00000001 1 83.33 75.852
00010100 20 4.167 3.793
00101000 40 2.083 1.896
00111100 60 1.389 1.264
01011010 90 0.926 0.843
Table 10. Limiter Attack Rate Settings
76543210
RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0
Binary Code Decimal Value Releas e Rate - 384 kHz
(µs per 1/8dB)Release Rate - 421.875 kHz
(µs per 1/8dB)
00000001 1 1333.333 1213.630
00010100 20 66.667 60.681
00101000 40 33.333 30.341
00111100 60 22.222 20.227
01011010 90 14.815 13.485
Table 11. Limiter Release Rate Settings
76543210
RESERVED RESERVED CHXX_CORS5 CHXX_CORS4 CHXX_CORS3 CHXX_CORS2 CHXX_CORS1 CHXX_CORS0
DS633F1 61
CS44600
7.19 Chnl XX Load Compensation Filter - Fine Adjust
(addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h)
7.19.1 Chann el Compensation Filter - Fine Adjust (CHXX_FINE[5:0])
Default = 000000
Function:
The Channel Load Compensatio n Filter Fine Adjustment settings control the amount of attenuation of this
single-pole filter which follows the Coarse Ad justment Compen sation Filter. These bits are used in con-
junction with the Coarse Adjustment bits to fine tune the tota l fre qu ency respo nse of the system to com-
pensate for speaker impedance load variations. Each PWM channel is controlled by an associated
register. The fine adjustment bits will attenuate the audio response curve according to the table below in
0.1 dB increments. Filter setting values less than -4.0 dB will cause the PWM output to mute.
7.20 Interrupt Mode Control (address 28h)
7.20.1 Interrupt Pin Control (INT1/INT0)
Default = 00
00 - Active high, high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
Function:
Determines how the interrupt pin (INT) will indicate an interrupt condition. If any of the mask bits in the
Interrupt Mask Register are set to a 1b, re ad the Interrupt Status Register to determine which condition
caused the interrupt.
CHXX_CORS[5:0] Coarse Filter Setting
000000 0 dB
000001 -0.1 dB
001010 -1.0 dB
011001 -2.5 dB
100000 -3.2 dB
101000 -4.0 dB
Table 12. Ch annel Load Compensation Filter Coarse Adjust
76543210
RESERVED RESERVED CHXX_FINE5 CHXX_FINE4 CHXX_FINE3 CHXX_FINE2 CHXX_FINE1 CHXX_FINE0
CHXX_FINE[5:0] Fine Filter Setting
000000 0 dB
000001 -0.1 dB
001010 -1.0 dB
011001 -2.5 dB
100000 -3.2 dB
101000 -4.0 dB
Table 13. Channel Load Compensation Filter Fine Adjust
76543210
INT1 INT0 RESERVED RESERVED RESERVED RESERVED RESERVED OVFL_L/E
62 DS633F1
CS44600
7.20.2 Overflow Level/Edge Select (OVFL_L/E)
Default = 0
Function:
This bit defines the OVFL interrupt type (0 = le vel sensitive, 1 = edge trigger). The Over Flow status of all
the audio channels when config ured as “edge trigger” is cleared by reading the Channel Over Flow Status
(address 2Bh) (Read Only) , and by reset. Aft er a Reset this bit defa ults to 0b, specifying “level sensitive”.
7.21 Interrupt Mask (address 29h)
Default = 00000000
Function:
The bits of this register serve as a mask for the interrupt sources found in the Interrupt Status register. If a
mask bit is set to 1b, the interrupt is unmasked, meaning that its occurrence will affect the INT pin and the
Interrupt St at us r egis t er . If a ma sk b it is se t to 0b , the condition is masked, mea ning tha t its occurr ence will
not affect the INT pin. The bit positions align with the corresponding bits in the Inter rupt Status register. T he
mask bits for the GPIO_INT interrupt are located in the GPIO Interrupt Mask Register.
7.22 Interrupt Status (address 2Ah) (Read Only)
For all bits in this register, a ‘1’ means the associated interrupt conditio n has occurred at least once since
the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets the SRC_UNLOCK, SRC_LOCK, RMPUP_DONE,
RMPDN_DONE and MUTE_DONE bits to 0. These bits are considered “edge-trigger” interrupts.
The OVFL_INT and GPIO_INT bits will not reset to 0 by reading this register. The OVFL_INT bit will be set
to 0 by a read to the “Channel Over Flow Status (address 2Bh) (Read Only)” on page 66 only when the in-
terrupt type is set to “edge-trigger”. The GPIO_INT bit will be set to 0 by a read to the “GPIO Status Register
(address 2Fh)” on page 67 only when the interrupt type is set to “edge trigger”. If either of these interrupt
types are configured as “level sensitive”, then reading the appropriate status register will not clear the cor-
responding status bit in this register. OVFL_INT or GPIO_INT will remain set as long as the logic active level
is present. Once the level is cleared, then a read to the proper status register will clear the status bit.
7.22.1 SRC Unlock In terrupt (SRC_UNLOCK)
Default = 0
Function:
When high, indicates that the DAI interface has detect ed an error condition and/or the SRC has lost lock.
Conditions which cause the SRC to loose lock, such as loss of DAI_LRCK, DAI_MCLK or a DAI_LRCK/
DAI_MCLK ratio change, will cause an interrupt condition. This interrupt is an edge-triggered event.
If this bit is set to a 1b, indicating an unlock condition, and an SRC_LOCK interrupt is detected, then this
bit will be reset to 0b before a read of the Interrupt Status R egister. Only the last valid state of the SRC
will be reported.
765 4 3210
M_SRC_UNLOCK M_SRC_LOCK M_RMPUP_DONE M_RMPDN_DONE M_MUTE_DONE M_OVFL_INT RESERVED RESERVED
7 6 5 4 3210
SRC_UNLOCK SRC_LOCK RMPUP_DONE RMPDN_DONE MUTE_DONE OVFL_INT GPIO_INT RESERVED
DS633F1 63
CS44600
7.22.2 SRC Lock Interrupt (SRC_LOCK)
Default = 0
Function:
When high, indicates that on all active channels, the sample rate converters have achieved lock. This
interrupt is an edge-triggered event.
If this bit is set to a 1b, indicating a lock condition, and an SRC_UNLOCK condition is dete cted , then this
bit will be reset to 0b before a read of the Interrupt Status Register. Only the last valid state of the SRC
will be reported.
7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE)
Default = 0
Function:
When high, indicates that all active channels have completed the configured ramp-up interval.
7.22.4 Ramp-Down Complete Interrupt (RMP DN_DONE)
Default = 0
Function:
When high, indicates that all active channels have completed the configured ramp-down interval.
7.22.5 Mute Complete Interrupt (Mute_DONE)
Default = 0
Function:
When high, indicates that all muted channels have completed the mute cycle-down inter val as defin ed by
the SZC[1:0] bits in the “Volume Control Configuration (address 06h)” on page 55.
7.22.6 Channel Over Flow Interrupt (OVFL_INT)
Default = 0
Function:
When high, indicates that the magnitude of an output sample on one of the channels has exceeded full
scale and has been clipped to positive or negative full scale as appropriate. Th is bit is the logical O R of
all the bits in the Channel Over Flow Status Register. Read the Channel Over Flow Status Register to
determine which chan nel(s) had the overfl ow condition.
7.22.7 GPIO Interrupt Condition (GPIO_INT)
Default = 0
Function:
When high, indicates that a transition as configured on one of the un-masked GPIO pins has occurred.
This bit is the logical OR of all the supported un-ma sked bits in the GPIO Status Register. Read the GPIO
Status Register to determine which GPIO input(s) caused the interrupt condition. The GPIO interrupt is
not removed by reading this register. The GPIO Status Register must be read to clear this interrupt. If the
GPIO input is configured as “edge trigger” the interrupt will clear. If the GPIO input is configured as “level
sensitive”, the interrupt condition will remain as long as the GPIO input remains at the active level.
64 DS633F1
CS44600
7.23 Channel Over Flow Status (address 2Bh) (Read Only)
For all bits in this register, a ‘1’ means the associated condition has occurred at least once since the register
was last read. A ‘0’ means the associated conditio n has NOT occurred since the last rea ding of the register.
Reading the register resets all bits to 0 if the Overflow Level/Edge interrupt type is set to “edge trigger”.
These channel overflow status bits are not effected by the interrup t mask bit, M _OVFL_ INT. The ov erflow
condition of each channel can be polled instead of generating an interrupt as required.
7.23.1 ChXX_OVFL
Default = 0
Function:
When high, indicates that the magnitude of the cur rent output samp le on the associated chann el has ex-
ceeded full scale and has been clipped to positive or ne gative full scale as appropriate.
7.24 GPIO Pin In/Out (address 2Ch)
7.24.1 GPIO In/Out Selection (GPIOX_I/O)
Default = 0
0 - General Purpose Input
1 - General Purpose Output
Function:
General Purpose Input - The pin is configured as an input.
General Purpose Output - The pin is configured as a general purpose output.
7.25 GPIO Pin Polarity/Type (address 2Dh)
7.25.1 GPIO Polarity/Type Selection (GPIOX_P/T)
Default = 1
Function:
General Purpose Input - If the pin is configured as an input, this bit defines the input polarity (0 = Active
Low, 1 = Active High).
General Purpose Output - If the pin is configured as a general purpose output, this bit defines the GPIO
output type (0 = CMOS, 1 = OPEN-DRAIN).
76543210
RESERVED RESERVED CHB3_OVFL CHA3_OVFL CHB2_OVFL CHA2_OVFL CHB1_OVFL CHA1_OVFL
76543210
RESERVED GPIO6_I/O GPIO5_I/O GPIO4_I/O GPIO3_I/O GPIO2_I/O GPIO1_I/O GPIO0_I/O
76543210
RESERVED GPIO6_P/T GPIO5_P/T GPIO4_P/T GPIO3_P/T GPIO2_P/T GPIO1_P/T GPIO0_P/T
DS633F1 65
CS44600
7.26 GPIO Pin Level/Edge Trigger (address 2Eh)
7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E)
Default = 0
Function:
General Purpose Input - This bit defines the GPIO input type (0 = level sensitive, 1 = edge trigger) when
a GPIO pin is configured as an input. The GPIO pin status of an input configured as “edge trigger” is
cleared by reading the GPIO Status Register when not enabled to generate an interrupt (MASK bit equals
0b) and by reset. After a reset this bit defaults to 0b, specifying “level sensitive”.
General Purpose Output - Not Used.
7.27 GPIO Status Register (address 2Fh)
7.27.1 GPIO Pin Status (GPIOX_STATUS)
Default = x
Function:
General Purpose Inpu t - Bits in this register are read only when the corresponding GPIO pin is configured
as an input. Each bit indicates the status of the GPIO pin. The corresponding bit of a GPIO input config-
ured as “edge trigger” is cleared by reading the GPIO Status Register. GPIO inputs configured as “level
sensitive” will not be automatically cleared, but will reflect the logic state on the GPIO input. The mask bits
in the GPIO Interrupt Mask Register have no effect on the operation of these status bits.
When a GPIO is un-masked and enabled to generate an interrupt, and is configured as “edge trigger”, a
read operation to this register will clear the status bit and remove the interrupt condition. A read operation
to the Interrupt Status (addre ss 2Ah) (read only) when a GPIO is config ured to generate an interrupt con-
dition will not clear any bits in this register.
General Purpose Output - For GPIO pins con figur ed as outp uts, the se bits are u sed to contr ol the ou tput
signal level. A 1b written to a particular bit w ill cause the correspondin g GPIO pin to be driven to a logic
high. A 0b will cause a logic low.
76543210
RESERVED GPIO6_L/E GPIO5_L/E GPIO4_L/E GPIO3_L/E GPIO2_L/E GPIO1_L/E GPIO0_L/E
76 543210
RESERVED GPIO6_STATUS GPIO5_STATUS GPIO4_STATUS GPIO3_STATUS GPIO2_STATUS GPIO1_STATUS GPIO0_STATUS
66 DS633F1
CS44600
7.28 GPIO Interrupt Mask Register (address 30h)
7.28.1 GPIO Pin Interrupt Mask (M_GPIOX)
Default = 0
Function:
General Purpose Input - The bits of this register serve as a mask for GPIO[3:0] interrupt sources. If a mask
bit is set to 1, the interrupt is unmasked, meaning that its occurrence will affect the INT pin and the Inter-
rupt Status register. If a mask bit is set to 0, the condition is masked, meanin g that its occurrence will not
affect the INT pin or Interrupt Status R egister. The proper pin status will be reported in the GPIO Status
Register. The bit positions align with the corresponding bits in the GPIO Status register.
General Purpose Output - This register is not used.
7.29 PWM Configuration Register (address 31h)
7.29.1 Over Sample Rate Selection (OSRATE)
Default = 0
0 - modulated PWM output pulses run at single-mode switch rate. Typically 384 kHz or 421.875 kHz.
1 - modulated PWM output pulses run at double-mode switch rate. Typically 768 kHz or 843.75 kHz.
Function:
Enables the interpolation filter in the modulator to over-sample the incoming audio to support a double-
speed PWM switch rate . This pa ram eter can only be changed when all modulators and associated logic
are in the powe r-down state by settin g the PDN bit in the register “Clock Configuration and Power Control
(address 02h) ” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.29.2 Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG)
Default = 0
0 - pwm outputs for both channels A1 and B1 are configured for half-bridge operation
1 - pwm outputs for both channels A1 and B1 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for channels
A1 and B1. This parameter can only be changed when all modulator s and associated logic are in the pow-
er-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”
on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.29.3 Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG)
Default = 0
0 - pwm outputs for both channels A2 and B2 are configured for half-bridge operation
1 - pwm outputs for both channels A2 and B2 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for channels
A2 and B2. This parameter can only be changed when all modulator s and associated logic are in the pow-
76543210
RESERVED RESERVED RESERVED RESERVED M_GPIO3 M_GPIO2 M_GPIO1 M_GPIO0
76 5 4 3 2 1 0
OSRATE RESERVED RESERVED A1/B1_OUT_CNFG A2/B2_OUT_CNFG A3_OUT_CNFG B3_OUT_CNFG RESERVED
DS633F1 67
CS44600
er-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”
on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.29.4 Channel A3 Output Configuration (A3_OU T_CNFG)
Default = 0
0 - pwm outputs for channel A3 are configured for half-bridge operation
1 - pwm outputs for channel A3 are configured for full-bridge operation
Function:
Identifies the output confi guration. The value selected for this bit is applicable to the outputs for only chan-
nel A3. This parameter can only be changed when all modulators and associated logic are in the power
down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”
on page 51 to a ‘1’b. Attempts to write this register while the PDN is not set will be ignored.
7.29.5 Channel B3 Output Configuration (B3_OU T_CNFG)
Default = 0
0 - pwm outputs for channel B3 are configured for half-bridge operation
1 - pwm outputs for channel B3 are configured for full-bridge operation
Function:
Identifies the output confi guration. The value selected for this bit is applicable to the outputs for only chan-
nel B3. This parameter can only be changed when all modulators and associated logic are in the power-
down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”
on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.30 PWM Minimum Pulse Width Register (address 32h)
7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-)
Default = 0
0 - PWM minus (“-”) diffe rential signal is operational when PWM channel is configured for half-bridge.
1 - PWM minus (“-”) diffe rential signal is disabled when PWM channel is configured for half-bridge.
Function:
Determines if the PWM minus (“-”) di fferential signal is disabled when the particular PWM channel is con-
figured for half-bridge operation. This bit is ignored for channels configured for full-bridge operation. The
value selected for this bit is applicable to the outputs for all channels configured for half- bridge opera tion.
This parameter can only be changed when all modulators and associated logic are in the power-down
state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on
page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0])
Default = 00000
Function:
The PWM Minimum Pulse registers allow settings for the minimum allowable pulse width on each of the
PWMOUT differential signal pairs , PWMOUTxx+ and PWMOUTxx-. The value selected in this register is
applicable to all PWM channels. The effective minimum pulse is calcula ted by multiplying the register val-
ue by the period of the PWM_MCLK. This parameter can only be changed when all modulators and as-
sociated logic are in the power-down state by setting the PDN bit in the re gister “Clock Configuration and
76543210
DISABLE_PWMOUTXX- RESERVED RESERVED MIN_PULSE4 MIN_PULSE3 MIN_PULSE2 MIN_PULSE1 MIN_PULSE0
68 DS633F1
CS44600
Power Control ( addre ss 02 h) ” o n page 51 to a 1b. Attempts to write this register while the PDN is not set
will be ignored.
7.31 PWMOUT Delay Register (address 33h)
7.31.1 Differential Signal Delay (DIFF_DLY[2:0])
Default = 000
Function:
The Differential Signal Delay bits allow delay adjustment between each channel’s differential signals,
PWMOUTxx+ and PWMOUTxx-. This set of bits control the delay between PWMOUTxx+ and PW-
MOUTxx- across all active channels. The value of this register determines the amount of delay inserted
in the output path. The effective delay is calculated by multiplying the register value by the period of the
PWM_MCLK. This parameter can only be changed when all modulators and associated logic are in the
power-down state by setting the PDN bit in the register “Clock Co nfiguration and Power Control (address
02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.31.2 Channel Delay Settings (CHNL_DLY[4:0])
Default = 00000
Function:
The Channel Delay bits allow delay adjustment of each of the PWMOUT differential signal pairs, PW-
MOUTAx+/PWMOUTAx- from the associated PWMOUTBx+/PWMOUTBx- . The value of this register de-
termines the amount of delay inserted in the output path. The effective delay is calculated by multiplying
the register value by the period of the PWM_MCLK. This parameter can only be changed when all mod-
ulators and associated logic are in the power-down state by setting the PDN bit in the reg ister “Clock Con-
figuration and Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the
PDN is not set will be ignored.
Binary Code
MIN_PULSE[4:0] Minimum Pulse
Setting (multiply by
PWM_MCLK period)
00000 0 - no minimum
00110 6
10100 20
11111 31
Table 14. PWM Minimum Pulse Width Settings
76543210
DIFF_DLY2 DIFF_DLY1 DIFF_DLY0 CHNL_DLY4 CHNL_DLY3 CHNL_DLY2 CHNL_DLY1 CHNL_DLY0
Binary Code Delay Setting (multiply by
PWM_MCLK period)
000 0 - no delay
001 1
100 4
111 7
Table 15. Differential Signal Delay Settings
Binary Code Delay Setting(multipl y by PWM_ MCLK pe riod )
00000 0 - no delay
00110 6
11000 24
11111 31
Table 16. Cha nn el Delay Settings
DS633F1 69
CS44600
7.32 PSR and Power Supply Configuration (address 34h)
7.32.1 Power Supply Rejection Enable (PSR_EN)
Default = 0
0 - disable
1 - enable
Function:
Enables the on-card and internal power supply rejection circuitry. This bit will cause the PSR_EN output
signal to change logic level. A ‘0’b in this bit will cause the PSR_EN to drive a logic low. A ‘1’b will drive a
logic high.
76 5 4 3 2 1 0
PSR_EN PSR_RESET FEEDBACK_EN RESERVED RESERVED PS_SYNC_DIV2 PS_SYNC_DIV1 PS_SYNC_DIV0
PWMOUTA2+
PWMOUTA2-
PWMOUTB2+
PWMOUTB2-
tchdly
tdifdly
tdifdly
PWMOUTA1+
PWMOUTA1-
PWMOUTB1+
PWMOUTB1-
tchdly
tdifdly
tdifdly
PWMOUTA3+
PWMOUTA3-
PWMOUTB3+
PWMOUTB3-
tchdly
tdifdly
tdifdly
Figure 31. PWM Output Delay
70 DS633F1
CS44600
7.32.2 Power Supply Rejection Reset (PSR_RESET)
Default = 0
0 - force reset condition
1 - remove reset condition
Function:
This bit is used to assert a reset condition to the on-card PSR components. When set to a ‘0’b, the
PSR_RESET signal will be asserted low. The reset condition will continue as long as this bit is set to a
‘0’b. This bit must be set to a ‘1’b for proper PSR operation.
7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN)
Default = 0
0 - disable
1 - enable
Function:
Enables the internal power supply rejection feedback logic.
7.32.4 Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0])
Default = 000
Function:
These three bits determine the divider for the XTAL clock signal for generating the PS_SYNC clock signal.
7.33 Decimator Shift/Scale (addresses 35h, 36h, 37h)
7.33.1 Decimator Shift (DEC_SHIFT[2:0])
Default = 010
Function:
These bits are used to scale the power supp ly reading (Decimator Outd (addresses 3Bh, 3Ch, 3Dh)) dur-
ing the PSR feedback calibration sequence. The combination of shift and scale factors
(DEC_SCALE[18:0]*2^(DEC_SHIFT[2:0])) can be viewed as a floating poi nt coefficient. The floating point
coefficient will be determined during the PSR feedback calibration sequence. See Decimator Scale
(DEC_SCALE[18:0]) register description and “Recommended PSR Calib ration Sequence” on page 44.
PS_SYNC_DIV[2:0] PS_SYNC Clock Divider
000 Output Disabled
001 Divide by 32
010 Divide by 64
011 Divide by 128
100 Divide by 25 6
101 Divide by 51 2
110 Divide by 1024
Table 17. Power Supply Sync Clock Divider Settings
76543210
RESERVED DEC_SHIFT2 DEC_SHIFT1 DEC_SHIFT0 RESERVED DEC_SCALE18 DEC_SCALE17 DEC_SCALE16
76543210
DEC_SCALE15 DEC_SCALE14 DEC_SCALE13 DEC_SCALE12 DEC_SCALE11 DEC_SCALE10 DEC_SCALE09 DEC_SCALE08
76543210
DEC_SCALE07 DEC_SCALE06 DEC_SCALE05 DEC_SCALE04 DEC_SCALE03 DEC_SCALE02 DEC_SCALE01 DEC_SCALE00
DS633F1 71
CS44600
7.33.2 Decimator Scale (DEC_SCAL E[18:0])
Default = 25868h
Function:
These bits are used to scale the power supply reading ( Decimator Outd (a ddresses 3Bh, 3Ch, 3Dh)) d ur-
ing the PSR feedback calibration sequence. DEC_SCALE[ 18:0] has 19-bit precision, formatted as signed
1.18 with decimal values from -1 to 1-2^(-18). The combination of shift and scale factors
(DEC_SCALE[18:0]*2^(DEC_SHIFT[2:0])) can be viewed as a floatin g point coefficient. The floating point
coefficient will be determined during the PSR feedback calibration sequence. See Decimator Shift
(DEC_SHIFT[2:0]) register description and “Recommended PSR Calibration Sequence” on page 44.
7.34 Decimator Outd (addresses 3Bh, 3Ch, 3Dh)
7.34.1 Decimator Outd (DEC_OUTD[23:0])
Default = 000000h (Read Only)
Function:
These bits reflect the real-time power supply value as measured by the external PSR feedback circuit.
DEC_OUTD[23:0] has 24-bit precision, formatted as signed 2.22 with decimal values from -4 to 4-2^(-22).
Calibration need s to be done to co rrelate the value of DEC_OUTD[23:0] with the real powe r supply value.
A quiet DC power supply without any ripple is treated as 1.0 with DEC_OUTD[23:0] calibrated at 400000h.
See “Recommended PSR Calibration Sequence” on page 44.
DEC_SCALE[18:0] DEC_SHIFT[2:0] Calculated Coefficient (CPSR)
20000h=0.5 001b=1 0.5*2^(1)=1
28851h=0.6331 010b=2 0.6331*2^(2)=2.5325
Table 18. Dec imator Shift/Scale Coefficient Calculation Examples
76543210
DEC_OUTD23 DEC_OUTD22 DEC_OUTD21 DEC_OUTD20 DEC_OUTD19 DEC_OUTD18 DEC_OUTD17 DEC_OUTD16
76543210
DEC_OUTD15 DEC_OUTD14 DEC_OUTD13 DEC_OUTD12 DEC_OUTD11 DEC_OUTD10 DEC_OUTD09 DEC_OUTD08
76543210
DEC_OUTD07 DEC_OUTD06 DEC_OUTD05 DEC_OUTD04 DEC_OUTD03 DEC_OUTD02 DEC_OUTD01 DEC_OUTD00
72 DS633F1
CS44600
8. PARAMETER DEFINITIONS
Dynamic Range (DR)
The ratio of the rm s value of the signal to the rms sum of all other spectral components over the specified
bandwidth, typ ically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measuremen t over the spec-
ified band w idth made with a - 60 dBFS signal. 60 dB is then added to the re sulting measureme nt to refer
the measurement to full-scale, with units in dB FS A. This technique ensures that the distortion components
are below the noise level and do not effect the measurement. This measurement technique has been ac-
cepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan,
EIAJ CP-307.
Frequency Response (FR)
FR is the deviation in sign al level ver ses frequ enc y. The 0 dB reference point is 1 kHz. The amplitude cor-
ner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed
minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency to maxi-
mum frequency inclusive.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid- scale transition (111...111 to 000...000) from the ideal. Units in mV.
dB FS A
dB FS is defined as dB relative to full-scale. The “A” indicates an A weighting filter was used.
Differential No nl in ea rit y
The worst case deviation from the ideal code width. Units in LSB.
FFT
Fast Fourier Transform.
Fs
Sampling Frequency.
Resolution
The number of bits in the output words to the DACs, and in the input words to the ADCs.
DS633F1 73
CS44600
Signal to Noise Ratio (SNR)
SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal t o the RMS sum of the n oise floo r, in
the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB.
SRC
Sample Rate Converter. Conver ts data derived at one sample rate to a differing sample rate . The CS44600
operates at a fixed sample frequency. The internal sample rate converter is used to convert digital audio
streams playing ba ck at other frequencies to the PWM output rate.
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral compon ents over th e specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
9. REFERENCES
1. Cirrus Logic, “Audio Quality Measurement Specification,” Version 1.0, 1997.
http://www.cirrus.com/products/papers/meas/meas.html
2. Cirrus Logic, “AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,”
Version 6.0, February 1998.
3. Cirrus Logic, “AN22: Overview of Digital Audio Interface Data Structures, Version 2.0”, February 1998.; A
useful tutorial on di gi tal au d io spe cif ica tion s.
4. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998.
http://www.semiconductors.philips.com
74 DS633F1
CS44600
10.PACKAGE DIMENSIONS
INCHES MILLIMETERS
DIM MIN NOM MAX MIN NOM MAX
A --- 0.55 0.063 --- 1.40 1.60
A1 0.002 0.004 0.006 0.05 0.10 0.15
B 0.007 0.008 0.011 0.17 0.20 0.27
D 0.461 0.472 BSC 0.484 11.70 12.0 BSC 12.30
D1 0.390 0.39 3 BSC 0 .3 98 9.90 10.0 BSC 10.10
E 0.461 0.472 BSC 0.484 11.70 12.0 BSC 12.30
E1 0.390 0.39 3 BSC 0 .3 98 9.90 10.0 BSC 10.10
e* 0.016 0.020 BSC 0.024 0.40 0 .50 BSC 0.60
L 0.018 0.024 0.030 0.45 0.60 0.75
∝0.000° 4° 7.000° 0.00° 4° 7.00°
* Nominal pin pitch is 0.50 mmControlling dimension is mm.
JEDEC Designation: MS022
Figure 32. 64-Pin LQFP Package Drawing
Note: See Legend Below
64L LQFP PACKAGE DRAWING
E1
E
D1
D
1
e
L
∝
B
A1
A
DS633F1 75
CS44600
11.THERMAL CHARACTERISTICS
12.ORDERING INFORMATION
13.REVISION HISTORY
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance 2 Layer Board
4 Layer Board θJA -
-48
38 -
-°C/Watt
Product Description Package Pb-Free Temp Range Container Order#
CS44600 6-Channel Digital Ampli-
fier Controller LQFP YES -10° to +7 0°C Rail CS44600-CQZ
CS44600 6-Channel Digital Ampli-
fier Controller LQFP YES -10° to +70°C Tape and
Reel CS44600-CQZR
CS44600 6-Channel Digital Ampli-
fier Controller LQFP YES -40° to +8 5°C Rail CS44600-DQZ
CS44600 6-Channel Digital Ampli-
fier Controller LQFP YES -40° to +85°C Tape and
Reel CS44600-DQZR
CDB44800 CS44600/800 Evalua-
tion Board - - - - CDB44800
CRD44800 8x50 W Half-Bridge
Reference Design Board - - - - CRD44800
CRD44800-ST-FB 8x60 W Full-Bridge
Reference Design Board - - - - CRD44800-ST-FB
CRD44600-PH-FB 2x100 W Full-Bridge
Reference Design Board - - - - CRD44600-PH-FB
Release Date Changes
PP1 May 2005
-Updated “Features” on page 1
-Correcte “Power Supply Curre nt” on page 9
-Corrected “High-Level Input Voltage” on page 9
-Corrected “Low-Level Input Voltage” on page 9
-Corrected “High-Level Output Voltage at Io = -2 mA” on page 9
-Corrected “Low-Level Output Volta ge at Io = 2 mA” on page 9
-Corrected “Digital Filter Response (Note 12)” on page 11
-Updated “Typical Full-Bridge Connection Diagram” on page 22
-Updated “Typical Half-Bridge Connection Diagram” on page 23
-Corrected Figure 13 on page 23
-Updated Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 51
-Updated “Ordering Information” on page 75
F1 March 2006 -Final Datasheet Release
76 DS633F1
CS44600
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representa tive.
To find the one nearest to you, go to www.cirrus.com.
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