2007-07-24
1
BCR08PN
NPN/PNP Silicon Digital Transistor Array
• Switching circuit, inverter, interface circuit,
driver circuit
• Two (galvanic) internal isolated NPN/PNP
Transistors in one package
• Built in bias resistor NPN and PNP
(R1=2.2 kΩ, R2=47 kΩ)
• Pb-free (RoHS compliant) package1)
• Qualified according AEC Q101
1
623
54
EHA07176
654
321
C1 B2 E2
C2B1E1
1
R
R
2
R
1
R
2
TR1 TR2
Tape loading orientation
EHA07193
123
456
W1s
Direction of Unreeling
Top View Marking on SOT-363 package
(for example W1s)
corresponds to pin 1 of device
Position in tape: pin 1
opposite of feed hole side
Type Marking Pin Configuration Package
BCR08PN WFs 1=E1 2=B1 3=C2 4=E2 5=B2 6=C1 SOT363
Maximum Ratings for NPN and PNP Types
Parameter Symbol Value Unit
Collector-emitter voltage VCEO 50 V
Collector-base voltage VCBO 50
Input forward voltage Vi(fwd) 20
Input reverse voltage Vi(rev) 5
DC collector current IC100 mA
Total power dissipation, TS = 115 °C Ptot 250 mW
Junction temperature Tj150 °C
Storage temperature Tstg -65 ... 150
Thermal Resistance
Junction - soldering point2) RthJS ≤ 140 K/W
1Pb-containing package may be available upon special request
2For calculation of RthJA please refer to Application Note Thermal Resistance
http://store.iiic.cc/