OCTOBER 2008
DSC-6109/0A
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
1
18Mb Pipelined
QDR™II SRAM
Burst of 2
IDT71P72804
IDT71P72604
Description
The IDT QDRIITM Burst of two SRAMs are high-speed synchro-
nous memories with independent, double-data-rate (DDR), read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput, with two data items passed
with each read or write. Four data word transfers occur per clock
cycle, providing quad-data-rate (QDR) performance. Comparing this
with standard SRAM common I/O (CIO), single data rate (SDR) de-
vices, a four to one increase in data access is achieved at equivalent
clock speeds. Considering that QDRII allows clock speeds in excess of
standard SRAM devices, the throughput can be increased well beyond
four to one in most applications.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.
The QDRII has a single DDR address bus with multiplexed read
and write addresses. All read addresses are received on the first half of
the clock cycle and all write addresses are received on the second half
of the clock cycle. The read and write enables are received on the first
half of the clock cycle. The byte and nibble write signals are received on
both halves of the clock cycle simultaneously with the data they are
controlling on the data input bus.
Functional Block Diagram
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 2 signal lines for x18, and 4r signal lines for x36.
4) Represents 36 signal lines for x18, and 72 signal lines for x36.
ADD
REG
CTRL
LOGIC
CLK
GEN
(Note2)
SA
R
W(Note3)
BWx
K
K
C
C
SELECT OUTPUT CONTROL
WRITE/READDECODE
SENSEAMPS
OUTPUTREG
OUTPUTSELECT
WRITE DRIVER
(Note4)
(Note2)
CQ
Q
(Note1)
(Note4)
18M
MEMORY
ARRAY
CQ
DATA
REG (Note1)
(Note1)
6109 drw 16
DATA
REG
(Note1)
D
Features
◆18Mb Density (1Mx18, 512kx36)
◆Separate, Independent Read and Write Data Ports
- Supports concurrent transactions
◆Dual Echo Clock Output
◆2-Word Burst on all SRAM accesses
◆DDR (Double Data Rate) Multiplexed Address Bus
- One Read and One Write request per clock cycle
◆DDR (Double Data Rate) Data Buses
- T wo word burst data per clock on each port
- Four word transfers per clock cycle (2 word bursts
on 2 ports)
◆Depth expansion through Control Logic
◆HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V .
◆Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V .
- Output Impedance adjustable from 35 ohms to 70
ohms
◆Commercial and Industrial Temperature Ranges
◆1.8V Core V oltage (VDD)
◆165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
◆JT AG Interface
6.422
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Clocking
The QDRII SRAM has two sets of input clocks, namely the K, K
clocks and the C, C clocks. In addition, the QDRII has an output “echo”
clock, CQ, CQ.
The K and K clocks are the primary device input clocks. The K clock
is, used to clock in the control signals (R, W and BWx), the read ad-
dress, and the first word of the data burst during a write operation. The
K clock is used to clock in the control signals (BWx), write address and
the second word of the data burst during a write operation. The K and
K clocks are also used internally by the SRAM. In the event that the user
disables the C and C clocks, the K and K clocks will also be used to clock
the data out of the output register and generate the echo clock. The C
and C clocks may be used to clock the data out of the output register
during read operations and to generate the echo clocks. C and C must
be presented to the SRAM within the timing tolerances. The output data
from the QDRII will be closely aligned to the C and C input, through the
use of an internal DLL. When C is presented to the QDRII SRAM, the
DLL will have already internally clocked the first data word to arrive at
the device output simultaneously with the arrival of the C clock.
The C clock and second data word of the burst will also correspond.
Single Clock Mode
The QDRII SRAM may be operated with a single clock pair . C and
C may be disabled by tying both signals high, forcing the outputs and
echo clocks to be controlled instead by the K and K clocks.
DLL Operation
The DLL in the output structure of the QDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low . With the DLL off, the C and C (or K and K
if C and C are not used) will directly clock the output register of the
SRAM. With the DLL off, there will be a propagation delay from the time
the clock enters the device until the data appears at the output.
The QDRII has echo clocks, which provide the user with a clock that
is precisely timed to the data output, and tuned with matching impedance
and signal quality. The user can use the echo clock for downstream
clocking of the data. Echo clocks eliminate the need for the user to
produce alternate clocks with precise timing, positioning, and signal quali-
ties to guarantee data capture. Since the echo clocks are generated by
the same source that drives the data output, the relationship to the data is
not significantly affected by voltage, temperature and process, as would
be the case if the clock were generated by an outside source.
All interfaces of the QDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
The device is capable of sustaining full bandwidth on both the input
and output ports simultaneously. All data is in two word bursts, with
addressing capability to the burst level.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
QDRII devices internally store the two words of the burst as a single,
wide word and will retain their order in the burst. There is no ability to
address to the single word level or reverse the burst order; however, the
byte and nibble write signals can be used to prevent writing any indi-
vidual bytes, or combined to prevent writing one word of the burst.
Read operations are initiated by holding the read port select (R) low ,
and presenting the read address to the address port during the rising
edge of K which will latch the address. The data will then be read and will
appear at the device output at the designated time in correspondence
with the C and C clocks.
Write operations are initiated by holding the write port select (W) low
and designating with the Byte Write inputs (BWx) which bytes are to be
written. The first word of the data must also be present on the data input
bus D[X:0]. Upon the rising edge of K the first word of the burst will be
latched into the input register . After K has risen, and the designated hold
times observed, the second half of the clock cycle is initiated by present-
ing the write address to the address bus SA[X:0], the BWx inputs for the
second data word of the burst, and the second data item of the burst to the
data bus D[X:0]. Upon the rising edge of K, the second word of the burst
will be latched, along with the designated address. Both the first and
second words of the burst will then be written into memory as designated
by the address and byte write enables.
Output Enables
The QDRII SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
6.42
3
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Symbol Pin Function Description
D[X:0] Input
Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations
1M x 18 -- D[17: 0]
512K x 36 -- D[35:0]
BW
0
, BW
1
BW
2
, BW
3
Input
Synchronous
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K
clocks during write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data.
Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
1M x 18 -- BW
0
co ntro ls D[8:0] and BW
1
c o ntro l s D[ 17 :9]
512K x 36 -- BW
0
c o ntro l s D[ 8: 0] , BW
1
co ntro ls D[17:9], BW
2
co ntro ls D[26:18] and BW
3
c on tro l s D[ 35 : 27]
SA Input
Synchronous
Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write
addresses are sampled on the rising edge of K clock during active write operations. These address inputs are
multiplexed, so that both a read and write operation can occur on the same clock cycle. These inputs are ignored when
the appropriate port is deselected.
Q[X:0] Output
Synchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising
edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the
Read port is deselected, Q[X:0] are automatically three-stated.
WInput
Synchronous
Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write
operation in initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause
D[X:0] to be ignore d.
RInput
Synchronous
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read
operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is
allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock.
Each read access consists of a burst of two sequential transfer.
CInp ut Cl o ck Po s iti ve Outp ut Clo c k Inp ut. C is us e d i n co nj unc tio n with C to clock out the Read data from the device. C and C c an b e
used together to deskew the flight times of various devices on the board back to the controller. See application example
fo r furthe r de tail s .
CInp ut Cl o ck Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can
be used together to deskew the flight times of various devices on the board back to the controller. See application
example for further details.
K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out
data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
KInput Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data
through Q[X:0] when in single clock mode.
CQ, CQ Outp ut Clock Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs
and can be used as a data valid indication. These signals are free running and do not stop when the output data is tri-
stated.
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance.
Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this
pin can be connected directly to V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected
directly to GND or left unconnected.
6109 tbl 02a
Pin Definitions
6.424
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Symbol Pin Function Description
Doff Input
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be
diffe rent from those listed in this data shee t. There will be an increased propagation de lay from the incid ence of C and C
to Q, or K and K to Q as configured. The propagation delay is not a tested parameter, but will be similar to the
propagation delay of other SRAM devices in this speed grade.
TDO Output TDO pin for JTAG
TCK In p ut TCK pi n for JTA G .
TDI Inp ut TDI p in fo r J TA G. An inte rnal re s is to r wil l p ull TDI to V
DD
when the pin is unconnected.
TMS Input TMS pin for JTAG. An internal resistor will pull TMS to V
DD
when the pin is unconnected.
NC No Connect No connects inside the package. Can be tied to any voltage level
V
REF
Input
Reference Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC
measurement points.
V
DD
Power
Supply Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
V
SS
Ground Ground for the device. Should be connected to ground of the system.
V
DDQ
Power
Supply Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the
desired output voltage.
6109 tbl 02b
Pin Definitions continued
6.42
5
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Pin Configuration IDT71P72804 (1M x 18)
165-ball FBGA Pinout
TOP VIEW
1234567891011
ACQ V
SS/
SA
(3)
NC/
SA
(1)
WBW
1
KNC RSA V
SS
/
SA
(2)
CQ
BNC Q
9
D
9
SA NC K BW
0
SA NC NC Q
8
CNC NC D
10
V
SS
SA SA SA V
SS
NC Q
7
D
8
DNC D
11
Q
10
V
SS
V
SS
V
SS
V
SS
V
SS
NC NC D
7
ENC NC Q
11
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
NC D
6
Q
6
FNC Q
12
D
12
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC NC Q
5
GNC D
13
Q
13
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC NC D
5
HDoff V
REF
V
DDQ
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
REF
ZQ
JNC NC D
14
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC Q
4
D
4
KNC NC Q
14
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC D
3
Q
3
LNC Q
15
D
15
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
NC NC Q
2
MNC NC D
16
V
SS
V
SS
V
SS
V
SS
V
SS
NC Q
1
D
2
NNC D
17
Q
16
V
SS
SA SA SA V
SS
NC NC D
1
PNC NC Q
17
SA SA C SA SA NC D
0
Q
0
RTDO TCK SA SA SA CSA SA SA TMS TDI
6109 tb l 12b
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72804) devices.
3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72 804) devices.
6.426
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Pin Configuration IDT71P72604 (512K x 36)
165-ball FBGA Pinout
TOP VIEW
1234567891011
ACQ V
SS/
SA
(4)
NC/
SA
(2)
WBW
2
KBW
1
RNC/
SA
(1)
V
SS/
SA
(3)
CQ
BQ
27
Q
18
D
18
SA BW
3
KBW
0
SA D
17
Q
17
Q
8
CD
27
Q
28
D
19
V
SS
SA SA SA V
SS
D
16
Q
7
D
8
DD
28
D
20
Q
19
V
SS
V
SS
V
SS
V
SS
V
SS
Q
16
D
15
D
7
EQ
29
D
29
Q
20
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
Q
15
D
6
Q
6
FQ
30
Q
21
D
21
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
D
14
Q
14
Q
5
GD
30
D
22
Q
22
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
13
D
13
D
5
HDoff V
REF
V
DDQ
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
REF
ZQ
JD
31
Q
31
D
23
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
D
12
Q
4
D
4
KQ
32
D
32
Q
23
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
12
D
3
Q
3
LQ
33
Q
24
D
24
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
D
11
Q
11
Q
2
MD
33
Q
34
D
25
V
SS
V
SS
V
SS
V
SS
V
SS
D
10
Q
1
D
2
ND
34
D
26
Q
25
V
SS
SA SA SA V
SS
Q
10
D
9
D
1
PQ
35
D
35
Q
26
SA SA C SA SA Q
9
D
0
Q
0
RTDO TCK SA SA SA CSA SA SA TMS TDI
6109 tb l 12c
NOTES:
1. A9 is reserved for the 36Mb expansion address.
2. A3 is reserved for the 72Mb expansion address.
3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604)
devices.
4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604)
devices.
6.42
7
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Absolute Maximum Ratings(1) (2) Capacitance (TA = +25°C, f = 1.0MHz)(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
NOTE:
1. Tested at characterization and retested after any design or process
change that may affect these parameters.
Symbol Parameter Conditions Max. Unit
C
IN
Input Capacitance V
DD
= 1.8V
V
DDQ
= 1.5V
5pF
C
CLK
Clock Input Capacitance 6 pF
C
O
Output Capacitance 7 pF
6109 tbl 06
Symbol Rating Value Unit
V
TERM
Supply Voltage on V
DD
with
Re s p e ct to GND –0.5 to +2.9 V
V
TERM
Supply Voltage on V
DDQ
with
Re s p e ct to GND –0.5 to V
DD
+0.3 V
V
TERM
Vo lta g e o n Inp ut te rmi nals with
re s p e ct to GND. –0.5 to V
DD
+0.3 V
V
TERM
Voltage on Output and I/O
te rminal s wi th re sp e c t to GND. -0.5 to V
DDQ
+0.3 V
T
BIAS
Temperature Under Bias –55 to +125 °C
T
STG
Storage Temperature –65 to +150 °C
I
OUT
Continuous Current i nto Outputs + 20 mA
6109 tbl 05
Recommended DC Operating and
Temperature Conditions
NOTES:
1) All byte write (BWx) signals are sampled on
the rising edge of K and again on K. The data that is present on the
data bus in the designated byte will be latched into the input if
the corresponding BWx is held low . The rising edge of K will
sample the first byte of the two word burst and the rising edge
of K will sample the second byte of the two word burst.
2) The availability of the BWx on designated devices is de
scribed in the pin description table.
3) The QDRII Burst of two SRAM has data forwarding. A read request
that is initiated on the same cycle as a write request to the same
address will produce the newly written data in response to the read
request.
Signal BW
0
BW
1
BW
2
BW
3
Write Byte 0 L X X X
Write Byte 1 X L X X
Write Byte 2 X X L X
Write Byte 3 X X X L
6109 tb l 09
Write Descriptions(1,2,3)
Symbol Parameter Min. Typ. Max. Unit
VDD Powe r Supp ly Vo ltage 1.7 1. 8 1.9 V
VDDQ I/O S up p ly Vo ltag e 1. 4 1. 5 VDD V
VSS Ground 0 0 0 V
VREF Input Refe renc e Vo l tag e 0. 68 V DDQ/2 0.95 V
TAAmbient
Temperature (1)
Comme rcial 0 to + 70
o
c
Ind us tri al -40 to +85
o
c
6109 tb l 04
NOTE:
1. During production testing, the case temperature equals the ambient
temperature.
6.428
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Application Example
SRAM #1
SA WBW
0
BW
1
C
Q
ZQ 250
Ω
R
D
K
K
C
Data In
R
MEMORY
CONTROLLER
Return CLK
Source CLK
Return CLK
Source CLK R=50Ω
R
V
T
=V
REF
R
6109 drw 20
V
T
V
T
W
Address
Data Out
R
V
T
R
V
T
R
SRAM #4
SA WBW
0
BW
1
C
Q
ZQ 250
Ω
R
D
K
K
C
R
R
R
BWx
6.42
9
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter Symbol Test Conditions Min Max Unit Note
Input Leakag e Curre nt I
IL
V
DD
= Max V
IN
= V
SS
to V
DDQ
-2 +2 µA
O utp ut L e akage Cu rre n t I
OL
Output Disabled -2 +2 µA
Com'l Ind
Operating Current
(x 36): DDR I
DD
V
DD
= Max,
I
OUT
= 0mA (outputs open),
Cycle Time > t
KHKH
Min
200MH
Z
-950 1000 mA 1
167MH
Z
-850 900
Operating Current
(x 18): DDR I
DD
V
DD
= Max,
I
OUT
= 0mA (outputs open),
Cycle Time > t
KHKH
Min
250MH
Z
-850-
mA 1,8200MH
Z
-750800
167MH
Z
-650700
Stand b y Curre nt: NOP I
SB1
Device Deselected (in NOP state),
Io ut = 0mA (outputs o pen),
f=Max,
All Inputs <0.2V or > V DD -0. 2V
250MH
Z
-375-
mA 2,8200MH
Z
-335385
167MH
Z
-300350
O utp ut Hi gh Vo l tage V
OH1
RQ = 25 0Ω, I
OH
= -15mA V
DDQ
/2-0.12 V
DDQ
/2+0.12 V 3,7
O utp ut L o w Voltage V
OL1
RQ = 25 0Ω, I
OL
= 15mA V
DDQ
/2-0.12 V
DDQ
/2+0.12 V 4,7
O utp ut Hi gh Vo l tage V
OH2
I
OH
= -0.1mA V
DDQ
-0.2 V
DDQ
V5
O utp ut L o w Voltage V
OL2
I
OL
= 0.1mA V
SS
0.2 V 6
6109 tb l 10c
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
8. Industrial temperature range is not available for the 250MHz speed grade.
6.4210
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Input Electrical Characteristics Over
the Operating Temperature and
Supply Voltage Range
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter Symbol Min Max Unit Notes
Inp ut H ig h Vo l tag e , DC V
IH
(DC
)V
REF
+0.1 V
DDQ
+0.3 V 1,2
Input Low Voltage, DC V
IL
(DC)
-0.3 V
REF
-0. 1 V 1, 3
Inp ut H ig h Vo l tag e , AC V
IH
(AC)
V
REF
+0.2 - V 4,5
Input Low Voltage, AC V
IL (AC)
-V
REF
-0. 2 V 4, 5
6109 tb l 10d
NOTES:
1.These are DC test criteria. DC design criteria is VREF + 50mV. The
AC VIH/VIL levels are defined separately for measuring timing param
eters.
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse
width <20% tKHKH (min))
3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20%
tKHKH (min))
4. This conditon is for AC function test only , not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through the
target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the
target DC level, VIL(DC) or VIH(DC)
V
SS
V
IH
V
SS
-0.25V
V
SS
-0.5V
20% tKHKH (MIN)
6109 drw 2
2
V
IL
V
DD
V
DD
+0.25
V
DD
+0.5
2
0
%
t
K
H
K
H
(
I
N
)
6109drw 2
1
Overshoot Timing
Undershoot Timing
6.42
11
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
AC Test Load
Device
R
L
=50
Ω
Z
0
=50
Ω
V
DDQ
/2
Under
Test
V
REF
OUTPUT
6109 drw 04
ZQ R
Q
=250
Ω
DDQ
/2
V
Parameter Symbol Value Unit
Co re P o we r S up p l y Vo l tag e V
DD
1. 7 to 1. 9 V
I/O Power Supply Vo ltage V
DDQ
1.4 to V
DD
V
Input High Level V
IH
(V
DDQ
/2)+ 0.5 V
Input Lo w Le v e l V
IL
(V
DDQ
/2)- 0. 5 V
In pu t R efer en ce Level V R EF V
DDQ
/2 V
Input Rise /Fall Time TR/TF 0.3/0.3 ns
Outp ut Timing Re fe renc e Leve l V
DDQ
/2 V
6109tb l 11a
AC Test Conditions(1)
NOTE:
1. Parameters are tested with RQ=250Ω
(
V
DDQ
/2) + 0.5V
(V
DDQ
/2) - 0.5V
6109 drw 06
V
DDQ
/2 V
DDQ
/2Test points
Input Waveform
Output Waveform
6109 drw 06a
V
DDQ
/2 V
DDQ
/2Test points
6.4212
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
AC Electrical Characteristics
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, Commercial and Industrial Temperature Ranges)
(3,7)(3,7)
(3,7)(3,7)
(3,7)
Symbol Parameter
250MHz
(10,11)
200MHz 167MHz
Unit Notes
Min. Max Min. Max Min. Max
Clock P aram eters
t
KHKH
Clo c k Cy cl e Ti me (K,K,C,C)4.00 6.30 5.00 7.88 6.00 8.40 ns
t
KC var
Clock Phase Jitter (K,K,C,C) - 0.20 - 0.20 - 0.20 ns 1,5
t
KHKL
Clo c k Hig h Tim e (K, K,C,C)1.60 - 2.00 - 2.40 - ns 8
t
KLKH
Clo c k LOW Tim e (K, K,C,C)1.60 - 2.00 - 2.40 - ns 8
t
KHKH
Clo c k to clock (K →K,C→C)1.80 - 2.20 - 2.70 - ns 9
t
KHKH
Clock to clock (K→K,C→C) 1.80 - 2.20 - 2.70 - ns 9
t
KHCH
Clock to data clock (K→C,K→C)0.00 1.80 0.00 2.30 0.00 2.80 ns
t
KC lock
DLL l oc k tim e (K, C) 1024 -1024-1024-cycles2
t
KC reset
K s tatic to DLL re se t 30 -30-30-ns
Output Param eters
t
CHQV
C,C HIG H to ou tp ut v al id -0.45 - 0.45 - 0.50 ns 3
t
CHQX
C,C HIG H to ou tp ut hol d -0.45 - -0.45 - -0.50 - ns 3
t
CHCQV
C,C HIGH to echo clock valid -0.45 - 0.45 - 0.50 ns 3
t
CHCQX
C,C HIGH to echo clock hold -0.45 - -0.45 - -0.50 - ns 3
t
CQHQV
CQ,CQ HIGH to output valid -0.30 - 0.35 - 0.40 ns
t
CQHQX
CQ,CQ HIGH to output hol d -0.30 - -0.35 - -0.40 - ns
t
CHQZ
C HIGH to output High-Z -0.45 - 0.45 - 0.50 ns 3,4,5
t
CHQX1
C HIGH to output Low-Z -0.45 - -0.45 - -0.50 - ns 3,4,5
Set-Up Times
t
AVKH
Address valid to K,K rising edge 0.35 - 0.40 - 0.50 - ns 6
t
IVKH
R, W i n p uts vali d to K , K rising edge 0.35 - 0.40 - 0.50 - ns
t
DVKH
Data-in and BWx v alid to K, K rising edge 0.35 - 0.40 - 0.50 - ns
Hol d Ti m es
t
KHAX
K,K rising edge to address hold 0.35 - 0.40 - 0.50 - ns 6
t
KHIX
K,K rising edge to R, W inp uts hold 0.35 - 0.40 - 0.50 - ns
t
KHDX
K, K rising edge to data-in and BWx hold 0.35 - 0.40 - 0.50 - ns
6109 tb l 11
NOTES:
1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals T A.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
10. The 250MHz speed grade is not available in the 512K x 36-bit option.
1 1. Industrial temperature range is not available for the 250MHz speed grade.
6.42
13
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Timing Waveform of Combined Read and Write Cycles
6109 drw 09a
K
K
123
R
SA
Q
tKHCH
tKHKL
tKHIX
tIVKH
tKHAXtAVKH
C
C
CQ
CQ
tCHQX
tCHQX1
tKLKH
tCHCQV
tCHCQX
W
D
tKHDXtDVKH
45678910
tKLKH tKHKH tKHKH
A0 A3A2
A1 A4 A5 A6
tKHAX
tAVKH
D10 D11 D30 D31 D50 D51 D60 D61
tKHDXtDVKH
Q00 Q01 Q20 Q21 Q40 Q41
tCHQZ
tCHQV tCHQV
tCHQX tCQHQV
tKHCH
tKHKL
tKHKHtKHKH
tCHCQX
tCHCQV
Read A0 Write A1 Read A2 Read A4 NOP NOP NOPWrite A3 Write A5 Write A6
tCQHQX
6.4214
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
This part contains an IEEE standard 1 149.1 Compatible Test Ac-
cess Port (T AP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturing and system diagnostics. In conformance with IEEE 1 149.1,
the SRAM contains a T AP controller , Instruction register, Bypass Regis-
ter and ID register . The T AP controller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
JTAG Block Diagram JTAG Instruction Coding
IR2 IR1 IR0 Instruction TDO Output Notes
0 0 0 EXTEST Boundary Scan Register
0 0 1 IDCODE Ide n ti fic a tion r e g i s te r 2
0 1 0 SAMPLE-Z Boundary Scan Register 1
0 1 1 RESERVED Do Not Use 5
1 0 0 SAMPLE/PRELOAD Boundary Scan register 4
1 0 1 RESERVED Do Not Use 5
1 1 0 RESERVED Do Not Use 5
1 1 1 BYPASS Bypass Re gister 3
6109tbl 13
NOTES:
1. Places Qs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
3. Bypass register is initialized to Vss when BYP ASS instruction is in
voked. The Bypass Register also holds serially loaded TDI when
exiting the Shift DR states.
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
TAP Controller State Diagram
Test Logic Reset
Run Test Idle Select DR
Capture DR
Pause DR
Exit 2 DR
Update DR
Shift DR
Exit 1 DR
Select IR
Capture IR
Pause IR
Exit 2 IR
Update IR
Shift IR
Exit 1 IR
0
0
0
0
0
0
1
1
1
1
1
1
1
0
6109 drw 17
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg
.
Control Signal
s
TAP Controller
A,D
K,K
C,C
Q
CQ
CQ
TDI
TMS
TCK
TD
O
6109 drw 18
S
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
required. It is possible to use this device without utilizing the TAP. To
disable the T AP controller without interfacing with normal operation of the
SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor . TDO should be left unconnected.
6.42
15
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Part Instruction Register Bypass Regi ster I D Register Boundary Scan
512Kx36 3 bi ts 1 bi t 32 bi ts 107 bi ts
1Mx18 3 bi ts 1 bi t 32 bits 107 bits
6109 tbl 14
INSTRUCTION FIELD AL L DE VI CE S DESCRIPTION PART NUM BE R
Revision Number (31:29) 0x0 Revision Number
Device ID (28:12) 0x0284
0x0285 512Kx36 QDRII Burst of 2
1Mx18 71P72604S
71P72804S
IDT JEDEC ID CODE (11:1) 0x033 Allows unique identification of SRAM
vendor.
ID Register Presence
In d i c ator (0) 1Indicates the presence of an ID register.
6109 tbl 15
Scan Register Definition
Identification Register Definitions
6.4216
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Boundary Scan Exit Order
ORDER PI N ID
16R
26P
36N
47P
57N
67R
78R
88P
99R
10 11P
11 10P
12 10N
13 9P
14 10M
15 11N
16 9M
17 9N
18 11L
19 11M
20 9L
21 10L
22 11K
23 10K
24 9J
25 9K
26 10J
27 11J
28 11H
29 10G
30 9G
31 11F
32 11G
33 9F
34 10F
35 11E
36 10E
6109 tbl 16
ORDER PI N ID
37 10D
38 9E
39 10C
40 11D
41 9C
42 9D
43 11B
44 11C
45 9B
46 10B
47 11A
48 Internal
49 9A
50 8B
51 7C
52 6C
53 8A
54 7A
55 7B
56 6B
57 6A
58 5B
59 5A
60 4A
61 5C
62 4B
63 3A
64 1H
65 1A
66 2B
67 3B
68 1C
69 1B
70 3D
71 3C
72 1D
6109 tb l 17
ORDER PIN ID
73 2C
74 3E
75 2D
76 2E
77 1E
78 2F
79 3F
80 1G
81 1F
82 3G
83 2G
84 1J
85 2J
86 3K
87 3J
88 2K
89 1K
90 2L
91 3L
92 1M
93 1L
94 3N
95 3M
96 1N
97 2M
98 3P
99 2N
100 2P
101 1P
102 3R
103 4R
104 4P
105 5P
106 5N
107 5R
6109 tbl 18
6.42
17
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Parameter Symbol Min Typ Max Unit Note
I/O Power Supply V
DDQ
1.4 - V
DD
V
Power Supp ly Voltag e V
DD
1.7 1.8 1.9 V
In p u t Hi g h L e v el V
IH
1.3 - V
DD
+0.3 V
In p u t Low Lev el V
IL
-0.3 - 0.5 V
TCK Input Le akag e Curre nt I
IL
-5 - +5 µA
TMS, TDI Input Leakage Current I
IL
-15 - +15 µA
TDO Outp ut Le akag e Curre nt I
0L
-5 - +5 µA
Output High Voltage (I
OH
= -1mA) V
OH
V
DDQ -
0.2 - V
DDQ
V1
Outp ut Low Vo ltag e (I
OL
= 1mA) V
OL
V
SS
-0.2V1
6109 tbl 19
Parameter Symbol Value Unit Note
In p ut Hi g h L e v el V
IH
1.8 V
In p ut L o w L e v e l V
IL
0V
Input Rise/ Fall Time TR/TF 1.0/1.0 ns
Input and Outp ut Timing Re fere nce Le ve l 0.9 V 1
6109 tb l 20
JTAG DC Operating Conditions
JTAG AC Test Conditions
NOTE:
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external
resistor connected to ZQ.
NOTE:
1. For SRAM outputs see AC test load on page 11.
JTAG Input Test WaveForm
JTAG Output Test WaveForm
JTAG AC Test Load
6109 drw 23
0.9 V 0.9 VTest points
1
.8 V
0V
6109 drw 23a
0.9 V 0.9 VTest points
0.9 V
50Ω
T
DO Z
0
=50Ω
6109 drw 24
,
6.4218
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Parameter Symbol Min Max Unit Note
TC K C ycl e T i m e t
CHCH
50 - ns
TCK High Pulse Width t
CHCL
20 - ns
TCK Lo w Pulse Width t
CLCH
20 - ns
TMS Input Setu p Ti me t
MVCH
5-ns
TM S In p u t Hol d Ti m e t
CHMX
5-ns
TDI Inp u t S e tup Tim e t
DVCH
5-ns
TDI Inp u t Ho l d Ti me t
CHDX
5-ns
SRAM Inp ut Setup Time t
SVCH
5-ns
SRAM Inp ut Ho ld Time t
CHSX
5-ns
Cl o c k Low to O utput
Valid t
CLQV
010ns
6109 tb l .2 1
JTAG AC Characteristics
JTAG Timing Diagram
TCK
TMS
TDI/
SRAM
Inputs
TDO
t
MVCH
t
DVCH
t
SVCH
t
CHCL
t
CHMX
t
CHDX
t
CHSX
t
CLCH
6109 drw 19
t
CLQV
S
RAM
O
utputs
t
CHCH
6.42
19
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.4220
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Commercial and IndustrialTemperature Range
18 Mb QDR II SRAM Burst of 2
Ordering Information
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
S
Power
XXX
Speed
BQ
Package
BQ
71P72XXX
250
(1,2)
200
167
6109 drw 15
Device
Type
165 Fine Pitch Ball Grid Array (fBGA)
Clock Frequency in MegaHertz
IDT71P72804 1M x 18 QDR II SRAM Burst of 2
IDT71P72604 512K x 36 QDR II SRAM Burst of 2
X
Process
Temperature
Range
Commercial (0oCto+70
oC)
Blank
Notes:
1) The 250MHz speed grade is not available in the 512K x36-bit option.
2) Industrial temperature range is not available for the 250MHz speed grade.
Restricted Hazardous Substance Device
G
X
IIndustrial (-40oCto+85
oC)
CORPORA TE HEADQUARTERS for SALES: for T ech Support:
6024 Silver Creek V alley Road 800-345-7015 or sramhelp@idt.com
San Jose, CA 95138 408-284-8200 408-284-4532
fax: 408-284-2775
www.idt.com
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18 x -Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Revision History
REVISION DATE PAGES DESCRIPTION
0 07/20/05 p.1-22 Released Final datasheet
A 04/21/06 p.1-3,7-9 Removed x8 and x9 information from the datasheet.
12,15,20
p. 7,11,17 Clarified Max VDDQ equals VDD.
p.1,7,9,12,20 Added Industrial temperature to the datasheet.
p.20 Added Green to the datasheet “Restricted hazardous substance device”
B 10/13/08 p.20 Removed "IDT" from orderable part number